+2017-07-18 Nick Clifton <nickc@redhat.com>
+
+ PR 21775
+ * coff-sh.c: Fix spelling typos.
+ * compress.c: Likewise.
+ * cpu-pdp11.c: Likewise.
+ * ecofflink.c: Likewise.
+ * elf-m10300.c: Likewise.
+ * elf.c: Likewise.
+ * elf32-arm.c: Likewise.
+ * elf32-m68k.c: Likewise.
+ * elf32-nds32.c: Likewise.
+ * elf32-ppc.c: Likewise.
+ * elf32-sh.c: Likewise.
+ * elf32-v850.c: Likewise.
+ * elf64-ppc.c: Likewise.
+ * elf64-x86-64.c: Likewise.
+ * elflink.c: Likewise.
+ * elfnn-aarch64.c: Likewise.
+ * elfxx-mips.c: Likewise.
+ * som.c: Likewise.
+ * sunos.c: Likewise.
+ * vms-alpha.c: Likewise.
+ * xcofflink.c: Likewise.
+
2017-07-18 Nick Clifton <nickc@redhat.com>
PR binutils/21781
contents = coff_section_data (abfd, sec)->contents;
- /* The deletion must stop at the next ALIGN reloc for an aligment
+ /* The deletion must stop at the next ALIGN reloc for an alignment
power larger than the number of bytes we are deleting. */
irelalign = NULL;
if (orig_compression_header_size == 0)
{
/* Convert it from .zdebug* section. Get the uncompressed
- size first. We need to substract the 12-byte overhead in
+ size first. We need to subtract the 12-byte overhead in
.zdebug* section. Set orig_compression_header_size to
the 12-bye overhead. */
orig_compression_header_size = 12;
0, /* only 1 machine */
"pdp11",
"pdp11",
- 1, /* aligment = 16 bit */
+ 1, /* alignment = 16 bit */
TRUE, /* the one and only */
bfd_default_compatible,
bfd_default_scan,
if (! bfd_link_relocatable (info))
{
- /* When are are hashing strings, we lie about the number of
+ /* When we are hashing strings, we lie about the number of
strings attached to each FDR. We need to set cbSs
because some versions of dbx apparently use it to decide
how much of the string table to read in. */
if (ELF32_R_TYPE ((irelend - 1)->r_info) == (int) R_MN10300_ALIGN)
--irelend;
- /* The deletion must stop at the next ALIGN reloc for an aligment
+ /* The deletion must stop at the next ALIGN reloc for an alignment
power larger than, or not a multiple of, the number of bytes we
are deleting. */
for (; irel < irelend; irel++)
else
adjustment = vma_offset - off_offset;
- which can can be collapsed into the expression below. */
+ which can be collapsed into the expression below. */
static file_ptr
vma_page_aligned_bias (bfd_vma vma, ufile_ptr off, bfd_vma maxpagesize)
if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
{
_bfd_error_handler
- (_("%B has has both the current and legacy "
+ (_("%B has both the current and legacy "
"Tag_MPextension_use attributes"),
ibfd);
result = FALSE;
struct
{
/* Offset from the start of .got section. To calculate offset relative
- to GOT pointer one should substract got->offset from this value. */
+ to GOT pointer one should subtract got->offset from this value. */
bfd_vma offset;
/* Pointer to the next GOT entry for this global symbol.
of instruction a time.
It recognizes three types of relocations.
- 1. R_NDS32_LABEL - a aligment.
+ 1. R_NDS32_LABEL - a alignment.
2. R_NDS32_INSN16 - relax a 32-bit instruction to 16-bit.
3. is_16bit_NOP () - remove a 16-bit instruction. */
- /* TODO: It seems currently implementation only support 4-byte aligment.
- We should handle any-aligment. */
+ /* TODO: It seems currently implementation only support 4-byte alignment.
+ We should handle any-alignment. */
Elf_Internal_Rela *insn_rel = NULL, *label_rel = NULL, *irel;
Elf_Internal_Rela *tmp_rel, *tmp2_rel = NULL;
#define VXWORKS_PLT_NON_JMP_SLOT_RELOCS 3
/* The number of relocations in the PLTResolve slot. */
#define VXWORKS_PLTRESOLVE_RELOCS 2
-/* The number of relocations in the PLTResolve slot when when creating
+/* The number of relocations in the PLTResolve slot when creating
a shared library. */
#define VXWORKS_PLTRESOLVE_RELOCS_SHLIB 0
contents = elf_section_data (sec)->this_hdr.contents;
- /* The deletion must stop at the next ALIGN reloc for an aligment
+ /* The deletion must stop at the next ALIGN reloc for an alignment
power larger than the number of bytes we are deleting. */
irelalign = NULL;
{
_bfd_error_handler
/* xgettext:c-format */
- (_("error: %B needs 8-byte aligment but %B is set for 4-byte alignment"),
+ (_("error: %B needs 8-byte alignment but %B is set for 4-byte alignment"),
ibfd, obfd);
result = FALSE;
}
the values of any global symbols in a toc section that has been
edited. Globals in toc sections should be a rarity, so this function
sets a flag if any are found in toc sections other than the one just
- edited, so that futher hash table traversals can be avoided. */
+ edited, so that further hash table traversals can be avoided. */
struct adjust_toc_info
{
/* Merge the used and skip arrays. Assume that TOC
doublewords not appearing as either used or unused belong
- to to an entry more than one doubleword in size. */
+ to an entry more than one doubleword in size. */
for (drop = skip, keep = used, last = 0, some_unused = 0;
drop < skip + (toc->size + 7) / 8;
++drop, ++keep)
};
/* The first entry in the x32 IBT-enabled lazy procedure linkage table
- is the the same as the normal lazy PLT. Subsequent entries for an
+ is the same as the normal lazy PLT. Subsequent entries for an
x32 IBT-enabled lazy procedure linkage table look like this. */
static const bfd_byte elf_x32_lazy_ibt_plt_entry[LAZY_PLT_ENTRY_SIZE] =
case R_X86_64_GOTPCREL64:
/* Use global offset table entry as symbol value. */
case R_X86_64_GOTPLT64:
- /* This is obsolete and treated the the same as GOT64. */
+ /* This is obsolete and treated the same as GOT64. */
base_got = htab->elf.sgot;
if (htab->elf.sgot == NULL)
bfd_vma mask;
asection *sec = h->root.u.def.section;
- /* The section aligment of definition is the maximum alignment
+ /* The section alignment of the definition is the maximum alignment
requirement of symbols defined in the section. Since we don't
know the symbol alignment requirement, we start with the
maximum alignment and check low bits of the symbol address
uint32_t v = 0;
uint32_t opc_v = 0;
- /* Bail out quickly if INSN doesn't fall into the the load-store
+ /* Bail out quickly if INSN doesn't fall into the load-store
encoding space. */
if (!AARCH64_LDST (insn))
return FALSE;
{
/* If this is a dynamic link, we should have created a
_DYNAMIC_LINK symbol or _DYNAMIC_LINKING(for normal mips) symbol
- in in _bfd_mips_elf_create_dynamic_sections.
+ in _bfd_mips_elf_create_dynamic_sections.
Otherwise, we should define the symbol with a value of 0.
FIXME: It should probably get into the symbol table
somehow as well. */
{
asym->section = section;
/* MIPS_TEXT is a bit special, the address is not an offset
- to the base of the .text section. So substract the section
+ to the base of the .text section. So subtract the section
base address to make it an offset. */
asym->value -= section->vma;
}
{
asym->section = section;
/* MIPS_DATA is a bit special, the address is not an offset
- to the base of the .data section. So substract the section
+ to the base of the .data section. So subtract the section
base address to make it an offset. */
asym->value -= section->vma;
}
push (v);
}
else
- /* An operator. Pop two two values from the stack and
+ /* An operator. Pop two values from the stack and
use them as operands to the given operation. Push
the result of the operation back on the stack. */
switch (c)
}
/* This is called for each reloc against an external symbol. If this
- is a reloc which are are going to copy as a dynamic reloc, then
+ is a reloc which are going to copy as a dynamic reloc, then
copy it over, and tell the caller to not bother processing this
reloc. */
fprintf (file, _("OPR_ADD (add)\n"));
break;
case ETIR__C_OPR_SUB:
- fprintf (file, _("OPR_SUB (substract)\n"));
+ fprintf (file, _("OPR_SUB (subtract)\n"));
break;
case ETIR__C_OPR_MUL:
fprintf (file, _("OPR_MUL (multiply)\n"));
tocoff += h->descriptor->u.toc_offset;
/* The first instruction in the glink code needs to be
- cooked to to hold the correct offset in the toc. The
+ cooked to hold the correct offset in the toc. The
rest are just output raw. */
bfd_put_32 (output_bfd,
bfd_xcoff_glink_code(output_bfd, 0) | (tocoff & 0xffff), p);
+2017-07-18 Nick Clifton <nickc@redhat.com>
+
+ PR 21775
+ * coffgrok.c: Fix spelling typos.
+ * readelf.c: Likewise.
+ * stabs.c: Likewise.
+ * testsuite/binutils-all/objcopy.exp: Likewise.
+
2017-07-18 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
case C_UNTAG:
/* Various definition. */
if (top_scope == NULL)
- fatal (_("Aggregate defintion encountered without a scope"));
+ fatal (_("Aggregate definition encountered without a scope"));
i = do_define (i, top_scope);
break;
case C_EXT:
case C_LABEL:
if (file_scope == NULL)
- fatal (_("Label defintion encountered without a file scope"));
+ fatal (_("Label definition encountered without a file scope"));
i = do_define (i, file_scope);
break;
case C_STAT:
case C_AUTO:
case C_REG:
if (top_scope == NULL)
- fatal (_("Variable defintion encountered without a scope"));
+ fatal (_("Variable definition encountered without a scope"));
i = do_define (i, top_scope);
break;
case C_EOS:
error (_("section [%5u] in group section [%5u] > maximum section [%5u]\n"),
entry, i, elf_header.e_shnum - 1);
if (num_group_errors == 10)
- warn (_("Futher error messages about overlarge group section indicies suppressed\n"));
+ warn (_("Further error messages about overlarge group section indicies suppressed\n"));
}
continue;
}
break;
case 'T':
- /* Struct, union, or enum tag. For GNU C++, this can be be followed
+ /* Struct, union, or enum tag. For GNU C++, this can be followed
by 't' which means we are typedef'ing it as well. */
if (*p != 't')
{
}
# Tests that in a debug only copy of a file the sections
-# headers whoes types have been changed to NOBITS still
+# headers whose types have been changed to NOBITS still
# retain their sh_link fields.
proc keep_debug_symbols_and_check_links { prog flags test } {
+2017-07-18 Nick Clifton <nickc@redhat.com>
+
+ PR 21775
+ * config/tc-arm.c: Fix spelling typos.
+ * config/tc-mips.c: Likewise.
+ * config/tc-msp430.c: Likewise.
+ * config/tc-sh64.c: Likewise.
+ * config/tc-tic4x.c: Likewise.
+ * ecoff.c: Likewise.
+ * testsuite/gas/arm/ldr-bad.l: Likewise.
+ * testsuite/gas/arm/ldr-t-bad.l: Likewise.
+ * testsuite/gas/tic54x/opcodes.s: Likewise.
+ * testsuite/gas/msp340/errata_warns.l: Likewise.
+
2017-07-18 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
&& (inst.operands[0].reg == REG_PC
&& inst.operands[1].reg == REG_PC
&& (inst.reloc.exp.X_add_number & 0x3)),
- _("ldr to register 15 must be 4-byte alligned"));
+ _("ldr to register 15 must be 4-byte aligned"));
}
static void
/* We are going to store value (shifted right by two) in the
instruction, in a 24 bit, signed field. Bits 26 through 32 either
all clear or all set and bit 0 must be clear. For B/BL bit 1 must
- also be be clear. */
+ also be clear. */
if (value & temp)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("misaligned branch destination"));
}
/* Try to get a constant expression from the next tokens in ARG. Consume
- the tokens and return return true on success, storing the constant value
+ the tokens and return true on success, storing the constant value
in *VALUE. */
static bfd_boolean
We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
MIPS symbols and associated with BAL instructions as these instructions
- may be be converted to JALX by the linker. */
+ may be converted to JALX by the linker. */
static bfd_boolean
fix_bad_cross_mode_branch_p (fixS *fixP)
case NOP_CHECK_CPU12:
if (silicon_errata_warn & SILICON_ERRATA_CPU12)
- as_warn (_("CPU12: CMP/BIT with PC destinstion ignores next instruction"));
+ as_warn (_("CPU12: CMP/BIT with PC destination ignores next instruction"));
if (silicon_errata_fix & SILICON_ERRATA_CPU12)
doit = TRUE;
|| is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU11)
- as_bad (_("CPU11: PC is destinstion of SR altering instruction"));
+ as_bad (_("CPU11: PC is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
- as_warn (_("CPU11: PC is destinstion of SR altering instruction"));
+ as_warn (_("CPU11: PC is destination of SR altering instruction"));
}
/* If the status register is the destination... */
))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU13)
- as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_bad (_("CPU13: SR is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
- as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_warn (_("CPU13: SR is destination of SR altering instruction"));
}
if (is_opcode ("clr") && bin == 0x4302 /* CLR R2*/)
))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU13)
- as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_bad (_("CPU13: SR is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
- as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_warn (_("CPU13: SR is destination of SR altering instruction"));
}
if (extended_op)
|| is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU11)
- as_bad (_("CPU11: PC is destinstion of SR altering instruction"));
+ as_bad (_("CPU11: PC is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
- as_warn (_("CPU11: PC is destinstion of SR altering instruction"));
+ as_warn (_("CPU11: PC is destination of SR altering instruction"));
}
/* If the status register is the destination... */
))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU13)
- as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_bad (_("CPU13: SR is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
- as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_warn (_("CPU13: SR is destination of SR altering instruction"));
}
if ( (is_opcode ("bic") && bin == 0xc232)
&& (is_opcode ("rra") || is_opcode ("rrc") || is_opcode ("sxt")))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU13)
- as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_bad (_("CPU13: SR is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
- as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_warn (_("CPU13: SR is destination of SR altering instruction"));
}
insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
return (sh64_abi == sh64_abi_64) ? bfd_mach_sh5 : 0;
}
-/* This is MD_PCREL_FROM_SECTION, we we define so it is called instead of
+/* This is MD_PCREL_FROM_SECTION, we define so it is called instead of
md_pcrel_from (in tc-sh.c). */
valueT
if (tinsn->operands[1].mode == M_REGISTER
&& tinsn->operands[tinsn->num_operands-1].mode == M_REGISTER
&& tinsn->operands[1].expr.X_add_number == tinsn->operands[tinsn->num_operands-1].expr.X_add_number )
- as_warn (_("Equal parallell destination registers, one result will be discarded"));
+ as_warn (_("Equal parallel destination registers, one result will be discarded"));
}
}
#26 48 0x00000030 struct no name { ifd = -1, index = 1048575 }
*/
\f
-/* Redefinition of of storage classes as an enumeration for better
+/* Redefinition of storage classes as an enumeration for better
debugging. */
typedef enum sc {
[^:]*: Assembler messages:
[^:]*:5: Warning: destination register same as write-back base
-[^:]*:9: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]'
-[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7'
+[^:]*:9: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,\[r15,#5\]'
+[^:]*:12: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,.-0xab7'
[^:]*:15: Warning: destination register same as write-back base
[^:]*:16: Error: cannot use register index with PC-relative addressing -- `ldr r2,\[r15,r2\]!'
[^:]*:19: Error: cannot use register index with PC-relative addressing -- `ldr r1,\[r1,r15\]'
[^:]*: Assembler messages:
[^:]*:8: Error: registers may not be the same -- `ldr r1,\[r1,#5\]!'
-[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]'
+[^:]*:12: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,\[r15,#5\]'
[^:]*:16: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,#4\]'
[^:]*:25: Error: branch must be last instruction in IT block -- `ldrge r15,.0x4'
-[^:]*:30: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7'
+[^:]*:30: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,.-0xab7'
[^:]*:36: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,r1\]'
[^:]*:41: Error: r13 not allowed here -- `ldr r1,\[r2,r13\]'
[^:]*:42: Error: r15 not allowed here -- `ldr r2,\[r2,r15\]'
[^:]*:13: Warning: CPU8: Stack pointer accessed with an odd offset
[^:]*:14: Warning: CPU8: Stack pointer accessed with an odd offset
[^:]*:15: Warning: CPU8: Stack pointer accessed with an odd offset
-[^:]*:18: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:19: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:20: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:21: Warning: CPU12: CMP/BIT with PC destinstion ignores next instruction
-[^:]*:21: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:22: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:23: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:24: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:25: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:26: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:30: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:31: Warning: CPU12: CMP/BIT with PC destinstion ignores next instruction
-[^:]*:31: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:34: Warning: CPU12: CMP/BIT with PC destinstion ignores next instruction
-[^:]*:34: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:35: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:36: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:37: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:38: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:39: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:40: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:41: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:42: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:43: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:44: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:45: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:46: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:47: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:48: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:49: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:50: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:51: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:52: Warning: CPU13: SR is destinstion of SR altering instruction
+[^:]*:18: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:19: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:20: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:21: Warning: CPU12: CMP/BIT with PC destination ignores next instruction
+[^:]*:21: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:22: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:23: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:24: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:25: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:26: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:30: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:31: Warning: CPU12: CMP/BIT with PC destination ignores next instruction
+[^:]*:31: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:34: Warning: CPU12: CMP/BIT with PC destination ignores next instruction
+[^:]*:34: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:35: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:36: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:37: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:38: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:39: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:40: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:41: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:42: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:43: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:44: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:45: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:46: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:47: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:48: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:49: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:50: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:51: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:52: Warning: CPU13: SR is destination of SR altering instruction
[^:]*:56: Warning: CPU19: Instruction setting CPUOFF must be followed by a NOP
[^:]*:57: Warning: CPU19: Instruction setting CPUOFF must be followed by a NOP
-[^:]*:57: Warning: CPU13: SR is destinstion of SR altering instruction
+[^:]*:57: Warning: CPU13: SR is destination of SR altering instruction
ld #7,arp \r
ld *ar2+,asm \r
ldm ar3,a \r
- ld *ar2+,a || mac *ar3+,b ; single-line parallell\r
+ ld *ar2+,a || mac *ar3+,b ; single-line parallel\r
ld *ar4+,b || macr *ar5+,a ; with optional DST_ specified\r
ld *ar2+,a ; double-line parallel\r
|| mas *ar3+ \r
+2017-07-18 Nick Clifton <nickc@redhat.com>
+
+ PR 21775
+ * aarch64.cc: Fix spelling typos.
+ * arm.cc: Likewise.
+ * layout.cc: Likewise.
+ * powerpc.cc: Likewise.
+ * x86_64.cc: Likewise.
+
2017-07-12 Alan Modra <amodra@gmail.com>
* po/es.po: Update from translationproject.org/latest/gold/.
uint32_t v = 0;
uint32_t opc_v = 0;
- /* Bail out quickly if INSN doesn't fall into the the load-store
+ /* Bail out quickly if INSN doesn't fall into the load-store
encoding space. */
if (!aarch64_ldst (insn))
return false;
private:
// Section offset of "adrp". (We do not need a "adrp_shndx_" field, because we
- // can can obtain it from its parent.)
+ // can obtain it from its parent.)
const unsigned int adrp_sh_offset_;
};
// Target::do_select_as_default_target() hook so that we do not spend time
// building the table if we are not linking ARM objects.
//
-// An alternative is to to process the information in arm-reloc.def in
+// An alternative is to process the information in arm-reloc.def in
// compilation time and generate a representation of it in PODs only. That
// way we can avoid initialization when the linker starts.
if (in_attr[elfcpp::Tag_MPextension_use].int_value()
!= in_attr[i].int_value())
{
- gold_error(_("%s has has both the current and legacy "
+ gold_error(_("%s has both the current and legacy "
"Tag_MPextension_use attributes"),
name);
}
Arm_address target = (pc_for_insn + offset) | (is_blx ? 0 : 1);
- // Add a new stub if destination address in in the same page.
+ // Add a new stub if destination address is in the same page.
if (((address + i) & ~0xfffU) == (target & ~0xfffU))
{
Cortex_a8_stub* stub =
const Task* task)
{
// We need to look at all the input sections in output in ascending
- // order of of output address. We do that by building a sorted list
+ // order of output address. We do that by building a sorted list
// of output sections by addresses. Then we looks at the output sections
// in order. The input sections in an output section are already sorted
// by addresses within the output section.
}
// Set the file offsets of all the segments, and all the sections they
-// contain. They have all been created. LOAD_SEG must be be laid out
+// contain. They have all been created. LOAD_SEG must be laid out
// first. Return the offset of the data to follow.
off_t
this->set_processor_specific_flags(flags);
}
- // Offset to to save stack slot
+ // Offset to save stack slot
int
stk_toc () const
{ return this->abiversion() < 2 ? 40 : 24; }
case elfcpp::R_X86_64_GOT64:
case elfcpp::R_X86_64_GOTPLT64:
- // R_X86_64_GOTPLT64 is obsolete and treated the the same as
+ // R_X86_64_GOTPLT64 is obsolete and treated the same as
// GOT64.
gold_assert(have_got_offset);
Reloc_funcs::rela64(view, got_offset, addend);
+2017-07-18 Nick Clifton <nickc@redhat.com>
+
+ PR 21775
+ * aout/adobe.h: Fix spelling typos.
+ * aout/aout64.h: Likewise.
+ * aout/hp300hpux.h: Likewise.
+ * elf/hppa.h: Likewise.
+ * gdb/remote-sim.h: Likewise.
+ * libiberty.h: Likewise.
+ * mach-o/arm.h: Likewise.
+ * opcode/v850.h: Likewise.
+
2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
* dis-asm.h (struct disassemble_info): Change type of buffer_length
/* Struct external_exec is the same. */
-/* This is the layout on disk of the 32-bit or 64-bit exec header. */
+/* This is the layout on disk of the 32-bit or 64-bit exec header. */
struct external_exec
{
- bfd_byte e_info[4]; /* magic number and stuff */
- bfd_byte e_text[BYTES_IN_WORD]; /* length of text section in bytes */
- bfd_byte e_data[BYTES_IN_WORD]; /* length of data section in bytes */
- bfd_byte e_bss[BYTES_IN_WORD]; /* length of bss area in bytes */
- bfd_byte e_syms[BYTES_IN_WORD]; /* length of symbol table in bytes */
- bfd_byte e_entry[BYTES_IN_WORD]; /* start address */
- bfd_byte e_trsize[BYTES_IN_WORD]; /* length of text relocation info */
- bfd_byte e_drsize[BYTES_IN_WORD]; /* length of data relocation info */
+ bfd_byte e_info[4]; /* Magic number and stuff. */
+ bfd_byte e_text[BYTES_IN_WORD]; /* Length of text section in bytes. */
+ bfd_byte e_data[BYTES_IN_WORD]; /* Length of data section in bytes. */
+ bfd_byte e_bss[BYTES_IN_WORD]; /* Length of bss area in bytes. */
+ bfd_byte e_syms[BYTES_IN_WORD]; /* Length of symbol table in bytes. */
+ bfd_byte e_entry[BYTES_IN_WORD]; /* Start address. */
+ bfd_byte e_trsize[BYTES_IN_WORD]; /* Length of text relocation info. */
+ bfd_byte e_drsize[BYTES_IN_WORD]; /* Length of data relocation info. */
};
#define EXEC_BYTES_SIZE (4 + BYTES_IN_WORD * 7)
-/* Magic numbers for a.out files */
+/* Magic numbers for a.out files. */
#undef ZMAGIC
#define ZMAGIC 0xAD0BE /* Cute, eh? */
The actual text of the segments starts at N_TXTOFF in the file,
regardless of how many or how few segment headers there are. */
-struct external_segdesc {
- unsigned char e_type[1];
- unsigned char e_size[3];
- unsigned char e_virtbase[4];
- unsigned char e_filebase[4];
+struct external_segdesc
+{
+ unsigned char e_type[1];
+ unsigned char e_size[3];
+ unsigned char e_virtbase[4];
+ unsigned char e_filebase[4];
};
-struct internal_segdesc {
- unsigned int a_type:8; /* Segment type N_TEXT, N_DATA, 0 */
- unsigned int a_size:24; /* Segment size */
- bfd_vma a_virtbase; /* Virtual address */
- unsigned int a_filebase; /* Base address in object file */
+struct internal_segdesc
+{
+ unsigned int a_type:8; /* Segment type N_TEXT, N_DATA, 0. */
+ unsigned int a_size:24; /* Segment size. */
+ bfd_vma a_virtbase; /* Virtual address. */
+ unsigned int a_filebase; /* Base address in object file. */
};
#define N_TXTADDR(x) is_this_really_unused?
#define N_SYMOFF(x) ( N_DRELOFF(x) + (x)->a_drsize )
#define N_STROFF(x) ( N_SYMOFF(x) + (x)->a_syms )
\f
-/* Symbols */
-struct external_nlist {
- bfd_byte e_strx[BYTES_IN_WORD]; /* index into string table of name */
- bfd_byte e_type[1]; /* type of symbol */
- bfd_byte e_other[1]; /* misc info (usually empty) */
- bfd_byte e_desc[2]; /* description field */
- bfd_byte e_value[BYTES_IN_WORD]; /* value of symbol */
+/* Symbols. */
+struct external_nlist
+{
+ bfd_byte e_strx[BYTES_IN_WORD]; /* Index into string table of name. */
+ bfd_byte e_type[1]; /* Type of symbol. */
+ bfd_byte e_other[1]; /* Misc info (usually empty). */
+ bfd_byte e_desc[2]; /* Description field. */
+ bfd_byte e_value[BYTES_IN_WORD]; /* Value of symbol. */
};
#define EXTERNAL_NLIST_SIZE (BYTES_IN_WORD+4+BYTES_IN_WORD)
-struct internal_nlist {
- unsigned long n_strx; /* index into string table of name */
- unsigned char n_type; /* type of symbol */
- unsigned char n_other; /* misc info (usually empty) */
- unsigned short n_desc; /* description field */
- bfd_vma n_value; /* value of symbol */
+struct internal_nlist
+{
+ unsigned long n_strx; /* Index into string table of name. */
+ unsigned char n_type; /* Type of symbol. */
+ unsigned char n_other; /* Misc info (usually empty). */
+ unsigned short n_desc; /* Description field. */
+ bfd_vma n_value; /* Value of symbol. */
};
/* The n_type field is the symbol type, containing: */
-#define N_UNDF 0 /* Undefined symbol */
-#define N_ABS 2 /* Absolute symbol -- defined at particular addr */
-#define N_TEXT 4 /* Text sym -- defined at offset in text seg */
-#define N_DATA 6 /* Data sym -- defined at offset in data seg */
-#define N_BSS 8 /* BSS sym -- defined at offset in zero'd seg */
-#define N_COMM 0x12 /* Common symbol (visible after shared lib dynlink) */
-#define N_FN 0x1f /* File name of .o file */
-#define N_FN_SEQ 0x0C /* N_FN from Sequent compilers (sigh) */
+#define N_UNDF 0 /* Undefined symbol. */
+#define N_ABS 2 /* Absolute symbol -- defined at particular addr. */
+#define N_TEXT 4 /* Text sym -- defined at offset in text seg. */
+#define N_DATA 6 /* Data sym -- defined at offset in data seg. */
+#define N_BSS 8 /* BSS sym -- defined at offset in zero'd seg. */
+#define N_COMM 0x12 /* Common symbol (visible after shared lib dynlink). */
+#define N_FN 0x1f /* File name of .o file. */
+#define N_FN_SEQ 0x0C /* N_FN from Sequent compilers (sigh). */
/* Note: N_EXT can only be usefully OR-ed with N_UNDF, N_ABS, N_TEXT,
N_DATA, or N_BSS. When the low-order bit of other types is set,
(e.g. N_WARNING versus N_FN), they are two different types. */
-#define N_EXT 1 /* External symbol (as opposed to local-to-this-file) */
+#define N_EXT 1 /* External symbol (as opposed to local-to-this-file). */
#define N_TYPE 0x1e
-#define N_STAB 0xe0 /* If any of these bits are on, it's a debug symbol */
+#define N_STAB 0xe0 /* If any of these bits are on, it's a debug symbol. */
#define N_INDR 0x0a
in that it can satisfy undefined external references. */
/* These appear as input to LD, in a .o file. */
-#define N_SETA 0x14 /* Absolute set element symbol */
-#define N_SETT 0x16 /* Text set element symbol */
-#define N_SETD 0x18 /* Data set element symbol */
-#define N_SETB 0x1A /* Bss set element symbol */
+#define N_SETA 0x14 /* Absolute set element symbol. */
+#define N_SETT 0x16 /* Text set element symbol. */
+#define N_SETD 0x18 /* Data set element symbol. */
+#define N_SETB 0x1A /* Bss set element symbol. */
/* This is output from LD. */
#define N_SETV 0x1C /* Pointer to set vector in data area. */
instructions. Eg, on the 68k, each move instruction can reference
the target with a displacement of 16 or 32 bits. On the sparc, move
instructions use an offset of 14 bits, so the offset is stored in
- the reloc field, and the data in the section is ignored.
-*/
+ the reloc field, and the data in the section is ignored. */
/* This structure describes a single relocation to be performed.
The text-relocation section of the file is a vector of these structures,
all of which apply to the text section.
Likewise, the data-relocation section applies to the data section. */
-struct reloc_std_external {
- bfd_byte r_address[BYTES_IN_WORD]; /* offset of of data to relocate */
- bfd_byte r_index[3]; /* symbol table index of symbol */
- bfd_byte r_type[1]; /* relocation type */
+struct reloc_std_external
+{
+ bfd_byte r_address[BYTES_IN_WORD]; /* Offset of data to relocate. */
+ bfd_byte r_index[3]; /* Symbol table index of symbol. */
+ bfd_byte r_type[1]; /* Relocation type. */
};
#define RELOC_STD_BITS_PCREL_BIG 0x80
#define RELOC_STD_BITS_PCREL_LITTLE 0x01
#define RELOC_STD_BITS_LENGTH_BIG 0x60
-#define RELOC_STD_BITS_LENGTH_SH_BIG 5 /* To shift to units place */
+#define RELOC_STD_BITS_LENGTH_SH_BIG 5 /* To shift to units place. */
#define RELOC_STD_BITS_LENGTH_LITTLE 0x06
#define RELOC_STD_BITS_LENGTH_SH_LITTLE 1
#define RELOC_STD_BITS_RELATIVE_BIG 0x02
#define RELOC_STD_BITS_RELATIVE_LITTLE 0x02
-#define RELOC_STD_SIZE (BYTES_IN_WORD + 3 + 1) /* Bytes per relocation entry */
+#define RELOC_STD_SIZE (BYTES_IN_WORD + 3 + 1) /* Bytes per relocation entry. */
struct reloc_std_internal
{
unsigned int r_extern:1;
/* The next three bits are for SunOS shared libraries, and seem to
be undocumented. */
- unsigned int r_baserel:1; /* Linkage table relative */
- unsigned int r_jmptable:1; /* pc-relative to jump table */
- unsigned int r_relative:1; /* "relative relocation" */
+ unsigned int r_baserel:1; /* Linkage table relative. */
+ unsigned int r_jmptable:1; /* pc-relative to jump table. */
+ unsigned int r_relative:1; /* "relative relocation". */
/* unused */
- unsigned int r_pad:1; /* Padding -- set to zero */
+ unsigned int r_pad:1; /* Padding -- set to zero. */
};
/* EXTENDED RELOCS */
-struct reloc_ext_external {
- bfd_byte r_address[BYTES_IN_WORD]; /* offset of of data to relocate */
- bfd_byte r_index[3]; /* symbol table index of symbol */
- bfd_byte r_type[1]; /* relocation type */
- bfd_byte r_addend[BYTES_IN_WORD]; /* datum addend */
+struct reloc_ext_external
+{
+ bfd_byte r_address[BYTES_IN_WORD]; /* Offset of data to relocate. */
+ bfd_byte r_index[3]; /* Symbol table index of symbol. */
+ bfd_byte r_type[1]; /* Relocation type. */
+ bfd_byte r_addend[BYTES_IN_WORD]; /* Datum addend. */
};
#define RELOC_EXT_BITS_EXTERN_BIG 0x80
enum reloc_type
{
- /* simple relocations */
+ /* Simple relocations. */
RELOC_8, /* data[0:7] = addend + sv */
RELOC_16, /* data[0:15] = addend + sv */
RELOC_32, /* data[0:31] = addend + sv */
- /* pc-rel displacement */
+ /* PC-rel displacement. */
RELOC_DISP8, /* data[0:7] = addend - pc + sv */
RELOC_DISP16, /* data[0:15] = addend - pc + sv */
RELOC_DISP32, /* data[0:31] = addend - pc + sv */
- /* Special */
+ /* Special. */
RELOC_WDISP30, /* data[0:29] = (addend + sv - pc)>>2 */
RELOC_WDISP22, /* data[0:21] = (addend + sv - pc)>>2 */
RELOC_HI22, /* data[0:21] = (addend + sv)>>10 */
RELOC_LO10, /* data[0:9] = (addend + sv) */
RELOC_SFA_BASE,
RELOC_SFA_OFF13,
- /* P.I.C. (base-relative) */
- RELOC_BASE10, /* Not sure - maybe we can do this the */
- RELOC_BASE13, /* right way now */
+ /* P.I.C. (base-relative). */
+ RELOC_BASE10, /* Not sure - maybe we can do this the */
+ RELOC_BASE13, /* right way now. */
RELOC_BASE22,
- /* for some sort of pc-rel P.I.C. (?) */
+ /* For some sort of pc-rel P.I.C. (?) */
RELOC_PC10,
RELOC_PC22,
- /* P.I.C. jump table */
+ /* P.I.C. jump table. */
RELOC_JMP_TBL,
- /* reputedly for shared libraries somehow */
+ /* Reputedly for shared libraries somehow. */
RELOC_SEGOFF16,
RELOC_GLOB_DAT,
RELOC_JMP_SLOT,
RELOC_CONSTH,
NO_RELOC
- };
-
+};
-struct reloc_internal {
- bfd_vma r_address; /* offset of of data to relocate */
- long r_index; /* symbol table index of symbol */
- enum reloc_type r_type; /* relocation type */
- bfd_vma r_addend; /* datum addend */
+struct reloc_internal
+{
+ bfd_vma r_address; /* Offset of data to relocate. */
+ long r_index; /* Symbol table index of symbol. */
+ enum reloc_type r_type; /* Relocation type. */
+ bfd_vma r_addend; /* Datum addend. */
};
-#endif /* __A_OUT_ADOBE_H__ */
+#endif /* __A_OUT_ADOBE_H__ */
struct reloc_std_external
{
- bfd_byte r_address[BYTES_IN_WORD]; /* Offset of of data to relocate. */
+ bfd_byte r_address[BYTES_IN_WORD]; /* Offset of data to relocate. */
bfd_byte r_index[3]; /* Symbol table index of symbol. */
bfd_byte r_type[1]; /* Relocation type. */
};
struct reloc_ext_external
{
- bfd_byte r_address[BYTES_IN_WORD]; /* Offset of of data to relocate. */
+ bfd_byte r_address[BYTES_IN_WORD]; /* Offset of data to relocate. */
bfd_byte r_index[3]; /* Symbol table index of symbol. */
bfd_byte r_type[1]; /* Relocation type. */
bfd_byte r_addend[BYTES_IN_WORD]; /* Datum addend. */
struct reloc_internal
{
- bfd_vma r_address; /* Offset of of data to relocate. */
+ bfd_vma r_address; /* Offset of data to relocate. */
long r_index; /* Symbol table index of symbol. */
enum reloc_type r_type; /* Relocation type. */
bfd_vma r_addend; /* Datum addend. */
#define EXEC_BYTES_SIZE 64
struct hp300hpux_nlist_bytes
- {
- unsigned char e_value[4];
- unsigned char e_type[1];
- unsigned char e_length[1]; /* length of ascii symbol name */
- unsigned char e_almod[2]; /* alignment mod */
- unsigned char e_shlib[2]; /* info about dynamic linking */
- };
+{
+ unsigned char e_value[4];
+ unsigned char e_type[1];
+ unsigned char e_length[1]; /* Length of ascii symbol name. */
+ unsigned char e_almod[2]; /* Alignment mod. */
+ unsigned char e_shlib[2]; /* Info about dynamic linking. */
+};
#define EXTERNAL_NLIST_SIZE 10
struct hp300hpux_reloc
- {
- unsigned char r_address[4];/* offset of of data to relocate */
- unsigned char r_index[2]; /* symbol table index of symbol */
- unsigned char r_type[1]; /* relocation type */
- unsigned char r_length[1]; /* length of item to reloc */
- };
+{
+ unsigned char r_address[4];/* offset of data to relocate */
+ unsigned char r_index[2]; /* symbol table index of symbol */
+ unsigned char r_type[1]; /* relocation type */
+ unsigned char r_length[1]; /* length of item to reloc */
+};
struct hp300hpux_header_extension
{
- unsigned char e_syms[4];
- unsigned char unique_headers[12*4];
- unsigned char e_header[2]; /* type of header */
- unsigned char e_version[2]; /* version */
- unsigned char e_size[4]; /* bytes following*/
- unsigned char e_extension[4];/* file offset of next extension */
+ unsigned char e_syms[4];
+ unsigned char unique_headers[12*4];
+ unsigned char e_header[2]; /* Type of header. */
+ unsigned char e_version[2]; /* Version. */
+ unsigned char e_size[4]; /* Bytes following. */
+ unsigned char e_extension[4];/* File offset of next extension. */
};
#define EXTERNAL_EXTENSION_HEADER_SIZE (16*4)
-/* hpux separates object files (0x106) and impure executables (0x107) */
-/* but the bfd code does not distinguish between them. Since we want to*/
-/* read hpux .o files, we add an special define and use it below in */
-/* offset and address calculations. */
+/* HPUX separates object files (0x106) and impure executables (0x107)
+ but the bfd code does not distinguish between them. Since we want to
+ read hpux .o files, we add an special define and use it below in
+ offset and address calculations. */
#define HPUX_DOT_O_MAGIC 0x106
-#define OMAGIC 0x107 /* object file or impure executable. */
+#define OMAGIC 0x107 /* Object file or impure executable. */
#define NMAGIC 0x108 /* Code indicating pure executable. */
-#define ZMAGIC 0x10B /* demand-paged executable. */
+#define ZMAGIC 0x10B /* Demand-paged executable. */
#define N_HEADER_IN_TEXT(x) 0
-#if 0 /* libaout.h only uses the lower 8 bits */
+#if 0 /* libaout.h only uses the lower 8 bits. */
#define HP98x6_ID 0x20A
#define HP9000S200_ID 0x20C
#endif
#define N_EXTHOFF(x) ( N_DRELOFF(x) /* + (x)->a_drsize */)
#define N_STROFF(x) ( 0 /* no string table */ )
-/* use these when the file has gnu symbol tables */
+/* Use these when the file has gnu symbol tables. */
#define N_GNU_TRELOFF(x) (N_DATOFF(x) + (x)->a_data)
#define N_GNU_DRELOFF(x) (N_GNU_TRELOFF(x) + (x)->a_trsize)
#define N_GNU_SYMOFF(x) (N_GNU_DRELOFF(x) + (x)->a_drsize)
When supporting argument relocations, function calls must be
accompanied by parameter relocation information. This information is
carried in the ten high-order bits of the addend field. The remaining
- 22 bits of of the addend field are sign-extended to form the Addend.
+ 22 bits of the addend field are sign-extended to form the Addend.
Note the code to build argument relocations depends on the
addend being zero. A consequence of this limitation is GAS
that information is not directly accessable via this interface.
SIM_SIGNALLED: The program has been terminated by a signal. The
- simulator has encountered target code that causes the the program
+ simulator has encountered target code that causes the program
to exit with signal SIGRC.
SIM_RUNNING, SIM_POLLING: The return of one of these values
Copyright (C) 1997-2017 Free Software Foundation, Inc.
Note - certain prototypes declared in this header file are for
- functions whoes implementation copyright does not belong to the
+ functions whose implementation copyright does not belong to the
FSF. Those prototypes are present in this file for reference
purposes only and their presence in this file should not construed
as an indication of ownership by the FSF of the implementation of
/* ARM relocations. */
#define BFD_MACH_O_ARM_RELOC_VANILLA 0 /* Generic relocation. */
#define BFD_MACH_O_ARM_RELOC_PAIR 1 /* Second entry in a pair. */
-#define BFD_MACH_O_ARM_RELOC_SECTDIFF 2 /* Substract with a PAIR. */
+#define BFD_MACH_O_ARM_RELOC_SECTDIFF 2 /* Subtract with a PAIR. */
#define BFD_MACH_O_ARM_RELOC_LOCAL_SECTDIFF 3 /* Like above, but local ref. */
#define BFD_MACH_O_ARM_RELOC_PB_LA_PTR 4 /* Prebound lazy pointer. */
#define BFD_MACH_O_ARM_RELOC_BR24 5 /* 24bit branch. */
/* The operand has '%' prefix. */
#define V850_OPERAND_PERCENT 0x200000
-/* This operand is a cache oparation. */
+/* This operand is a cache operation. */
#define V850_OPERAND_CACHEOP 0x400000
-/* This operand is a prefetch oparation. */
+/* This operand is a prefetch operation. */
#define V850_OPERAND_PREFOP 0x800000
/* A PC-relative displacement where a positive value indicates a backwards displacement. */
+2017-07-18 Nick Clifton <nickc@redhat.com>
+
+ PR 21775
+ * ld.texinfo: Fix spelling typos.
+ * testsuite/ld-elfcomm/elfcomm.exp: Likewise.
+
2017-07-17 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/ld-i386/i386.exp: Run pie1 and pie1-nacl.
@code{PRIVATE}: Put the symbol in the DLL's export table, but do not put
it into the static import library used to resolve imports at link time. The
symbol can still be imported using the @code{LoadLibrary/GetProcAddress}
-API at runtime or by by using the GNU ld extension of linking directly to
+API at runtime or by using the GNU ld extension of linking directly to
the DLL without an import library.
See ld/deffilep.y in the binutils sources for the full specification of
test_sort_common
-set test1 "size/aligment change of common symbols"
+set test1 "size/alignment change of common symbols"
set test1w1 "$test1 (warning 1)"
set test1w2 "$test1 (warning 2)"
set test1c1 "$test1 (change 1)"
+2017-07-18 Nick Clifton <nickc@redhat.com>
+
+ PR 21775
+ * aarch64-opc.c: Fix spelling typos.
+ * i386-dis.c: Likewise.
+
2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
* dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
case AARCH64_OPND_PAIRREG:
case AARCH64_OPND_SVE_Rm:
/* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
- the <ic_op>, therefore we we use opnd->present to override the
+ the <ic_op>, therefore we use opnd->present to override the
generic optional-ness information. */
if (opnd->type == AARCH64_OPND_Rt_SYS)
{
/* X86_64_82 */
{
- /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */
+ /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
{ REG_TABLE (REG_80) },
},
projects / binutils-gdb.git / commitdiff