RX assembler: switch arguments of thw MVTACGU insn.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 0be692c6401c066782c6914023af37bd96d5be27..a299d024d95b756290698480743fbe7583e8e5de 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2022-10-31  Nick Clifton  <nickc@redhat.com>
+
+       * testsuite/gas/rx/mvtacgu.d: Update expected disassembly.
+
 2022-10-11  Nick Clifton  <nickc@redhat.com>
 
        * symbols.c (S_GET_VALUE): If the unresolved symbol is the fake

diff --git a/gas/testsuite/gas/rx/mvtacgu.d b/gas/testsuite/gas/rx/mvtacgu.d
index 334cafa902e768ca01b366542308b1d54a37a737..67e8e857509e574ca8a5102d3aebda096a54f80f 100644 (file)
--- a/gas/testsuite/gas/rx/mvtacgu.d
+++ b/gas/testsuite/gas/rx/mvtacgu.d
@@ -7,7 +7,7 @@
 Disassembly of section \.text:
 
 00000000 <\.text>:
-   0:  fd 17 30                        mvtacgu a0, r0
-   3:  fd 17 3f                        mvtacgu a0, r15
-   6:  fd 17 b0                        mvtacgu a1, r0
-   9:  fd 17 bf                        mvtacgu a1, r15
+   0:  fd 17 30                        mvtacgu r0, a0
+   3:  fd 17 3f                        mvtacgu r15, a0
+   6:  fd 17 b0                        mvtacgu r0, a1
+   9:  fd 17 bf                        mvtacgu r15, a1

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bbd3544b83d07ad40acd5bd2589150602cf8af6f..5bddae5c626a4dba5ca07ff3e9334ee39bcdd913 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2022-10-31  Yoshinori Sato  <ysato@users.sourceforge.jp>
+
+       * rx-decode.opc: Switch arguments of the MVTACGU insn.
+       * rx-decode.c: Regenerate.
+
 2022-09-22  Yoshinori Sato  <ysato@users.sourceforge.jp>
 
        * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC

diff --git a/opcodes/rx-decode.c b/opcodes/rx-decode.c
index 17fbcfcfe6c503a6ca846d6603b9b08a431a2929..8ccb12674a70c42627e4f38f0baf4e90e0d440bd 100644 (file)
--- a/opcodes/rx-decode.c
+++ b/opcodes/rx-decode.c
@@ -12476,22 +12476,22 @@ rx_decode_opcode (unsigned long pc AU,
                   break;
                 case 0x30:
                     {
-                      /** 1111 1101 0001 0111 a011 rdst        mvtacgu %0, %1 */
+                      /** 1111 1101 0001 0111 a011 rsrc        mvtacgu %1, %0 */
 #line 1110 "rx-decode.opc"
                       int a AU = (op[2] >> 7) & 0x01;
 #line 1110 "rx-decode.opc"
-                      int rdst AU = op[2] & 0x0f;
+                      int rsrc AU = op[2] & 0x0f;
                       if (trace)
                         {
                           printf ("\033[33m%s\033[0m  %02x %02x %02x\n",
-                                 "/** 1111 1101 0001 0111 a011 rdst    mvtacgu %0, %1 */",
+                                 "/** 1111 1101 0001 0111 a011 rsrc    mvtacgu %1, %0 */",
                                  op[0], op[1], op[2]);
                           printf ("  a = 0x%x,", a);
-                          printf ("  rdst = 0x%x\n", rdst);
+                          printf ("  rsrc = 0x%x\n", rsrc);
                         }
-                      SYNTAX("mvtacgu  %0, %1");
+                      SYNTAX("mvtacgu  %1, %0");
 #line 1110 "rx-decode.opc"
-                      ID(mvtacgu); DR(a+32); SR(rdst); F_____;
+                      ID(mvtacgu); SR(rsrc); DR(a+32); F_____;
 
                     }
                   break;

diff --git a/opcodes/rx-decode.opc b/opcodes/rx-decode.opc
index 86effc398624c24f211703f568f60e365b218fc5..1b303ed8b19a233b8b8b1058eea447d06dd50242 100644 (file)
--- a/opcodes/rx-decode.opc
+++ b/opcodes/rx-decode.opc
@@ -1106,8 +1106,8 @@ rx_decode_opcode (unsigned long pc AU,
 /** 1111 1101 0001 111i a m11 rdst     mvfacgu #%2, %1, %0 */
   ID(mvfacgu); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
 
-/** 1111 1101 0001 0111 a011 rdst      mvtacgu %0, %1 */
-  ID(mvtacgu); DR(a+32); SR(rdst); F_____;
+/** 1111 1101 0001 0111 a011 rsrc      mvtacgu %1, %0 */
+  ID(mvtacgu); SR(rsrc); DR(a+32); F_____;
 
 /** 1111 1101 0001 1001 a00i 0000      racl    #%1, %0 */
   ID(racl); SC(i+1); DR(a+32); F_____;