profile = Param.Latency('0ns', "trace the kernel stack")
do_quiesce = Param.Bool(True, "enable quiesce instructions")
- if not buildEnv['FULL_SYSTEM']:
- workload = VectorParam.Process("processes to run")
+ workload = VectorParam.Process([], "processes to run")
if buildEnv['TARGET_ISA'] == 'sparc':
dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
Source('thread_context.cc')
Source('thread_state.cc')
-if env['FULL_SYSTEM']:
- if env['TARGET_ISA'] == 'sparc':
- SimObject('LegionTrace.py')
- Source('legiontrace.cc')
+if env['TARGET_ISA'] == 'sparc':
+ SimObject('LegionTrace.py')
+ Source('legiontrace.cc')
if env['USE_CHECKER']:
Source('checker/cpu.cc')
interrupts->setCPU(this);
if (FullSystem) {
-#if FULL_SYSTEM
profileEvent = NULL;
if (params()->profile)
profileEvent = new ProfileEvent(this, params()->profile);
-#endif
}
tracer = params()->tracer;
}
bool
checkInterrupts(ThreadContext *tc) const
{
- return interrupts->checkInterrupts(tc);
+ return FullSystem && interrupts->checkInterrupts(tc);
}
class ProfileEvent : public Event
#include <list>
#include <string>
+#include "arch/kernel_stats.hh"
+#include "arch/vtophys.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "arch/vtophys.hh"
-#endif // FULL_SYSTEM
-
using namespace std;
//The CheckerCPU does alpha only
using namespace AlphaISA;
exitOnError = p->exitOnError;
warnOnlyOnLoadError = p->warnOnlyOnLoadError;
-#if FULL_SYSTEM
itb = p->itb;
dtb = p->dtb;
systemPtr = NULL;
-#else
process = p->process;
thread = new SimpleThread(this, /* thread_num */ 0, process);
tc = thread->getTC();
threadContexts.push_back(tc);
-#endif
result.integer = 0;
}
void
CheckerCPU::setSystem(System *system)
{
-#if FULL_SYSTEM
systemPtr = system;
thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
threadContexts.push_back(tc);
delete thread->kernelStats;
thread->kernelStats = NULL;
-#endif
}
void
}
-#if FULL_SYSTEM
Addr
CheckerCPU::dbg_vtophys(Addr addr)
{
return vtophys(tc, addr);
}
-#endif // FULL_SYSTEM
bool
CheckerCPU::checkFlags(Request *req)
#include "sim/eventq.hh"
// forward declarations
-#if FULL_SYSTEM
namespace TheISA
{
class TLB;
}
-class Processor;
-class PhysicalMemory;
-
-#else
-class Process;
-
-#endif // FULL_SYSTEM
template <class>
class BaseDynInst;
class CheckerCPUParams;
-class ThreadContext;
-class MemInterface;
class Checkpoint;
+class MemInterface;
+class PhysicalMemory;
+class Process;
+class Processor;
+class ThreadContext;
class Request;
/**
TheISA::TLB *itb;
TheISA::TLB *dtb;
-#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
-#endif
union Result {
uint64_t integer;
this->dtb->demapPage(vaddr, asn);
}
-#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
-#else
// Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall.
void syscall(uint64_t callnum) { }
-#endif
void handleError()
{
#include <list>
#include <string>
+#include "arch/vtophys.hh"
#include "base/refcnt.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
-#if FULL_SYSTEM
-#include "arch/vtophys.hh"
-#endif // FULL_SYSTEM
-
using namespace std;
//The CheckerCPU does alpha only
using namespace AlphaISA;
// Try to fetch the instruction
-#if FULL_SYSTEM
-#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
-#else
-#define IFETCH_FLAGS(pc) 0
-#endif
+#define IFETCH_FLAGS(pc) (FullSystem ? 0 : ((pc) & 1) ? PHYSICAL : 0)
uint64_t fetch_PC = thread->readPC() & ~3;
}
if (fault != NoFault) {
-#if FULL_SYSTEM
fault->invoke(tc, curStaticInst);
willChangePC = true;
newPC = thread->readPC();
DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
-#endif
} else {
#if THE_ISA != MIPS_ISA
// go to the next instruction
}
-#if FULL_SYSTEM
- // @todo: Determine if these should happen only if the
- // instruction hasn't faulted. In the SimpleCPU case this may
- // not be true, but in the O3 or Ozone case this may be true.
- Addr oldpc;
- int count = 0;
- do {
- oldpc = thread->readPC();
- system->pcEventQueue.service(tc);
- count++;
- } while (oldpc != thread->readPC());
- if (count > 1) {
- willChangePC = true;
- newPC = thread->readPC();
- DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
+ if (FullSystem) {
+ // @todo: Determine if these should happen only if the
+ // instruction hasn't faulted. In the SimpleCPU case this may
+ // not be true, but in the O3 or Ozone case this may be true.
+ Addr oldpc;
+ int count = 0;
+ do {
+ oldpc = thread->readPC();
+ system->pcEventQueue.service(tc);
+ count++;
+ } while (oldpc != thread->readPC());
+ if (count > 1) {
+ willChangePC = true;
+ newPC = thread->readPC();
+ DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
+ }
}
-#endif
// @todo: Optionally can check all registers. (Or just those
// that have been modified).
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
-#if FULL_SYSTEM
System *getSystemPtr() { return actualTC->getSystemPtr(); }
PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }
-#endif
+
Process *getProcessPtr() { return actualTC->getProcessPtr(); }
TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
/// Set the status to Halted.
void halt() { actualTC->halt(); }
-#if FULL_SYSTEM
void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
-#endif
void takeOverFrom(ThreadContext *oldContext)
{
void unserialize(Checkpoint *cp, const std::string §ion)
{ actualTC->unserialize(cp, section); }
-#if FULL_SYSTEM
EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
Tick readLastActivate() { return actualTC->readLastActivate(); }
void profileClear() { return actualTC->profileClear(); }
void profileSample() { return actualTC->profileSample(); }
-#endif
int threadId() { return actualTC->threadId(); }
// @todo: Fix this!
bool misspeculating() { return actualTC->misspeculating(); }
-#if !FULL_SYSTEM
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-#endif
};
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
std::string sym_str;
Addr sym_addr;
Addr cur_pc = pc.instAddr();
- if (debugSymbolTable && Debug::ExecSymbol
-#if FULL_SYSTEM
- && !inUserMode(thread)
-#endif
+ if (debugSymbolTable && Debug::ExecSymbol && !inUserMode(thread)
&& debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) {
if (cur_pc != sym_addr)
sym_str += csprintf("+%d",cur_pc - sym_addr);
#include "arch/utility.hh"
#include "base/bigint.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/inorder/resources/resource_list.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/thread_context.hh"
#include "debug/Activity.hh"
#include "debug/InOrderCPU.hh"
+#include "debug/Interrupt.hh"
#include "debug/RefCount.hh"
#include "debug/SkedCache.hh"
#include "debug/Quiesce.hh"
#include "mem/translating_port.hh"
#include "params/InOrderCPU.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"
cpu->trapPending[tid] = false;
break;
-#if !FULL_SYSTEM
case Syscall:
cpu->syscall(inst->syscallNum, tid);
cpu->resPool->trap(fault, tid, inst);
break;
-#endif
+
default:
fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
}
timeBuffer(2 , 2),
removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity),
-#if FULL_SYSTEM
system(params->system),
-#endif // FULL_SYSTEM
#ifdef DEBUG
cpuEventNum(0),
resReqCount(0),
// Resize for Multithreading CPUs
thread.resize(numThreads);
-#if FULL_SYSTEM
- active_threads = 1;
-#else
- active_threads = params->workload.size();
+ if (FullSystem) {
+ active_threads = 1;
+ } else {
+ active_threads = params->workload.size();
- if (active_threads > MaxThreads) {
- panic("Workload Size too large. Increase the 'MaxThreads'"
- "in your InOrder implementation or "
- "edit your workload size.");
- }
+ if (active_threads > MaxThreads) {
+ panic("Workload Size too large. Increase the 'MaxThreads'"
+ "in your InOrder implementation or "
+ "edit your workload size.");
+ }
-
- if (active_threads > 1) {
- threadModel = (InOrderCPU::ThreadModel) params->threadModel;
-
- if (threadModel == SMT) {
- DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
- } else if (threadModel == SwitchOnCacheMiss) {
- DPRINTF(InOrderCPU, "Setting Thread Model to "
- "Switch On Cache Miss\n");
+
+ if (active_threads > 1) {
+ threadModel = (InOrderCPU::ThreadModel) params->threadModel;
+
+ if (threadModel == SMT) {
+ DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
+ } else if (threadModel == SwitchOnCacheMiss) {
+ DPRINTF(InOrderCPU, "Setting Thread Model to "
+ "Switch On Cache Miss\n");
+ }
+
+ } else {
+ threadModel = Single;
}
-
- } else {
- threadModel = Single;
}
-
-
-
-#endif
// Bind the fetch & data ports from the resource pool.
fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
pc[tid].set(0);
lastCommittedPC[tid].set(0);
-#if FULL_SYSTEM
- // SMT is not supported in FS mode yet.
- assert(numThreads == 1);
- thread[tid] = new Thread(this, 0, NULL);
-#else
- if (tid < (ThreadID)params->workload.size()) {
- DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
- tid, params->workload[tid]->prog_fname);
- thread[tid] =
- new Thread(this, tid, params->workload[tid]);
+ if (FullSystem) {
+ // SMT is not supported in FS mode yet.
+ assert(numThreads == 1);
+ thread[tid] = new Thread(this, 0, NULL);
} else {
- //Allocate Empty thread so M5 can use later
- //when scheduling threads to CPU
- Process* dummy_proc = params->workload[0];
- thread[tid] = new Thread(this, tid, dummy_proc);
+ if (tid < (ThreadID)params->workload.size()) {
+ DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
+ tid, params->workload[tid]->prog_fname);
+ thread[tid] =
+ new Thread(this, tid, params->workload[tid]);
+ } else {
+ //Allocate Empty thread so M5 can use later
+ //when scheduling threads to CPU
+ Process* dummy_proc = params->workload[0];
+ thread[tid] = new Thread(this, tid, dummy_proc);
+ }
+
+ // Eventually set this with parameters...
+ asid[tid] = tid;
}
-
- // Eventually set this with parameters...
- asid[tid] = tid;
-#endif
// Setup the TC that will serve as the interface to the threads/CPU.
InOrderThreadContext *tc = new InOrderThreadContext;
tc->cpu = this;
tc->thread = thread[tid];
-#if FULL_SYSTEM
// Setup quiesce event.
this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
-#endif
// Give the thread the TC.
thread[tid]->tc = tc;
dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
-#if FULL_SYSTEM
- // Use this dummy inst to force squashing behind every instruction
- // in pipeline
- dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
- dummyTrapInst[tid]->seqNum = 0;
- dummyTrapInst[tid]->squashSeqNum = 0;
- dummyTrapInst[tid]->setTid(tid);
-#endif
- trapPending[tid] = false;
+ if (FullSystem) {
+ // Use this dummy inst to force squashing behind every instruction
+ // in pipeline
+ dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
+ dummyTrapInst[tid]->seqNum = 0;
+ dummyTrapInst[tid]->squashSeqNum = 0;
+ dummyTrapInst[tid]->setTid(tid);
+ }
+
+ trapPending[tid] = false;
}
++numCycles;
-#if FULL_SYSTEM
checkForInterrupts();
-#endif
bool pipes_idle = true;
//Tick each of the stages
for (ThreadID tid = 0; tid < numThreads; ++tid)
thread[tid]->inSyscall = true;
-#if FULL_SYSTEM
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- ThreadContext *src_tc = threadContexts[tid];
- TheISA::initCPU(src_tc, src_tc->contextId());
+ if (FullSystem) {
+ for (ThreadID tid = 0; tid < numThreads; tid++) {
+ ThreadContext *src_tc = threadContexts[tid];
+ TheISA::initCPU(src_tc, src_tc->contextId());
+ }
}
-#endif
// Clear inSyscall.
for (ThreadID tid = 0; tid < numThreads; ++tid)
return total;
}
-#if FULL_SYSTEM
/** Pointer to the system. */
System *system;
-#endif
/** The global sequence number counter. */
InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
#include "params/InOrderCPU.hh"
+#include "sim/full_system.hh"
InOrderCPU *
InOrderCPUParams::create()
{
-#if FULL_SYSTEM
- // Full-system only supports a single thread for the moment.
- ThreadID actual_num_threads = 1;
-#else
- ThreadID actual_num_threads =
- (numThreads >= workload.size()) ? numThreads : workload.size();
+ ThreadID actual_num_threads;
+ if (FullSystem) {
+ // Full-system only supports a single thread for the moment.
+ actual_num_threads = 1;
+ } else {
+ actual_num_threads =
+ (numThreads >= workload.size()) ? numThreads : workload.size();
- if (workload.size() == 0) {
- fatal("Must specify at least one workload!");
+ if (workload.size() == 0) {
+ fatal("Must specify at least one workload!");
+ }
}
-#endif
numThreads = actual_num_threads;
public:
// Workloads
-#if !FULL_SYSTEM
std::vector<Process *> workload;
Process *process;
-#endif // FULL_SYSTEM
//
// Memory System/Caches
{
Port::setPeer(port);
-#if FULL_SYSTEM
// Update the ThreadContext's memory ports (Functional/Virtual
// Ports)
if (cachePortUnit->resName == "dcache_port") {
cachePortUnit->cpu->updateMemPorts();
}
-
-#endif
}
Port *
}
}
-#if !FULL_SYSTEM
void
CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
{
tlbBlocked[tid] = false;
}
-#endif
Fault
CacheUnit::read(DynInstPtr inst, Addr addr,
bool processSquash(CacheReqPacket *cache_pkt);
-#if !FULL_SYSTEM
void trap(Fault fault, ThreadID tid, DynInstPtr inst);
-#endif
+
void recvRetry();
/** Returns a specific port. */
#include "debug/Fault.hh"
#include "debug/InOrderExecute.hh"
#include "debug/InOrderStall.hh"
+#include "sim/full_system.hh"
using namespace std;
using namespace ThePipeline;
seq_num, didx, inst->readIntResult(didx));
#endif
-#if !FULL_SYSTEM
- // The Syscall might change the PC, so conservatively
- // squash everything behing it
- if (inst->isSyscall()) {
- inst->setSquashInfo(stage_num);
- setupSquash(inst, stage_num, tid);
+ if (!FullSystem) {
+ // The Syscall might change the PC, so conservatively
+ // squash everything behing it
+ if (inst->isSyscall()) {
+ inst->setSquashInfo(stage_num);
+ setupSquash(inst, stage_num, tid);
+ }
}
-#endif
} else {
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
"fault.\n", inst->readTid(), seq_num, fault->name());
#include "cpu/inorder/thread_context.hh"
#include "cpu/exetrace.hh"
#include "debug/InOrderCPU.hh"
+#include "sim/full_system.hh"
using namespace TheISA;
setStatus(old_context->status());
copyArchRegs(old_context);
-#if !FULL_SYSTEM
thread->funcExeInst = old_context->readFuncExeInst();
-#endif
old_context->setStatus(ThreadContext::Halted);
void
InOrderThreadContext::regStats(const std::string &name)
{
-#if FULL_SYSTEM
- thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
- thread->kernelStats->regStats(name + ".kern");
-#endif
- ;
+ if (FullSystem) {
+ thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+ thread->kernelStats->regStats(name + ".kern");
+ }
}
void setNextMicroPC(uint64_t val) { };
-#if FULL_SYSTEM
/** Returns a pointer to physical memory. */
PhysicalMemory *getPhysMemPtr()
{ assert(0); return 0; /*return cpu->physmem;*/ }
-#endif
/** Returns a pointer to this thread's kernel statistics. */
TheISA::Kernel::Statistics *getKernelStats()
#include "cpu/thread_state.hh"
#include "sim/sim_exit.hh"
-class Event;
-class InOrderCPU;
-
-#if FULL_SYSTEM
class EndQuiesceEvent;
-class FunctionProfile;
-class ProfileNode;
-#else
+class Event;
class FunctionalMemory;
-#endif
+class FunctionProfile;
+class InOrderCPU;
class Process;
+class ProfileNode;
/**
* Class that has various thread state, such as the status, the
void
IntrControl::post(int cpu_id, int int_num, int index)
{
-#if FULL_SYSTEM
DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
cpu->postInterrupt(int_num, index);
-#else
- panic("Called IntrControl::post in SE mode.\n");
-#endif
}
void
IntrControl::clear(int cpu_id, int int_num, int index)
{
-#if FULL_SYSTEM
DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
cpu->clearInterrupt(int_num, index);
-#else
- panic("Called IntrControl::clear in SE mode.\n");
-#endif
}
IntrControl *
#error Legion tracing only works with SPARC simulations!
#endif
-#include "config/full_system.hh"
-#if !FULL_SYSTEM
- #error Legion tracing only works in full system!
-#endif
-
#include <sys/ipc.h>
#include <sys/shm.h>
#include "arch/sparc/predecoder.hh"
#include "arch/sparc/registers.hh"
#include "arch/sparc/utility.hh"
+#include "arch/tlb.hh"
#include "base/socket.hh"
#include "cpu/base.hh"
#include "cpu/decode.hh"
#include "cpu/legiontrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
-#if FULL_SYSTEM
-#include "arch/tlb.hh"
-#endif
-
//XXX This is temporary
#include "cpu/m5legion_interface.h"
using namespace std;
using namespace TheISA;
-#if FULL_SYSTEM
static int diffcount = 0;
static bool wasMicro = false;
-#endif
namespace Trace {
SharedData *shared_data = NULL;
Trace::LegionTrace *
LegionTraceParams::create()
{
+ if (!FullSystem)
+ panic("Legion tracing only works in full system!");
return new Trace::LegionTrace(this);
};
activity = Param.Unsigned(0, "Initial count")
if buildEnv['USE_CHECKER']:
- if not buildEnv['FULL_SYSTEM']:
- checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
- exitOnError=False,
- updateOnError=True,
- warnOnlyOnLoadError=False),
- "checker")
- else:
- checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
- warnOnlyOnLoadError=False), "checker")
+ checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
+ exitOnError=False,
+ updateOnError=True,
+ warnOnlyOnLoadError=False),
+ "checker")
checker.itb = Parent.itb
checker.dtb = Parent.dtb
params->dtb = dtb;
params->system = system;
params->cpu_id = cpu_id;
-#if FULL_SYSTEM
params->profile = profile;
-#else
params->process = workload;
-#endif
O3Checker *cpu = new O3Checker(params);
return cpu;
void squashAfter(ThreadID tid, DynInstPtr &head_inst,
uint64_t squash_after_seq_num);
-#if FULL_SYSTEM
/** Handles processing an interrupt. */
void handleInterrupt();
/** Get fetch redirecting so we can handle an interrupt */
void propagateInterrupt();
-#endif // FULL_SYSTEM
/** Commits as many instructions as possible. */
void commitInsts();
#include "arch/utility.hh"
#include "base/loader/symtab.hh"
#include "base/cp_annotate.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/o3/commit.hh"
#include "debug/O3PipeView.hh"
#include "params/DerivO3CPU.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
#if USE_CHECKER
#include "cpu/checker/cpu.hh"
pc[tid].set(0);
lastCommitedSeqNum[tid] = 0;
}
-#if FULL_SYSTEM
interrupt = NoFault;
-#endif
}
template <class Impl>
updateStatus();
}
-#if FULL_SYSTEM
template <class Impl>
void
DefaultCommit<Impl>::handleInterrupt()
toIEW->commitInfo[0].interruptPending = true;
}
-#endif // FULL_SYSTEM
-
template <class Impl>
void
DefaultCommit<Impl>::commit()
{
-
-#if FULL_SYSTEM
- // Check for any interrupt that we've already squashed for and start processing it.
- if (interrupt != NoFault)
- handleInterrupt();
-
- // Check if we have a interrupt and get read to handle it
- if (cpu->checkInterrupts(cpu->tcBase(0)))
- propagateInterrupt();
-#endif // FULL_SYSTEM
+ if (FullSystem) {
+ // Check for any interrupt that we've already squashed for and start
+ // processing it.
+ if (interrupt != NoFault)
+ handleInterrupt();
+
+ // Check if we have a interrupt and get read to handle it
+ if (cpu->checkInterrupts(cpu->tcBase(0)))
+ propagateInterrupt();
+ }
////////////////////////////////////
// Check for any possible squashes, handle them first
updateComInstStats(head_inst);
-#if FULL_SYSTEM
- if (thread[tid]->profile) {
- thread[tid]->profilePC = head_inst->instAddr();
- ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
- head_inst->staticInst);
+ if (FullSystem) {
+ if (thread[tid]->profile) {
+ thread[tid]->profilePC = head_inst->instAddr();
+ ProfileNode *node = thread[tid]->profile->consume(
+ thread[tid]->getTC(), head_inst->staticInst);
- if (node)
- thread[tid]->profileNode = node;
- }
- if (CPA::available()) {
- if (head_inst->isControl()) {
- ThreadContext *tc = thread[tid]->getTC();
- CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
+ if (node)
+ thread[tid]->profileNode = node;
+ }
+ if (CPA::available()) {
+ if (head_inst->isControl()) {
+ ThreadContext *tc = thread[tid]->getTC();
+ CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
+ }
}
}
-#endif
DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
head_inst->seqNum, head_inst->pcState());
if (head_inst->traceData) {
*/
#include "arch/kernel_stats.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/o3/cpu.hh"
#include "debug/Quiesce.hh"
#include "enums/MemoryMode.hh"
#include "sim/core.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"
if (params->checker) {
BaseCPU *temp_checker = params->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
-#if FULL_SYSTEM
checker->setSystem(params->system);
-#endif
} else {
checker = NULL;
}
#endif // USE_CHECKER
-#if !FULL_SYSTEM
- thread.resize(numThreads);
- tids.resize(numThreads);
-#endif
+ if (!FullSystem) {
+ thread.resize(numThreads);
+ tids.resize(numThreads);
+ }
// The stages also need their CPU pointer setup. However this
// must be done at the upper level CPU because they have pointers
rename.setIEWStage(&iew);
rename.setCommitStage(&commit);
-#if !FULL_SYSTEM
- ThreadID active_threads = params->workload.size();
+ ThreadID active_threads;
+ if (FullSystem) {
+ active_threads = 1;
+ } else {
+ active_threads = params->workload.size();
- if (active_threads > Impl::MaxThreads) {
- panic("Workload Size too large. Increase the 'MaxThreads'"
- "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
- "edit your workload size.");
+ if (active_threads > Impl::MaxThreads) {
+ panic("Workload Size too large. Increase the 'MaxThreads' "
+ "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
+ "or edit your workload size.");
+ }
}
-#else
- ThreadID active_threads = 1;
-#endif
//Make Sure That this a Valid Architeture
assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
this->thread.resize(this->numThreads);
for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
-#if FULL_SYSTEM
- // SMT is not supported in FS mode yet.
- assert(this->numThreads == 1);
- this->thread[tid] = new Thread(this, 0, NULL);
-#else
- if (tid < params->workload.size()) {
- DPRINTF(O3CPU, "Workload[%i] process is %#x",
- tid, this->thread[tid]);
- this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
- (typename Impl::O3CPU *)(this),
- tid, params->workload[tid]);
-
- //usedTids[tid] = true;
- //threadMap[tid] = tid;
+ if (FullSystem) {
+ // SMT is not supported in FS mode yet.
+ assert(this->numThreads == 1);
+ this->thread[tid] = new Thread(this, 0, NULL);
} else {
- //Allocate Empty thread so M5 can use later
- //when scheduling threads to CPU
- Process* dummy_proc = NULL;
-
- this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
- (typename Impl::O3CPU *)(this),
- tid, dummy_proc);
- //usedTids[tid] = false;
+ if (tid < params->workload.size()) {
+ DPRINTF(O3CPU, "Workload[%i] process is %#x",
+ tid, this->thread[tid]);
+ this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
+ (typename Impl::O3CPU *)(this),
+ tid, params->workload[tid]);
+
+ //usedTids[tid] = true;
+ //threadMap[tid] = tid;
+ } else {
+ //Allocate Empty thread so M5 can use later
+ //when scheduling threads to CPU
+ Process* dummy_proc = NULL;
+
+ this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
+ (typename Impl::O3CPU *)(this),
+ tid, dummy_proc);
+ //usedTids[tid] = false;
+ }
}
-#endif // !FULL_SYSTEM
ThreadContext *tc;
assert(o3_tc->cpu);
o3_tc->thread = this->thread[tid];
-#if FULL_SYSTEM
- // Setup quiesce event.
- this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
-#endif
+ if (FullSystem) {
+ // Setup quiesce event.
+ this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
+ }
// Give the thread the TC.
this->thread[tid]->tc = tc;
commit.tick();
-#if !FULL_SYSTEM
- doContextSwitch();
-#endif
+ if (!FullSystem)
+ doContextSwitch();
// Now advance the time buffers
timeBuffer.advance();
}
}
-#if !FULL_SYSTEM
- updateThreadPriority();
-#endif
+ if (!FullSystem)
+ updateThreadPriority();
}
template <class Impl>
for (ThreadID tid = 0; tid < numThreads; ++tid)
thread[tid]->inSyscall = true;
-#if FULL_SYSTEM
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- ThreadContext *src_tc = threadContexts[tid];
- TheISA::initCPU(src_tc, src_tc->contextId());
+ if (FullSystem) {
+ for (ThreadID tid = 0; tid < numThreads; tid++) {
+ ThreadContext *src_tc = threadContexts[tid];
+ TheISA::initCPU(src_tc, src_tc->contextId());
+ }
}
-#endif
// Clear inSyscall.
for (int tid = 0; tid < numThreads; ++tid)
DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
// Will change now that the PC and thread state is internal to the CPU
// and not in the ThreadContext.
-#if FULL_SYSTEM
- ThreadContext *src_tc = system->threadContexts[tid];
-#else
- ThreadContext *src_tc = tcBase(tid);
-#endif
+ ThreadContext *src_tc;
+ if (FullSystem)
+ src_tc = system->threadContexts[tid];
+ else
+ src_tc = tcBase(tid);
//Bind Int Regs to Rename Map
for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
DerivO3CPU *
DerivO3CPUParams::create()
{
-#if FULL_SYSTEM
- // Full-system only supports a single thread for the moment.
- ThreadID actual_num_threads = 1;
-#else
- if (workload.size() > numThreads) {
- fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
- workload.size(), numThreads);
- } else if (workload.size() == 0) {
- fatal("Must specify at least one workload!");
+ ThreadID actual_num_threads;
+ if (FullSystem) {
+ // Full-system only supports a single thread for the moment.
+ actual_num_threads = 1;
+ } else {
+ if (workload.size() > numThreads) {
+ fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
+ workload.size(), numThreads);
+ } else if (workload.size() == 0) {
+ fatal("Must specify at least one workload!");
+ }
+
+ // In non-full-system mode, we infer the number of threads from
+ // the workload if it's not explicitly specified.
+ actual_num_threads =
+ (numThreads >= workload.size()) ? numThreads : workload.size();
}
-
- // In non-full-system mode, we infer the number of threads from
- // the workload if it's not explicitly specified.
- ThreadID actual_num_threads =
- (numThreads >= workload.size()) ? numThreads : workload.size();
-#endif
numThreads = actual_num_threads;
#include "arch/types.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/o3/decode.hh"
#include "cpu/inst_seq.hh"
#include "debug/Activity.hh"
#include "debug/Decode.hh"
#include "params/DerivO3CPU.hh"
+#include "sim/full_system.hh"
using namespace std;
if (decodeStatus[tid] == Blocked ||
decodeStatus[tid] == Unblocking) {
-#if !FULL_SYSTEM
- // In syscall emulation, we can have both a block and a squash due
- // to a syscall in the same cycle. This would cause both signals to
- // be high. This shouldn't happen in full system.
- // @todo: Determine if this still happens.
- if (toFetch->decodeBlock[tid]) {
- toFetch->decodeBlock[tid] = 0;
- } else {
+ if (FullSystem) {
toFetch->decodeUnblock[tid] = 1;
+ } else {
+ // In syscall emulation, we can have both a block and a squash due
+ // to a syscall in the same cycle. This would cause both signals
+ // to be high. This shouldn't happen in full system.
+ // @todo: Determine if this still happens.
+ if (toFetch->decodeBlock[tid])
+ toFetch->decodeBlock[tid] = 0;
+ else
+ toFetch->decodeUnblock[tid] = 1;
}
-#else
- toFetch->decodeUnblock[tid] = 1;
-#endif
}
// Set status to squashing.
#include <cstring>
#include "arch/isa_traits.hh"
+#include "arch/tlb.hh"
#include "arch/utility.hh"
+#include "arch/vtophys.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "sim/byteswap.hh"
#include "sim/core.hh"
#include "sim/eventq.hh"
-
-#if FULL_SYSTEM
-#include "arch/tlb.hh"
-#include "arch/vtophys.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
-#endif // FULL_SYSTEM
using namespace std;
DPRINTF(Fetch, "Running stage.\n");
- #if FULL_SYSTEM
- if (fromCommit->commitInfo[0].interruptPending) {
- interruptPending = true;
- }
+ if (FullSystem) {
+ if (fromCommit->commitInfo[0].interruptPending) {
+ interruptPending = true;
+ }
- if (fromCommit->commitInfo[0].clearInterrupt) {
- interruptPending = false;
+ if (fromCommit->commitInfo[0].clearInterrupt) {
+ interruptPending = false;
+ }
}
-#endif
for (threadFetched = 0; threadFetched < numFetchingThreads;
threadFetched++) {
/** D-cache port. */
DcachePort dcachePort;
-#if FULL_SYSTEM
/** Tell the CPU to update the Phys and Virt ports. */
void updateMemPorts() { cpu->updateMemPorts(); }
-#endif
protected:
/** The LSQ policy for SMT mode. */
{
Port::setPeer(port);
-#if FULL_SYSTEM
// Update the ThreadContext's memory ports (Functional/Virtual
// Ports)
lsq->updateMemPorts();
-#endif
}
template <class Impl>
#include <vector>
#include "arch/isa_traits.hh"
+#include "arch/kernel_stats.hh"
#include "arch/types.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
#include "debug/IEW.hh"
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#endif
-
/**
* Simple physical register file class.
* Right now this is specific to Alpha until we decide if/how to make things
/** Floating point register file. */
PhysFloatReg *floatRegFile;
-#if FULL_SYSTEM
private:
int intrflag; // interrupt flag
-#endif
private:
/** CPU pointer. */
* Korey Sewell
*/
+#include "arch/kernel_stats.hh"
#include "arch/registers.hh"
#include "config/the_isa.hh"
#include "cpu/o3/thread_context.hh"
O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
{
// some things should already be set up
-#if FULL_SYSTEM
assert(getSystemPtr() == old_context->getSystemPtr());
-#endif
assert(getProcessPtr() == old_context->getProcessPtr());
// copy over functional state
setContextId(old_context->contextId());
setThreadId(old_context->threadId());
-#if !FULL_SYSTEM
- thread->funcExeInst = old_context->readFuncExeInst();
-#else
- EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
- if (other_quiesce) {
- // Point the quiesce event's TC at this TC so that it wakes up
- // the proper CPU.
- other_quiesce->tc = this;
+ if (FullSystem) {
+ EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
+ if (other_quiesce) {
+ // Point the quiesce event's TC at this TC so that it wakes up
+ // the proper CPU.
+ other_quiesce->tc = this;
+ }
+ if (thread->quiesceEvent) {
+ thread->quiesceEvent->tc = this;
+ }
+
+ // Transfer kernel stats from one CPU to the other.
+ thread->kernelStats = old_context->getKernelStats();
+ cpu->lockFlag = false;
+ } else {
+ thread->funcExeInst = old_context->readFuncExeInst();
}
- if (thread->quiesceEvent) {
- thread->quiesceEvent->tc = this;
- }
-
- // Transfer kernel stats from one CPU to the other.
- thread->kernelStats = old_context->getKernelStats();
-// storeCondFailures = 0;
- cpu->lockFlag = false;
-#endif
old_context->setStatus(ThreadContext::Halted);
if (thread->status() == ThreadContext::Active)
return;
-#if FULL_SYSTEM
thread->lastActivate = curTick();
-#endif
-
thread->setStatus(ThreadContext::Active);
// status() == Suspended
if (thread->status() == ThreadContext::Suspended)
return;
-#if FULL_SYSTEM
thread->lastActivate = curTick();
thread->lastSuspend = curTick();
-#endif
-/*
-#if FULL_SYSTEM
- // Don't change the status from active if there are pending interrupts
- if (cpu->checkInterrupts()) {
- assert(status() == ThreadContext::Active);
- return;
- }
-#endif
-*/
+
thread->setStatus(ThreadContext::Suspended);
cpu->suspendContext(thread->threadId());
}
void
O3ThreadContext<Impl>::regStats(const std::string &name)
{
-#if FULL_SYSTEM
- thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
- thread->kernelStats->regStats(name + ".kern");
-#endif
+ if (FullSystem) {
+ thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+ thread->kernelStats->regStats(name + ".kern");
+ }
}
template <class Impl>
void
O3ThreadContext<Impl>::serialize(std::ostream &os)
{
-#if FULL_SYSTEM
- if (thread->kernelStats)
+ if (FullSystem && thread->kernelStats)
thread->kernelStats->serialize(os);
-#endif
-
}
template <class Impl>
void
O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
{
-#if FULL_SYSTEM
- if (thread->kernelStats)
+ if (FullSystem && thread->kernelStats)
thread->kernelStats->unserialize(cp, section);
-#endif
-
}
template <class Impl>
TheISA::copyRegs(tc, this);
thread->inSyscall = false;
-#if !FULL_SYSTEM
- this->thread->funcExeInst = tc->readFuncExeInst();
-#endif
+ if (!FullSystem)
+ this->thread->funcExeInst = tc->readFuncExeInst();
}
template <class Impl>
#include "base/output.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
+#include "sim/full_system.hh"
#include "sim/sim_exit.hh"
class EndQuiesceEvent;
: ThreadState(_cpu, _thread_num, _process),
cpu(_cpu), inSyscall(0), trapPending(0)
{
-#if FULL_SYSTEM
- if (cpu->params()->profile) {
- profile = new FunctionProfile(cpu->params()->system->kernelSymtab);
- Callback *cb =
- new MakeCallback<O3ThreadState,
- &O3ThreadState::dumpFuncProfile>(this);
- registerExitCallback(cb);
- }
+ if (FullSystem) {
+ if (cpu->params()->profile) {
+ profile = new FunctionProfile(
+ cpu->params()->system->kernelSymtab);
+ Callback *cb =
+ new MakeCallback<O3ThreadState,
+ &O3ThreadState::dumpFuncProfile>(this);
+ registerExitCallback(cb);
+ }
- // let's fill with a dummy node for now so we don't get a segfault
- // on the first cycle when there's no node available.
- static ProfileNode dummyNode;
- profileNode = &dummyNode;
- profilePC = 3;
-#endif
+ // let's fill with a dummy node for now so we don't get a segfault
+ // on the first cycle when there's no node available.
+ static ProfileNode dummyNode;
+ profileNode = &dummyNode;
+ profilePC = 3;
+ }
}
/** Pointer to the ThreadContext of this thread. */
numThreads = Param.Unsigned("number of HW thread contexts")
- if not buildEnv['FULL_SYSTEM']:
- mem = Param.FunctionalMemory(NULL, "memory")
+ mem = Param.FunctionalMemory(NULL, "memory")
width = Param.Unsigned("Width")
frontEndWidth = Param.Unsigned("Front end width")
// thread->funcExeInst--;
if (inst->isNonSpeculative()) {
-#if !FULL_SYSTEM
// Hack to make sure syscalls aren't executed until all stores
// write back their data. This direct communication shouldn't
// be used for anything other than this.
DPRINTF(BE, "Waiting for all stores to writeback.\n");
return false;
}
-#endif
DPRINTF(BE, "Encountered a store or non-speculative "
"instruction at the head of the ROB, PC %#x.\n",
if (inst_fault != NoFault) {
if (!inst->isNop()) {
-#if FULL_SYSTEM
DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
inst->seqNum, inst->readPC());
// generateTrapEvent();
return false;
-#else // !FULL_SYSTEM
- panic("fault (%d) detected @ PC %08p", inst_fault,
- inst->PC);
-#endif // FULL_SYSTEM
}
}
// Write the done sequence number here.
toIEW->doneSeqNum = inst->seqNum;
-#if FULL_SYSTEM
int count = 0;
Addr oldpc;
do {
// squashPending = true;
return false;
}
-#endif
return true;
}
params->dtb = dtb;
params->system = system;
params->cpu_id = cpu_id;
-#if FULL_SYSTEM
params->profile = profile;
-#else
params->process = workload;
-#endif
OzoneChecker *cpu = new OzoneChecker(params);
return cpu;
#include <set>
+#include "arch/alpha/tlb.hh"
#include "base/statistics.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "sim/eventq.hh"
// forward declarations
-#if FULL_SYSTEM
-#include "arch/alpha/tlb.hh"
-
-namespace TheISA
-{
- class TLB;
-}
-class PhysicalMemory;
-class MemoryController;
namespace TheISA {
namespace Kernel {
class Statistics;
};
+ class TLB;
};
-#else
-
-class Process;
-
-#endif // FULL_SYSTEM
-
class Checkpoint;
class EndQuiesceEvent;
+class MemoryController;
class MemObject;
+class PhysicalMemory;
+class Process;
class Request;
namespace Trace {
TheISA::TLB * getDTBPtr() { return cpu->dtb; }
-#if FULL_SYSTEM
System *getSystemPtr() { return cpu->system; }
PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
TheISA::Kernel::Statistics *getKernelStats()
{ return thread->getKernelStats(); }
-#endif
+
Process *getProcessPtr() { return thread->getProcessPtr(); }
TranslatingPort *getMemPort() { return thread->getMemPort(); }
/// Set the status to Halted.
void halt();
-#if FULL_SYSTEM
void dumpFuncProfile();
-#endif
void takeOverFrom(ThreadContext *old_context);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
-#if FULL_SYSTEM
EndQuiesceEvent *getQuiesceEvent();
Tick readLastActivate();
void profileClear();
void profileSample();
-#endif
int threadId();
bool misspeculating() { return false; }
-#if !FULL_SYSTEM
Counter readFuncExeInst() { return thread->funcExeInst; }
void setFuncExeInst(Counter new_val)
{ thread->funcExeInst = new_val; }
-#endif
};
// Ozone specific thread context
int switchCount;
-#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
bool interval_stats;
TheISA::TLB *dtb;
System *system;
PhysicalMemory *physmem;
-#endif
virtual Port *getPort(const std::string &name, int idx);
void dumpInsts() { frontEnd->dumpInsts(); }
-#if FULL_SYSTEM
Fault hwrei();
bool simPalCheck(int palFunc);
void processInterrupts();
-#else
void syscall(uint64_t &callnum);
-#endif
ThreadContext *tcBase() { return tc; }
{
DerivOzoneCPU *cpu;
-#if FULL_SYSTEM
- // Full-system only supports a single thread for the moment.
- ThreadID actual_num_threads = 1;
-#else
- // In non-full-system mode, we infer the number of threads from
- // the workload if it's not explicitly specified.
- ThreadID actual_num_threads =
- numThreads.isValid() ? numThreads : workload.size();
-
- if (workload.size() == 0) {
- fatal("Must specify at least one workload!");
+ if (FullSystem) {
+ // Full-system only supports a single thread for the moment.
+ ThreadID actual_num_threads = 1;
+ } else {
+ // In non-full-system mode, we infer the number of threads from
+ // the workload if it's not explicitly specified.
+ ThreadID actual_num_threads =
+ numThreads.isValid() ? numThreads : workload.size();
+
+ if (workload.size() == 0) {
+ fatal("Must specify at least one workload!");
+ }
}
-#endif
-
SimpleParams *params = new SimpleParams;
params->clock = clock;
params->system = system;
params->cpu_id = cpu_id;
-#if FULL_SYSTEM
params->profile = profile;
params->do_quiesce = do_quiesce;
params->do_checkpoint_insts = do_checkpoint_insts;
params->do_statistics_insts = do_statistics_insts;
-#else
params->workload = workload;
-// params->pTable = page_table;
-#endif // FULL_SYSTEM
params->checker = checker;
params->max_insts_any_thread = max_insts_any_thread;
* Nathan Binkert
*/
+#include "arch/alpha/osfpal.hh"
+#include "arch/faults.hh"
#include "arch/isa_traits.hh" // For MachInst
+#include "arch/kernel_stats.hh"
+#include "arch/tlb.hh"
+#include "arch/types.hh"
+#include "arch/vtophys.hh"
+#include "base/callback.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/ozone/cpu.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
+#include "cpu/profile.hh"
#include "cpu/quiesce_event.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
-#include "sim/sim_object.hh"
-#include "sim/stats.hh"
-
-#if FULL_SYSTEM
-#include "arch/alpha/osfpal.hh"
-#include "arch/faults.hh"
-#include "arch/kernel_stats.hh"
-#include "arch/tlb.hh"
-#include "arch/types.hh"
-#include "arch/vtophys.hh"
-#include "base/callback.hh"
-#include "cpu/profile.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
+#include "sim/process.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
+#include "sim/sim_object.hh"
+#include "sim/stats.hh"
#include "sim/system.hh"
-#else // !FULL_SYSTEM
-#include "sim/process.hh"
-#endif // FULL_SYSTEM
#if USE_CHECKER
#include "cpu/checker/thread_context.hh"
template <class Impl>
OzoneCPU<Impl>::OzoneCPU(Params *p)
-#if FULL_SYSTEM
- : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
-#else
- : BaseCPU(p), thread(this, 0, p->workload[0], 0),
- tickEvent(this, p->width),
-#endif
+ : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this,
+ p->width),
#ifndef NDEBUG
instcount(0),
#endif
#if USE_CHECKER
BaseCPU *temp_checker = p->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
-#if FULL_SYSTEM
checker->setSystem(p->system);
-#endif
checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
thread.tc = checkerTC;
tc = checkerTC;
itb = p->itb;
dtb = p->dtb;
-#if FULL_SYSTEM
- // Setup thread state stuff.
- thread.cpu = this;
- thread.setTid(0);
-
- thread.quiesceEvent = new EndQuiesceEvent(tc);
-
- system = p->system;
- physmem = p->system->physmem;
-
- if (p->profile) {
- thread.profile = new FunctionProfile(p->system->kernelSymtab);
- // @todo: This might be better as an ThreadContext instead of OzoneTC
- Callback *cb =
- new MakeCallback<OzoneTC,
- &OzoneTC::dumpFuncProfile>(&ozoneTC);
- registerExitCallback(cb);
- }
- // let's fill with a dummy node for now so we don't get a segfault
- // on the first cycle when there's no node available.
- static ProfileNode dummyNode;
- thread.profileNode = &dummyNode;
- thread.profilePC = 3;
-#else
- thread.cpu = this;
-#endif // !FULL_SYSTEM
+ if (FullSystem) {
+ // Setup thread state stuff.
+ thread.cpu = this;
+ thread.setTid(0);
+
+ thread.quiesceEvent = new EndQuiesceEvent(tc);
+
+ system = p->system;
+ physmem = p->system->physmem;
+
+ if (p->profile) {
+ thread.profile = new FunctionProfile(p->system->kernelSymtab);
+ // @todo: This might be better as an ThreadContext instead of
+ // OzoneTC
+ Callback *cb =
+ new MakeCallback<OzoneTC,
+ &OzoneTC::dumpFuncProfile>(&ozoneTC);
+ registerExitCallback(cb);
+ }
+
+ // let's fill with a dummy node for now so we don't get a segfault
+ // on the first cycle when there's no node available.
+ static ProfileNode dummyNode;
+ thread.profileNode = &dummyNode;
+ thread.profilePC = 3;
+ } else {
+ thread.cpu = this;
+ }
numInst = 0;
startNumInst = 0;
frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable);
-#if FULL_SYSTEM
- Port *mem_port;
- FunctionalPort *phys_port;
- VirtualPort *virt_port;
- phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
- name(), 0));
- mem_port = system->physmem->getPort("functional");
- mem_port->setPeer(phys_port);
- phys_port->setPeer(mem_port);
-
- virt_port = new VirtualPort(csprintf("%s-%d-vport",
- name(), 0));
- mem_port = system->physmem->getPort("functional");
- mem_port->setPeer(virt_port);
- virt_port->setPeer(mem_port);
-
- thread.setPhysPort(phys_port);
- thread.setVirtPort(virt_port);
-#endif
+ if (FullSystem) {
+ Port *mem_port;
+ FunctionalPort *phys_port;
+ VirtualPort *virt_port;
+ phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
+ name(), 0));
+ mem_port = system->physmem->getPort("functional");
+ mem_port->setPeer(phys_port);
+ phys_port->setPeer(mem_port);
+
+ virt_port = new VirtualPort(csprintf("%s-%d-vport",
+ name(), 0));
+ mem_port = system->physmem->getPort("functional");
+ mem_port->setPeer(virt_port);
+ virt_port->setPeer(mem_port);
+
+ thread.setPhysPort(phys_port);
+ thread.setVirtPort(virt_port);
+ }
DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
}
notIdleFraction++;
scheduleTickEvent(delay);
_status = Running;
-#if FULL_SYSTEM
if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
thread.quiesceEvent->deschedule();
-#endif
thread.setStatus(ThreadContext::Active);
frontEnd->wakeFromQuiesce();
}
// Mark this as in syscall so it won't need to squash
thread.inSyscall = true;
-#if FULL_SYSTEM
- for (int i = 0; i < threadContexts.size(); ++i) {
- ThreadContext *tc = threadContexts[i];
+ if (FullSystem) {
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
- // initialize CPU, including PC
- TheISA::initCPU(tc, tc->contextId());
+ // initialize CPU, including PC
+ TheISA::initCPU(tc, tc->contextId());
+ }
}
-#endif
frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable);
thread.getTC()->copyArchRegs(temp.getTC());
}
-#if FULL_SYSTEM
template <class Impl>
Addr
OzoneCPU<Impl>::dbg_vtophys(Addr addr)
{
return vtophys(tc, addr);
}
-#endif // FULL_SYSTEM
-#if FULL_SYSTEM
template <class Impl>
void
OzoneCPU<Impl>::wakeup()
{
if (_status == Idle) {
DPRINTF(IPI,"Suspended Processor awoke\n");
-// thread.activate();
// Hack for now. Otherwise might have to go through the tc, or
// I need to figure out what's the right thing to call.
activateContext(thread.threadId(), 1);
}
}
-#endif // FULL_SYSTEM
/* start simulation, program loaded, processor precise state initialized */
template <class Impl>
backEnd->generateTCEvent();
}
-#if !FULL_SYSTEM
template <class Impl>
void
OzoneCPU<Impl>::syscall(uint64_t &callnum)
frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable);
}
-#else
+
template <class Impl>
Fault
OzoneCPU<Impl>::hwrei()
return true;
}
-#endif
template <class Impl>
BaseCPU *
cpu->haltContext(thread->threadId());
}
-#if FULL_SYSTEM
template <class Impl>
void
OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
{
thread->dumpFuncProfile();
}
-#endif
template <class Impl>
void
OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
{
// some things should already be set up
-#if FULL_SYSTEM
assert(getSystemPtr() == old_context->getSystemPtr());
-#endif
assert(getProcessPtr() == old_context->getProcessPtr());
// copy over functional state
setCpuId(old_context->cpuId());
setContextId(old_context->contextId());
-#if !FULL_SYSTEM
setFuncExeInst(old_context->readFuncExeInst());
-#else
EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
if (other_quiesce) {
// Point the quiesce event's TC at this TC so that it wakes up
void
OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
{
-#if FULL_SYSTEM
- thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
- thread->kernelStats->regStats(name + ".kern");
-#endif
+ if (FullSystem) {
+ thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+ thread->kernelStats->regStats(name + ".kern");
+ }
}
template <class Impl>
OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion)
{ }
-#if FULL_SYSTEM
template <class Impl>
EndQuiesceEvent *
OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
{
thread->profileSample();
}
-#endif
template <class Impl>
int
thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
}
-#if !FULL_SYSTEM
thread->funcExeInst = tc->readFuncExeInst();
-#endif
// Need to copy the TC values into the current rename table,
// copy the misc regs.
void setMiscReg(int misc_reg, const MiscReg &val);
-#if FULL_SYSTEM
Fault hwrei();
void trap(Fault fault);
bool simPalCheck(int palFunc);
-#else
void syscall(uint64_t &callnum);
-#endif
ListIt iqIt;
bool iqItValid;
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/ozone/dyn_inst.hh"
-#include "sim/faults.hh"
-
-#if FULL_SYSTEM
#include "kern/kernel_stats.hh"
-#endif
+#include "sim/faults.hh"
template <class Impl>
OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
this->thread->setMiscReg(misc_reg, val);
}
-#if FULL_SYSTEM
-
template <class Impl>
Fault
OzoneDynInst<Impl>::hwrei()
{
return this->cpu->simPalCheck(palFunc);
}
-#else
+
template <class Impl>
void
OzoneDynInst<Impl>::syscall(uint64_t &callnum)
{
this->cpu->syscall(callnum);
}
-#endif
numInstsReady[0]++;
++num_inst;
-#if FULL_SYSTEM
if (inst->isQuiesce()) {
-// warn("%lli: Quiesce instruction encountered, halting fetch!", curTick());
status = QuiescePending;
break;
}
-#endif
if (inst->predTaken()) {
// Start over with tick?
cacheBlkValid = false;
-#if !FULL_SYSTEM
-// pTable = params->pTable;
-#endif
fetchFault = NoFault;
serializeNext = false;
barrierInst = NULL;
void regStats() { }
-#if FULL_SYSTEM
void checkInterrupts();
-#endif
void tick();
void executeInsts();
thread->setFuncExeInst(0);
}
-#if FULL_SYSTEM
template <class Impl>
void
InorderBackEnd<Impl>::checkInterrupts()
setSquashInfoFromXC();
}
}
-#endif
template <class Impl>
void
// if (interrupt) then set thread PC, stall front end, record that
// I'm waiting for it to drain. (for now just squash)
-#if FULL_SYSTEM
- if (interruptBlocked || cpu->checkInterrupts(tc)) {
+ if (FullSystem && (interruptBlocked || cpu->checkInterrupts(tc))) {
if (!robEmpty()) {
interruptBlocked = true;
//AlphaDep
return;
}
}
-#endif
if (status != DcacheMissLoadStall &&
status != DcacheMissStoreStall) {
(*instsAdded)++;
}
-#if FULL_SYSTEM
if (faultFromFetch && robEmpty() && frontEnd->isEmpty()) {
handleFault();
} else {
executeInsts();
}
-#else
- executeInsts();
-#endif
}
}
thread->setPC(commitPC);
thread->setNextPC(inst->readNextPC());
-#if FULL_SYSTEM
- int count = 0;
- Addr oldpc;
- do {
- if (count == 0)
- assert(!thread->inSyscall && !thread->trapPending);
- oldpc = thread->readPC();
- cpu->system->pcEventQueue.service(
- thread->getXCProxy());
- count++;
- } while (oldpc != thread->readPC());
- if (count > 1) {
- DPRINTF(IBE, "PC skip function event, stopping commit\n");
- completed_last_inst = false;
- squashPending = true;
- break;
+ if (FullSystem) {
+ int count = 0;
+ Addr oldpc;
+ do {
+ if (count == 0)
+ assert(!thread->inSyscall && !thread->trapPending);
+ oldpc = thread->readPC();
+ cpu->system->pcEventQueue.service(
+ thread->getXCProxy());
+ count++;
+ } while (oldpc != thread->readPC());
+ if (count > 1) {
+ DPRINTF(IBE, "PC skip function event, stopping commit\n");
+ completed_last_inst = false;
+ squashPending = true;
+ break;
+ }
}
-#endif
Fault inst_fault = NoFault;
}
if (inst_fault != NoFault) {
-#if FULL_SYSTEM
DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n",
inst->seqNum, inst->readPC());
squashPending = true;
- // Generate trap squash event.
-// generateTrapEvent(tid);
completed_last_inst = false;
break;
-#else // !FULL_SYSTEM
- panic("fault (%d) detected @ PC %08p", inst_fault,
- inst->PC);
-#endif // FULL_SYSTEM
}
for (int i = 0; i < inst->numDestRegs(); ++i) {
fromCommit = comm->getWire(-1);
}
-#if FULL_SYSTEM
template <class Impl>
void
LWBackEnd<Impl>::checkInterrupts()
}
}
}
-#endif
template <class Impl>
void
wbCycle = 0;
-#if FULL_SYSTEM
checkInterrupts();
-#endif
if (trapSquash) {
assert(!tcSquash);
(inst->isStoreConditional() && inst->getFault() == NoFault) ||
inst->isMemBarrier() ||
inst->isWriteBarrier()) {
-#if !FULL_SYSTEM
- // Hack to make sure syscalls aren't executed until all stores
- // write back their data. This direct communication shouldn't
- // be used for anything other than this.
- if (inst_num > 0 || LSQ.hasStoresToWB())
-#else
if ((inst->isMemBarrier() || inst->isWriteBarrier() ||
- inst->isQuiesce()) &&
- LSQ.hasStoresToWB())
-#endif
+ inst->isQuiesce()) && LSQ.hasStoresToWB())
{
DPRINTF(BE, "Waiting for all stores to writeback.\n");
return false;
++freed_regs;
}
-#if FULL_SYSTEM
- if (thread->profile) {
-// bool usermode =
-// (xc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
-// thread->profilePC = usermode ? 1 : inst->readPC();
+ if (FullSystem && thread->profile) {
thread->profilePC = inst->readPC();
ProfileNode *node = thread->profile->consume(thread->getTC(),
inst->staticInst);
if (node)
thread->profileNode = node;
}
-#endif
if (inst->traceData) {
inst->traceData->setFetchSeq(inst->seqNum);
toIEW->doneSeqNum = inst->seqNum;
lastCommitCycle = curTick();
-#if FULL_SYSTEM
- int count = 0;
- Addr oldpc;
- do {
- if (count == 0)
- assert(!thread->inSyscall && !thread->trapPending);
- oldpc = thread->readPC();
- cpu->system->pcEventQueue.service(
- thread->getTC());
- count++;
- } while (oldpc != thread->readPC());
- if (count > 1) {
- DPRINTF(BE, "PC skip function event, stopping commit\n");
- tcSquash = true;
- return false;
+ if (FullSystem) {
+ int count = 0;
+ Addr oldpc;
+ do {
+ if (count == 0)
+ assert(!thread->inSyscall && !thread->trapPending);
+ oldpc = thread->readPC();
+ cpu->system->pcEventQueue.service(
+ thread->getTC());
+ count++;
+ } while (oldpc != thread->readPC());
+ if (count > 1) {
+ DPRINTF(BE, "PC skip function event, stopping commit\n");
+ tcSquash = true;
+ return false;
+ }
}
-#endif
return true;
}
{
SimpleOzoneCPU *cpu;
-#if FULL_SYSTEM
- // Full-system only supports a single thread for the moment.
- ThreadID actual_num_threads = 1;
-#else
- // In non-full-system mode, we infer the number of threads from
- // the workload if it's not explicitly specified.
- ThreadID actual_num_threads =
- numThreads.isValid() ? numThreads : workload.size();
-
- if (workload.size() == 0) {
- fatal("Must specify at least one workload!");
+ if (FullSystem) {
+ // Full-system only supports a single thread for the moment.
+ ThreadID actual_num_threads = 1;
+ } else {
+ // In non-full-system mode, we infer the number of threads from
+ // the workload if it's not explicitly specified.
+ ThreadID actual_num_threads =
+ numThreads.isValid() ? numThreads : workload.size();
+
+ if (workload.size() == 0) {
+ fatal("Must specify at least one workload!");
+ }
}
-#endif
-
SimpleParams *params = new SimpleParams;
params->clock = clock;
params->system = system;
params->cpu_id = cpu_id;
-#if !FULL_SYSTEM
params->workload = workload;
-// params->pTable = page_table;
-#endif // FULL_SYSTEM
params->mem = mem;
params->checker = checker;
public:
TheISA::TLB *itb; TheISA::TLB *dtb;
-#if !FULL_SYSTEM
std::vector<Process *> workload;
-#endif // FULL_SYSTEM
//Page Table
PageTable *pTable;
class Event;
//class Process;
-#if FULL_SYSTEM
class EndQuiesceEvent;
+class FunctionalMemory;
class FunctionProfile;
-class ProfileNode;
-#else
class Process;
-class FunctionalMemory;
-#endif
+class ProfileNode;
// Maybe this ozone thread state should only really have committed state?
// I need to think about why I'm using this and what it's useful for. Clearly
typedef typename Impl::CPUType CPUType;
typedef TheISA::MiscReg MiscReg;
-#if FULL_SYSTEM
OzoneThreadState(CPUType *_cpu, int _thread_num)
: ThreadState(_cpu, -1, _thread_num),
intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0)
profilePC = 3;
miscRegFile.clear();
}
-#else
+
OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process)
: ThreadState(_cpu, -1, _thread_num, _process),
cpu(_cpu), inSyscall(0), trapPending(0)
{
miscRegFile.clear();
}
-#endif
RenameTable<Impl> renameTable;
void setNextPC(uint64_t val)
{ nextPC = val; }
-#if FULL_SYSTEM
void dumpFuncProfile()
{
std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
profile->dump(tc, *os);
}
-#endif
};
#endif // __CPU_OZONE_THREAD_STATE_HH__
#include "base/debug.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/pc_event.hh"
#include "cpu/thread_context.hh"
delete this;
}
-#if FULL_SYSTEM
void
sched_break_pc_sys(System *sys, Addr addr)
{
}
}
-#endif
if (FullSystem) {
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
-#if FULL_SYSTEM
ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
TheISA::initCPU(tc, tc->contextId());
-#endif
}
}
if (hasPhysMemPort) {
AtomicSimpleCPUParams::create()
{
numThreads = 1;
-#if !FULL_SYSTEM
if (!FullSystem && workload.size() != 1)
panic("only one workload allowed");
-#endif
return new AtomicSimpleCPU(this);
}
#include "params/BaseSimpleCPU.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
+#include "sim/full_system.hh"
#include "sim/sim_events.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
: BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
{
-#if FULL_SYSTEM
- thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
-#else
- thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
- p->itb, p->dtb);
-#endif // !FULL_SYSTEM
+ if (FullSystem)
+ thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
+ else
+ thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
+ p->itb, p->dtb);
thread->setStatus(ThreadContext::Halted);
BaseCPU::init();
if (FullSystem) {
for (int i = 0; i < threadContexts.size(); ++i) {
-#if FULL_SYSTEM
ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
TheISA::initCPU(tc, _cpuId);
-#endif
}
}
}
TimingSimpleCPUParams::create()
{
numThreads = 1;
-#if !FULL_SYSTEM
if (!FullSystem && workload.size() != 1)
panic("only one workload allowed");
-#endif
return new TimingSimpleCPU(this);
}
#include "mem/translating_port.hh"
#include "mem/vport.hh"
#include "params/BaseCPU.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
using namespace std;
// constructor
-#if !FULL_SYSTEM
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
TheISA::TLB *_itb, TheISA::TLB *_dtb)
: ThreadState(_cpu, _thread_num, _process),
clearArchRegs();
tc = new ProxyThreadContext<SimpleThread>(this);
}
-#else
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
TheISA::TLB *_itb, TheISA::TLB *_dtb,
bool use_kernel_stats)
if (use_kernel_stats)
kernelStats = new TheISA::Kernel::Statistics(system);
}
-#endif
SimpleThread::SimpleThread()
: ThreadState(NULL, -1, NULL)
SimpleThread::takeOverFrom(ThreadContext *oldContext)
{
// some things should already be set up
-#if FULL_SYSTEM
- assert(system == oldContext->getSystemPtr());
-#endif
+ if (FullSystem)
+ assert(system == oldContext->getSystemPtr());
assert(process == oldContext->getProcessPtr());
copyState(oldContext);
-#if FULL_SYSTEM
- EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
- if (quiesce) {
- // Point the quiesce event's TC at this TC so that it wakes up
- // the proper CPU.
- quiesce->tc = tc;
+ if (FullSystem) {
+ EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
+ if (quiesce) {
+ // Point the quiesce event's TC at this TC so that it wakes up
+ // the proper CPU.
+ quiesce->tc = tc;
+ }
+ if (quiesceEvent) {
+ quiesceEvent->tc = tc;
+ }
+
+ TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
+ if (stats) {
+ kernelStats = stats;
+ }
}
- if (quiesceEvent) {
- quiesceEvent->tc = tc;
- }
-
- TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
- if (stats) {
- kernelStats = stats;
- }
-#endif
storeCondFailures = 0;
{
copyState(context);
-#if FULL_SYSTEM
- EndQuiesceEvent *quiesce = context->getQuiesceEvent();
- if (quiesce) {
- quiesceEvent = quiesce;
- }
- TheISA::Kernel::Statistics *stats = context->getKernelStats();
- if (stats) {
- kernelStats = stats;
+ if (FullSystem) {
+ EndQuiesceEvent *quiesce = context->getQuiesceEvent();
+ if (quiesce) {
+ quiesceEvent = quiesce;
+ }
+ TheISA::Kernel::Statistics *stats = context->getKernelStats();
+ if (stats) {
+ kernelStats = stats;
+ }
}
-#endif
}
void
// copy over functional state
_status = oldContext->status();
copyArchRegs(oldContext);
-#if !FULL_SYSTEM
- funcExeInst = oldContext->readFuncExeInst();
-#endif
+ if (FullSystem)
+ funcExeInst = oldContext->readFuncExeInst();
_threadId = oldContext->threadId();
_contextId = oldContext->contextId();
lastActivate = curTick();
lastSuspend = curTick();
-/*
-#if FULL_SYSTEM
- // Don't change the status from active if there are pending interrupts
- if (cpu->checkInterrupts()) {
- assert(status() == ThreadContext::Active);
- return;
- }
-#endif
-*/
_status = ThreadContext::Suspended;
cpu->suspendContext(_threadId);
}
void
SimpleThread::regStats(const string &name)
{
-#if FULL_SYSTEM
- if (kernelStats)
+ if (FullSystem && kernelStats)
kernelStats->regStats(name + ".kern");
-#endif
}
void
Decoder decoder;
// constructor: initialize SimpleThread from given process structure
-#if FULL_SYSTEM
+ // FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
TheISA::TLB *_itb, TheISA::TLB *_dtb,
bool use_kernel_stats = true);
-#else
+ // SE
SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
TheISA::TLB *_itb, TheISA::TLB *_dtb);
-#endif
SimpleThread();
* Authors: Kevin Lim
*/
+#include "arch/kernel_stats.hh"
#include "base/output.hh"
#include "cpu/base.hh"
#include "cpu/profile.hh"
+#include "cpu/quiesce_event.hh"
#include "cpu/thread_state.hh"
#include "mem/port.hh"
#include "mem/translating_port.hh"
#include "mem/vport.hh"
+#include "sim/full_system.hh"
#include "sim/serialize.hh"
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "cpu/quiesce_event.hh"
-#endif
-
ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
: numInst(0), numLoad(0), _status(ThreadContext::Halted),
baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
-#if FULL_SYSTEM
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
- kernelStats(NULL),
-#endif
- process(_process), port(NULL), virtPort(NULL), physPort(NULL),
- funcExeInst(0), storeCondFailures(0)
+ kernelStats(NULL), process(_process), port(NULL), virtPort(NULL),
+ physPort(NULL), funcExeInst(0), storeCondFailures(0)
{
}
// thread_num and cpu_id are deterministic from the config
SERIALIZE_SCALAR(funcExeInst);
-#if FULL_SYSTEM
- Tick quiesceEndTick = 0;
- if (quiesceEvent->scheduled())
- quiesceEndTick = quiesceEvent->when();
- SERIALIZE_SCALAR(quiesceEndTick);
- if (kernelStats)
- kernelStats->serialize(os);
-#endif
+ if (FullSystem) {
+ Tick quiesceEndTick = 0;
+ if (quiesceEvent->scheduled())
+ quiesceEndTick = quiesceEvent->when();
+ SERIALIZE_SCALAR(quiesceEndTick);
+ if (kernelStats)
+ kernelStats->serialize(os);
+ }
}
void
// thread_num and cpu_id are deterministic from the config
UNSERIALIZE_SCALAR(funcExeInst);
-#if FULL_SYSTEM
- Tick quiesceEndTick;
- UNSERIALIZE_SCALAR(quiesceEndTick);
- if (quiesceEndTick)
- baseCpu->schedule(quiesceEvent, quiesceEndTick);
- if (kernelStats)
- kernelStats->unserialize(cp, section);
-#endif
+ if (FullSystem) {
+ Tick quiesceEndTick;
+ UNSERIALIZE_SCALAR(quiesceEndTick);
+ if (quiesceEndTick)
+ baseCpu->schedule(quiesceEvent, quiesceEndTick);
+ if (kernelStats)
+ kernelStats->unserialize(cp, section);
+ }
}
void
projects / gem5.git / commitdiff