Add links to other memory controller projects
authorJean THOMAS <git0@pub.jeanthomas.me>
Fri, 7 Aug 2020 18:35:47 +0000 (20:35 +0200)
committerJean THOMAS <git0@pub.jeanthomas.me>
Fri, 7 Aug 2020 18:35:47 +0000 (20:35 +0200)
doc/documentation.md

index 77ad88af79b6951f0c9043afdeae109f7cf78f2a..e1ecf58da1293981d08c2db822e06d2619858199 100644 (file)
@@ -7,4 +7,9 @@
 ## Memory chips
  
  * [A datasheet from Micron](https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/1gb_ddr3_sdram.pdf)
- * [Samsung DDR3 SDRAM Specification: Device Operation & Timing Diagram](https://www.samsung.com/semiconductor/global.semi/file/resource/2017/11/ddr3_device_operation_timing_diagram_rev14-2.pdf)
\ No newline at end of file
+ * [Samsung DDR3 SDRAM Specification: Device Operation & Timing Diagram](https://www.samsung.com/semiconductor/global.semi/file/resource/2017/11/ddr3_device_operation_timing_diagram_rev14-2.pdf)
+
+## Other open source memory controllers
+
+ * [Enjoy-Digital LiteDRAM](https://github.com/enjoy-digital/litedram)
+ * [UltraEmbedded core_ddr3_controller](https://github.com/ultraembedded/core_ddr3_controller)