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cache: fix longstanding prefetcher bug
author
Steve Reinhardt
<steve.reinhardt@amd.com>
Wed, 23 Jun 2010 04:29:43 +0000
(21:29 -0700)
committer
Steve Reinhardt
<steve.reinhardt@amd.com>
Wed, 23 Jun 2010 04:29:43 +0000
(21:29 -0700)
Thanks to Joe Gross for pointing this out (again?).
Apologies to anyone who pointed it out earlier and
we didn't listen.
src/mem/cache/cache_impl.hh
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diff --git
a/src/mem/cache/cache_impl.hh
b/src/mem/cache/cache_impl.hh
index d5eb38e48718041a7dbe6e26bbc476534dbc535b..8ff11b26fdeea47b073d39045e74affa892aecbf 100644
(file)
--- a/
src/mem/cache/cache_impl.hh
+++ b/
src/mem/cache/cache_impl.hh
@@
-1308,7
+1308,7
@@
Cache<TagStore>::getNextMSHR()
// fall through... no pending requests. Try a prefetch.
assert(!miss_mshr && !write_mshr);
- if (!mshrQueue.isFull()) {
+ if (
prefetcher &&
!mshrQueue.isFull()) {
// If we have a miss queue slot, we can try a prefetch
PacketPtr pkt = prefetcher->getPacket();
if (pkt) {