sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets

diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
new file mode 100644 (file)
index 0000000..10a69ee
--- /dev/null
+++ b/misoclib/mem/sdram/module.py
@@ -0,0 +1,70 @@
+from math import ceil
+
+from migen.fhdl.std import *
+from misoclib.mem import sdram
+
+class SDRAMModule:
+       def __init__(self, clk_freq, geom_settings, timing_settings):
+               self.clk_freq = clk_freq
+               self.geom_settings = sdram.GeomSettings(
+                       bank_a=log2_int(geom_settings["nbanks"]),
+                       row_a=log2_int(geom_settings["nrows"]),
+                       col_a=log2_int(geom_settings["ncols"])
+               )
+               self.timing_settings = sdram.TimingSettings(
+                       tRP=self.ns(timing_settings["tRP"]),
+                       tRCD=self.ns(timing_settings["tRCD"]),
+                       tWR=self.ns(timing_settings["tWR"]),
+                       tWTR=timing_settings["tWTR"],
+                       tREFI=self.ns(timing_settings["tREFI"], False),
+                       tRFC=self.ns(timing_settings["tRFC"])
+               )
+
+       def ns(self, t, margin=True):
+               clk_period_ns = 1000000000/self.clk_freq
+               if margin:
+                       t += clk_period_ns/2
+               return ceil(t/clk_period_ns)
+
+# SDR
+class IS42S16160(SDRAMModule):
+       geom_settings = {
+               "nbanks":       4,
+               "nrows":        8192,
+               "ncols":        512
+       }
+       timing_settings = {
+               "tRP":          20,
+               "tRCD":         20,
+               "tWR":          20,
+               "tWTR":         2,
+               "tREFI":        7800,
+               "tRFC":         70
+       }
+       def __init__(self, clk_freq):
+               SDRAMModule.__init__(self, clk_freq, self.geom_settings, self.timing_settings)
+
+class MT48LC4M16(SDRAMModule):
+       geom_settings = {
+               "nbanks":       4,
+               "nrows":        4096,
+               "ncols":        256
+       }
+       timing_settings = {
+               "tRP":          15,
+               "tRCD":         15,
+               "tWR":          14,
+               "tWTR":         2,
+               "tREFI":        64*1000*1000/4096,
+               "tRFC":         66
+       }
+       def __init__(self, clk_freq):
+               SDRAMModule.__init__(self, clk_freq, self.geom_settings, self.timing_settings)
+
+# DDR
+
+# LPDDR
+
+# DDR2
+
+# DDR3

diff --git a/targets/de0nano.py b/targets/de0nano.py
index c1be8d68f90c8dc8d9b7e0ca940a61a51bb8f07f..d98468e3b8bfcb71655ace1898fc10b060af0afc 100644 (file)
--- a/targets/de0nano.py
+++ b/targets/de0nano.py
@@ -3,6 +3,7 @@ from migen.bus import wishbone
 
 from misoclib.cpu.peripherals import gpio
 from misoclib.mem import sdram
+from misoclib.mem.sdram.module import IS42S16160
 from misoclib.mem.sdram.phy import gensdrphy
 from misoclib.com import uart
 from misoclib.soc.sdram import SDRAMSoC
@@ -90,27 +91,14 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform)
 
                if not self.with_main_ram:
-                       sdram_geom_settings = sdram.GeomSettings(
-                               bank_a=2,
-                               row_a=13,
-                               col_a=9
-                       )
-
-                       sdram_timing_settings = sdram.TimingSettings(
-                               tRP=self.ns(20),
-                               tRCD=self.ns(20),
-                               tWR=self.ns(20),
-                               tWTR=2,
-                               tREFI=self.ns(7800, False),
-                               tRFC=self.ns(70)
-                       )
+                       sdram_module = IS42S16160(self.clk_freq)
                        sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,
                                read_time=32,
                                write_time=16
                        )
                        self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
-                       self.register_sdram_phy(self.sdrphy, sdram_geom_settings, sdram_timing_settings,
+                       self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings,
                                sdram_controller_settings)
 
 default_subtarget = BaseSoC

diff --git a/targets/ppro.py b/targets/ppro.py
index ffd83195b55171ae7cacf7e09d200a1018da2c77..d69b9e28bd580ff8c17fa5ef1d798fe889fe401b 100644 (file)
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -4,6 +4,7 @@ from migen.fhdl.std import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoclib.mem import sdram
+from misoclib.mem.sdram.module import MT48LC4M16
 from misoclib.mem.sdram.phy import gensdrphy
 from misoclib.mem.flash import spiflash
 from misoclib.soc.sdram import SDRAMSoC
@@ -74,26 +75,14 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform, clk_freq)
 
                if not self.with_main_ram:
-                       sdram_geom_settings = sdram.GeomSettings(
-                               bank_a=2,
-                               row_a=12,
-                               col_a=8
-                       )
-                       sdram_timing_settings = sdram.TimingSettings(
-                               tRP=self.ns(15),
-                               tRCD=self.ns(15),
-                               tWR=self.ns(14),
-                               tWTR=2,
-                               tREFI=self.ns(64*1000*1000/4096, False),
-                               tRFC=self.ns(66)
-                       )
+                       sdram_module = MT48LC4M16(clk_freq)
                        sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,
                                read_time=32,
                                write_time=16
                        )
                        self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
-                       self.register_sdram_phy(self.sdrphy, sdram_geom_settings, sdram_timing_settings,
+                       self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings,
                                sdram_controller_settings)
 
                self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)