[ARM] FP16 ARM Alternative format variants of AAPCS tests.

testsuite/
2016-09-21  Matthew Wahab  <matthew.wahab@arm.com>

	* gcc.target/arm/fp16-aapcs-3.c: New.
	* gcc.target/arm/fp16-aapcs-4.c: New.
	* gcc.target/arm/aapcs/aapcs/vfp22.c: New.
	* gcc.target/arm/aapcs/aapcs/vfp23.c: New.
	* gcc.target/arm/aapcs/aapcs/vfp24.c: New.
	* gcc.target/arm/aapcs/aapcs/vfp25.c: New.

From-SVN: r240314

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fb04ac3f74739bee4c45d582dd1c93fc7d763a53..73db6902fc825740d84e681b08760f688f0fc52b 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2016-09-21  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gcc.target/arm/fp16-aapcs-3.c: New.
+       * gcc.target/arm/fp16-aapcs-4.c: New.
+       * gcc.target/arm/aapcs/aapcs/vfp22.c: New.
+       * gcc.target/arm/aapcs/aapcs/vfp23.c: New.
+       * gcc.target/arm/aapcs/aapcs/vfp24.c: New.
+       * gcc.target/arm/aapcs/aapcs/vfp25.c: New.
+
 2016-09-21  Bernd Edlinger  <bernd.edlinger@hotmail.de>
 
        PR tree-optimization/77550

diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp22.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp22.c
new file mode 100644 (file)
index 0000000..1944bb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp22.c
@@ -0,0 +1,28 @@
+/* Test AAPCS layout (VFP variant)  */
+
+/* { dg-do run { target arm_eabi } }  */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_fp16_hw }  */
+/* { dg-add-options arm_fp16_alternative }  */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp22.c"
+#include "abitest.h"
+
+#else
+#if defined (__ARM_BIG_ENDIAN)
+ARG (__fp16, 1.0f, S0 + 2)
+#else
+ARG (__fp16, 1.0f, S0)
+#endif
+ARG (float, 2.0f, S1)
+ARG (double, 4.0, D1)
+ARG (float, 2.0f, S4)
+#if defined (__ARM_BIG_ENDIAN)
+ARG (__fp16, 1.0f, S5 + 2)
+#else
+ARG (__fp16, 1.0f, S5)
+#endif
+LAST_ARG (int, 3, R0)
+#endif

diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp23.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp23.c
new file mode 100644 (file)
index 0000000..bcacf9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp23.c
@@ -0,0 +1,30 @@
+/* Test AAPCS layout (VFP variant)  */
+
+/* { dg-do run { target arm_eabi } }  */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_fp16_hw }  */
+/* { dg-add-options arm_fp16_alternative }  */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp23.c"
+
+__complex__ x = 1.0+2.0i;
+
+#include "abitest.h"
+#else
+#if defined (__ARM_BIG_ENDIAN)
+ARG (__fp16, 1.0f, S0 + 2)
+#else
+ARG (__fp16, 1.0f, S0)
+#endif
+ARG (float, 2.0f, S1)
+ARG (__complex__ double, x, D1)
+ARG (float, 3.0f, S6)
+#if defined (__ARM_BIG_ENDIAN)
+ARG (__fp16, 2.0f, S7 + 2)
+#else
+ARG (__fp16, 2.0f, S7)
+#endif
+LAST_ARG (int, 3, R0)
+#endif

diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp24.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp24.c
new file mode 100644 (file)
index 0000000..ef36bb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp24.c
@@ -0,0 +1,21 @@
+/* Test AAPCS layout (VFP variant)  */
+
+/* { dg-do run { target arm_eabi } }  */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_fp16_hw }  */
+/* { dg-add-options arm_fp16_alternative }  */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp24.c"
+
+#define PCSATTR __attribute__((pcs("aapcs")))
+
+#include "abitest.h"
+#else
+ARG (float, 1.0f, R0)
+ARG (double, 2.0, R2)
+ARG (float, 3.0f, STACK)
+ARG (__fp16, 2.0f, STACK+4)
+LAST_ARG (double, 4.0, STACK+8)
+#endif

diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp25.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp25.c
new file mode 100644 (file)
index 0000000..3c796ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp25.c
@@ -0,0 +1,25 @@
+/* Test AAPCS layout (VFP variant)  */
+
+/* { dg-do run { target arm_eabi } }  */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_fp16_hw }  */
+/* { dg-add-options arm_fp16_alternative }  */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp25.c"
+
+#define PCSATTR __attribute__((pcs("aapcs")))
+
+#include "abitest.h"
+#else
+#if defined (__ARM_BIG_ENDIAN)
+ARG (__fp16, 1.0f, R0 + 2)
+#else
+ARG (__fp16, 1.0f, R0)
+#endif
+ARG (double, 2.0, R2)
+ARG (__fp16, 3.0f, STACK)
+ARG (float, 2.0f, STACK+4)
+LAST_ARG (double, 4.0, STACK+8)
+#endif

diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
new file mode 100644 (file)
index 0000000..b7d7e58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile }  */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_fp16_ok } */
+/* { dg-options "-O2" }  */
+/* { dg-add-options arm_fp16_alternative } */
+
+/* Test __fp16 arguments and return value in registers (hard-float).  */
+
+void
+swap (__fp16, __fp16);
+
+__fp16
+F (__fp16 a, __fp16 b, __fp16 c)
+{
+  swap (b, a);
+  return c;
+}
+
+/* { dg-final { scan-assembler-times {vmov\tr[0-9]+, s[0-2]} 2 } }  */
+/* { dg-final { scan-assembler-times {vmov.f32\ts1, s0} 1 } }  */
+/* { dg-final { scan-assembler-times {vmov\ts0, r[0-9]+} 2 } }  */

diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
new file mode 100644 (file)
index 0000000..4c90a56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
@@ -0,0 +1,21 @@
+/* { dg-do compile }  */
+/* { dg-require-effective-target arm_fp16_ok } */
+/* { dg-options "-mfloat-abi=softfp -O2" }  */
+/* { dg-add-options arm_fp16_alternative } */
+/* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
+
+/* Test __fp16 arguments and return value in registers (softfp).  */
+
+void
+swap (__fp16, __fp16);
+
+__fp16
+F (__fp16 a, __fp16 b, __fp16 c)
+{
+  swap (b, a);
+  return c;
+}
+
+/* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } }  */
+/* { dg-final { scan-assembler-times {mov\tr1, r0} 1 } }  */
+/* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } }  */