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* ld-mips-elf/multi-got-1.d, ld-mips-elf/tls-multi-got-1.got,
authorThiemo Seufer <ths@networkno.de>
Wed, 5 Jul 2006 16:01:38 +0000 (16:01 +0000)
committerThiemo Seufer <ths@networkno.de>
Wed, 5 Jul 2006 16:01:38 +0000 (16:01 +0000)
ld-mips-elf/tls-multi-got-1.r: Update multigot testcases.

ld/testsuite/ChangeLog patch | blob | history
ld/testsuite/ld-mips-elf/multi-got-1.d patch | blob | history
ld/testsuite/ld-mips-elf/tls-multi-got-1.got patch | blob | history
ld/testsuite/ld-mips-elf/tls-multi-got-1.r patch | blob | history

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index c47a93bbea93367ce257f94a960c335249def2ac..35071425471ea6f8013818e629c2b958d9f3bef5 100644 (file)
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2006-07-05  Thiemo Seufer  <ths@mips.com>
+
+       * ld-mips-elf/multi-got-1.d, ld-mips-elf/tls-multi-got-1.got,
+       ld-mips-elf/tls-multi-got-1.r: Update multigot testcases.
+
 2006-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 
        * ld-i386/tlsbindesc.dd: Updated to expect xchg %ax,%ax instead
diff --git a/ld/testsuite/ld-mips-elf/multi-got-1.d b/ld/testsuite/ld-mips-elf/multi-got-1.d
index d04f9c47d3981693db3317943d7dce87a7895c7a..1ba5f4bf6109feabc2e47a2f983ebd59b01e5251 100644 (file)
--- a/ld/testsuite/ld-mips-elf/multi-got-1.d
+++ b/ld/testsuite/ld-mips-elf/multi-got-1.d
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+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
 00000000  00000000 R_MIPS_NONE      
 00000000  00000000 R_MIPS_NONE      
 00000000  00000000 R_MIPS_NONE      
diff --git a/ld/testsuite/ld-mips-elf/tls-multi-got-1.got b/ld/testsuite/ld-mips-elf/tls-multi-got-1.got
index fb8cc66597642808e75833bcf8534eb856eb6161..5732701fb701ba5e5f06debd358bcabed9602f2d 100644 (file)
--- a/ld/testsuite/ld-mips-elf/tls-multi-got-1.got
+++ b/ld/testsuite/ld-mips-elf/tls-multi-got-1.got
@@ -12,9 +12,9 @@ OFFSET   TYPE              VALUE
 0013f958 R_MIPS_TLS_DTPREL32  tlsvar_gd
 001495d8 R_MIPS_TLS_TPREL32  tlsvar_ie
 0013f950 R_MIPS_TLS_TPREL32  tlsvar_ie
-00135fcc R_MIPS_REL32      sym_2_8355
+00143f7c R_MIPS_REL32      sym_1_9526
 #...
-00142cec R_MIPS_REL32      sym_1_0945
+00139bd0 R_MIPS_REL32      sym_2_8654
 00000000 R_MIPS_NONE       \*ABS\*
 00000000 R_MIPS_NONE       \*ABS\*
 00000000 R_MIPS_NONE       \*ABS\*
@@ -43,7 +43,7 @@ Contents of section .got:
  122420 00000000 80000000 00000000 00000000  ................
  122430 00000000 00000000 00000000 00000000  ................
  122440 00000000 00000000 00000000 00000000  ................
- 122450 00000000 000e0a4c 000d3594 000d3584  ..........5...5.
+ 122450 00000000 000d8048 000d66a4 000d2054  .......H..f... T
 #...
  13f930 00000000 00000000 00000000 00000000  ................
  13f940 00000000 00000000 00000000 00000000  ................
diff --git a/ld/testsuite/ld-mips-elf/tls-multi-got-1.r b/ld/testsuite/ld-mips-elf/tls-multi-got-1.r
index 6b6be78bee764ca399f5bb78dec30aaa78da9273..c6280c25d868e616733e2584bf3a39121758d5d3 100644 (file)
--- a/ld/testsuite/ld-mips-elf/tls-multi-got-1.r
+++ b/ld/testsuite/ld-mips-elf/tls-multi-got-1.r
@@ -30,13 +30,13 @@ Relocation section '\.rel\.dyn' at offset 0x[0-9a-f]+ contains 20031 entries:
 001495e0  00000627 R_MIPS_TLS_DTPREL 00000000   tlsvar_gd
 0013f954  00000626 R_MIPS_TLS_DTPMOD 00000000   tlsvar_gd
 0013f958  00000627 R_MIPS_TLS_DTPREL 00000000   tlsvar_gd
-001495d8  00000c2f R_MIPS_TLS_TPREL3 00000004   tlsvar_ie
-0013f950  00000c2f R_MIPS_TLS_TPREL3 00000004   tlsvar_ie
-00135fcc  00000e03 R_MIPS_REL32      000e0a4c   sym_2_8355
-001424ac  00000f03 R_MIPS_REL32      000d3594   sym_1_4745
+001495d8  00000b2f R_MIPS_TLS_TPREL3 00000004   tlsvar_ie
+0013f950  00000b2f R_MIPS_TLS_TPREL3 00000004   tlsvar_ie
+00143f7c  00000e03 R_MIPS_REL32      000d8048   sym_1_9526
+00143768  00000f03 R_MIPS_REL32      000d66a4   sym_1_7885
 #...
-001369b0  004e2c03 R_MIPS_REL32      000da930   sym_2_2140
-00142cec  004e2d03 R_MIPS_REL32      000cfa34   sym_1_0945
+0014070c  004e2c03 R_MIPS_REL32      000cf2b4   sym_1_0465
+00139bd0  004e2d03 R_MIPS_REL32      000e0ef8   sym_2_8654
 00000000  00000000 R_MIPS_NONE      
 00000000  00000000 R_MIPS_NONE      
 00000000  00000000 R_MIPS_NONE