radv: use correct register setter for ngg hw addr

this shouldn't matter, but it's good to be correct.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index b1b90c8b0358f1826211a2e9e9018fb75db4497e..47f3f7887d10acb9c0c36eef83a869119ec0230e 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3428,7 +3428,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
 
        radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
        radeon_emit(cs, va >> 8);
-       radeon_emit(cs, va >> 40);
+       radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
        radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
        radeon_emit(cs, shader->config.rsrc1);
        radeon_emit(cs, shader->config.rsrc2);