radeonsi: adjust PIPE_SHADER_CAP_MAX_CONSTS
authorChristian König <deathsimple@vodafone.de>
Fri, 31 Aug 2012 11:59:14 +0000 (13:59 +0200)
committerChristian König <deathsimple@vodafone.de>
Tue, 4 Sep 2012 08:51:26 +0000 (10:51 +0200)
So it matches what we really can do.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
src/gallium/drivers/radeonsi/radeonsi_pipe.c
src/gallium/drivers/radeonsi/radeonsi_pipe.h

index 48b9a3ecb37427f7d1fd5fe58bfc4e186202d44c..f3914d736f6609ae883a40d15ce6f117621cbc8e 100644 (file)
@@ -450,9 +450,9 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
                /* FIXME Isn't this equal to TEMPS? */
                return 1; /* Max native address registers */
        case PIPE_SHADER_CAP_MAX_CONSTS:
-               return R600_MAX_CONST_BUFFER_SIZE;
+               return 64;
        case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
-               return R600_MAX_CONST_BUFFERS;
+               return 1;
        case PIPE_SHADER_CAP_MAX_PREDS:
                return 0; /* FIXME */
        case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
index 099b50916f6c0390c0da364707ad1fd7628bb232..a23f34fe7b9b3585f914da8f17ab220b8fd7a685 100644 (file)
@@ -41,9 +41,6 @@
 #include "r600_resource.h"
 #include "sid.h"
 
-#define R600_MAX_CONST_BUFFERS 1
-#define R600_MAX_CONST_BUFFER_SIZE 4096
-
 #ifdef PIPE_ARCH_BIG_ENDIAN
 #define R600_BIG_ENDIAN 1
 #else