{ 6, 6, 0, OPERAND_REG },
#define Rb (Ra3 + 1)
{ 6, 6, 6, OPERAND_REG },
-#define Rc (Rb + 1)
+#define Rb2 (Rb + 1)
+ { 6, 6, 6, OPERAND_REG|OPERAND_DEST },
+#define Rc (Rb2 + 1)
{ 6, 6, 12, OPERAND_REG },
#define Aa (Rc + 1)
{ 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST },
{ SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */
{ SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */
{ SHORT_RA, 2, { Ra, Ab, IMM6U2 } }, /* Ra,Ab,imm6u */
- { SHORT_MODINC, 1, { Ra, IMM5 } }, /* Ra,imm5 (modinc) */
- { SHORT_MODDEC, 3, { Ra, IMM5 } }, /* Ra,imm5 (moddec) */
+ { SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */
+ { SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */
{ SHORT_C1, 0, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */
{ SHORT_C2, 0, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */
{ SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */