isl: Add 2D ASTC format layouts and enums

Also, make changes needed for successful compilation and registration
as a texture compression mode.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 2a29b28da597600d3211266b941c87c566236a7e..71f297174f5b6e6f7d0a31fa6d5862fa72426268 100644 (file)
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -307,6 +307,34 @@ enum isl_format {
    ISL_FORMAT_R8G8B8_UINT =                                    456,
    ISL_FORMAT_R8G8B8_SINT =                                    457,
    ISL_FORMAT_RAW =                                            511,
+   ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB =                         512,
+   ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB =                         520,
+   ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB =                         521,
+   ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB =                         529,
+   ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB =                         530,
+   ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB =                         545,
+   ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB =                         546,
+   ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB =                         548,
+   ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB =                        561,
+   ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB =                        562,
+   ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB =                        564,
+   ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB =                       566,
+   ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB =                       574,
+   ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB =                       575,
+   ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 =                          576,
+   ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 =                          584,
+   ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 =                          585,
+   ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 =                          593,
+   ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 =                          594,
+   ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 =                          609,
+   ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 =                          610,
+   ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 =                          612,
+   ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 =                         625,
+   ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 =                         626,
+   ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 =                         628,
+   ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 =                        630,
+   ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 =                        638,
+   ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 =                        639,
 
    /* Hardware doesn't understand this out-of-band value */
    ISL_FORMAT_UNSUPPORTED =                             UINT16_MAX,
@@ -354,6 +382,7 @@ enum isl_txc {
    ISL_TXC_BPTC,
    ISL_TXC_ETC1,
    ISL_TXC_ETC2,
+   ISL_TXC_ASTC,
 };
 
 /**
@@ -879,6 +908,7 @@ isl_format_has_bc_compression(enum isl_format fmt)
    case ISL_TXC_BPTC:
    case ISL_TXC_ETC1:
    case ISL_TXC_ETC2:
+   case ISL_TXC_ASTC:
       return false;
    }
 

diff --git a/src/intel/isl/isl_format_layout.csv b/src/intel/isl/isl_format_layout.csv
index af2786ae63073edce84f1c34544060a56181c2cc..d66a172891ce9b320b78a402c8956c4b651fcccc 100644 (file)
--- a/src/intel/isl/isl_format_layout.csv
+++ b/src/intel/isl/isl_format_layout.csv
@@ -285,3 +285,31 @@ ETC2_EAC_SRGB8_A8           , 128,  4,  4,  1,  un8,  un8,  un8,  un8,     ,
 R8G8B8_UINT                 ,  24,  1,  1,  1,  ui8,  ui8,  ui8,     ,     ,     ,    , linear,
 R8G8B8_SINT                 ,  24,  1,  1,  1,  si8,  si8,  si8,     ,     ,     ,    , linear,
 RAW                         ,   0,  0,  0,  0,     ,     ,     ,     ,     ,     ,    ,       ,
+ASTC_LDR_2D_4X4_U8SRGB      , 128,  4,  4,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_5X4_U8SRGB      , 128,  5,  4,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_5X5_U8SRGB      , 128,  5,  5,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_6X5_U8SRGB      , 128,  6,  5,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_6X6_U8SRGB      , 128,  6,  6,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_8X5_U8SRGB      , 128,  8,  5,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_8X6_U8SRGB      , 128,  8,  6,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_8X8_U8SRGB      , 128,  8,  8,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_10X5_U8SRGB     , 128, 10,  5,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_10X6_U8SRGB     , 128, 10,  6,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_10X8_U8SRGB     , 128, 10,  8,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_10X10_U8SRGB    , 128, 10, 10,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_12X10_U8SRGB    , 128, 12, 10,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_12X12_U8SRGB    , 128, 12, 12,  1,  un8,  un8,  un8,  un8,     ,     ,    ,   srgb,  astc
+ASTC_LDR_2D_4X4_FLT16       , 128,  4,  4,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_5X4_FLT16       , 128,  5,  4,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_5X5_FLT16       , 128,  5,  5,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_6X5_FLT16       , 128,  6,  5,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_6X6_FLT16       , 128,  6,  6,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_8X5_FLT16       , 128,  8,  5,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_8X6_FLT16       , 128,  8,  6,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_8X8_FLT16       , 128,  8,  8,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_10X5_FLT16      , 128, 10,  5,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_10X6_FLT16      , 128, 10,  6,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_10X8_FLT16      , 128, 10,  8,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_10X10_FLT16     , 128, 10, 10,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_12X10_FLT16     , 128, 12, 10,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc
+ASTC_LDR_2D_12X12_FLT16     , 128, 12, 12,  1, sf16, sf16, sf16, sf16,     ,     ,    , linear,  astc

diff --git a/src/intel/isl/isl_format_layout_gen.bash b/src/intel/isl/isl_format_layout_gen.bash
index db88382737655ed65381b4458532052c180a7be8..31830815453e9adc48acdf7b3c954799590908ec 100755 (executable)
--- a/src/intel/isl/isl_format_layout_gen.bash
+++ b/src/intel/isl/isl_format_layout_gen.bash
@@ -85,7 +85,7 @@ s/\<(linear|srgb|yuv)\>/ISL_COLORSPACE_\1/
 s/\<alpha\>//
 
 # Translate texture compression
-s/\<(dxt|fxt|rgtc|bptc|etc)([0-9]*)\>/ISL_TXC_\1\2/
+s/\<(dxt|fxt|rgtc|bptc|etc|astc)([0-9]*)\>/ISL_TXC_\1\2/
 ' |
 tr 'a-z' 'A-Z' | # Convert to uppersace
 while IFS=, read -r format bpb bw bh bd \