sdram/module: add P3R1GE4JGF DDR2 (Atlys) and MT41J128M16 DDR3 (Opsis, Novena) modules.

diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
index 049c595cfb3737646eb390d1f4fefa9745b6c1df..ae265066b24eb6d2a3b2185a3809a93fa57b7b10 100644 (file)
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@@ -165,6 +165,26 @@ class MT47H128M8(SDRAMModule):
             self.timing_settings)
 
 
+class P3R1GE4JGF(SDRAMModule):
+    geom_settings = {
+        "nbanks": 8,
+        "nrows": 8192,
+        "ncols": 1024
+    }
+    timing_settings = {
+        "tRP":   12.5,
+        "tRCD":  12.5,
+        "tWR":   15,
+        "tWTR":  3,
+        "tREFI": 7800,
+        "tRFC":  127.5,
+    }
+
+    def __init__(self, clk_freq):
+        SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
+            self.timing_settings)
+
+
 # DDR3
 class MT8JTF12864(SDRAMModule):
     geom_settings = {
@@ -183,3 +203,23 @@ class MT8JTF12864(SDRAMModule):
     def __init__(self, clk_freq):
         SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
             self.timing_settings)
+
+
+class MT41J128M16(SDRAMModule):
+    geom_settings = {
+        "nbanks": 8,
+        "nrows":  16384,
+        "ncols":  1024,
+    }
+    timing_settings = {
+        "tRP":   15,
+        "tRCD":  15,
+        "tWR":   15,
+        "tWTR":  3,
+        "tREFI": 64*1000*1000/16384,
+        "tRFC":  260,
+    }
+
+    def __init__(self, clk_freq):
+        SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
+            self.timing_settings)