x86: Fix the flag handling code in FABS and FCHS

This changeset fixes two problems in the FABS and FCHS
implementation. First, the ISA parser expects the assignment in
flag_code to be a pure assignment and not an and-assignment, which
leads to the isa_parser omitting the misc reg update. Second, the FCHS
and FABS macro-ops don't set the SetStatus flag, which means that the
default micro-op version, which doesn't update FSW, is executed.

diff --git a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
index 779f1b5b25e65423c1594d699970045cc0864634..207b8a0b093e7701ff63925b112fc61b02a514d5 100644 (file)
--- a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
+++ b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
@@ -38,10 +38,10 @@
 microcode = '''
 
 def macroop FABS {
-    absfp st(0), st(0)
+    absfp st(0), st(0), SetStatus=True
 };
 
 def macroop FCHS {
-    chsfp st(0), st(0)
+    chsfp st(0), st(0), SetStatus=True
 };
 '''

diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index abb6abb72747e24857bee8d8b005bd6a5278be7d..e6372ba6be891e75432c89316ba787801b3fc794 100644 (file)
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -365,9 +365,9 @@ let {{
 
     class absfp(FpUnaryOp):
         code = 'FpDestReg = fabs(FpSrcReg1);'
-        flag_code = 'FSW &= (~CC1Bit);'
+        flag_code = 'FSW = FSW & (~CC1Bit);'
 
     class chsfp(FpUnaryOp):
         code = 'FpDestReg = (-1) * (FpSrcReg1);'
-        flag_code = 'FSW &= (~CC1Bit);'
+        flag_code = 'FSW = FSW & (~CC1Bit);'
 }};