ruby: allow restoring from checkpoint when using DRAMCtrl

Restoring from a checkpoint with ruby + the DRAMCtrl memory model was not
working, because ruby and DRAMCtrl disagreed on the current tick during warmup.
Since there is no reason to do timing requests during warmup, use functional
requests instead.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index a1d6ab83e0f5a90c945e053e432039e52225524c..4290c63fa314b93ccbea49edd740640fb397b649 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -40,7 +40,8 @@ AbstractController::AbstractController(const Params *p)
       m_transitions_per_cycle(p->transitions_per_cycle),
       m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
       memoryPort(csprintf("%s.memory", name()), this, ""),
-      m_responseFromMemory_ptr(new MessageBuffer())
+      m_responseFromMemory_ptr(new MessageBuffer()),
+      m_rubySystem(p->ruby_system)
 {
     // Set the sender pointer of the response message buffer from the
     // memory controller.
@@ -217,6 +218,13 @@ AbstractController::queueMemoryRead(const MachineID &id, Address addr,
     SenderState *s = new SenderState(id);
     pkt->pushSenderState(s);
 
+    // Use functional rather than timing accesses during warmup
+    if (m_rubySystem->m_warmup_enabled) {
+        memoryPort.sendFunctional(pkt);
+        recvTimingResp(pkt);
+        return;
+    }
+
     memoryPort.schedTimingReq(pkt, clockEdge(latency));
 }
 
@@ -237,6 +245,13 @@ AbstractController::queueMemoryWrite(const MachineID &id, Address addr,
     SenderState *s = new SenderState(id);
     pkt->pushSenderState(s);
 
+    // Use functional rather than timing accesses during warmup
+    if (m_rubySystem->m_warmup_enabled) {
+        memoryPort.sendFunctional(pkt);
+        recvTimingResp(pkt);
+        return;
+    }
+
     // Create a block and copy data from the block.
     memoryPort.schedTimingReq(pkt, clockEdge(latency));
 }

diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index f8970fb590d1edbaf284713d187cc7ce2e34fb5c..01859397a9537ecd435d25903045184cd5f00d7a 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -205,6 +205,9 @@ class AbstractController : public MemObject, public Consumer
     // memory controller.
     MessageBuffer *m_responseFromMemory_ptr;
 
+    // Needed so we know if we are warming up
+    RubySystem *m_rubySystem;
+
     // State that is stored in packets sent to the memory controller.
     struct SenderState : public Packet::SenderState
     {