Power: Correct little-endian e500v2 GPR frame offsets

This change corrects GPR frame offset calculation for the e500v2
processor.  On this target, featuring the SPE APU, GPRs are 64-bit and
are held in stack frames whole with the use of `evstdd' and `evldd'
instructions.  Their integer 32-bit part occupies the low-order word and
therefore its offset varies between the two endiannesses possible.

	* rs6000-tdep.c (rs6000_frame_cache): Correct little-endian GPR
	offset into SPE pseudo registers.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 1c689378c9aaea04488fc5612e5fe708f3bfd35c..4f486e9e74ad06cca6b0ad949db2306fea1a5df3 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2014-03-18  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * rs6000-tdep.c (rs6000_frame_cache): Correct little-endian GPR
+       offset into SPE pseudo registers.
+
 2014-03-18  Pedro Alves  <palves@redhat.com>
 
        PR gdb/13860

diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index bec06c7db899e2ed570cae9c8a143562cea9cdbc..dbe3aa2450663e8d12ae05e364217d783ebe943d 100644 (file)
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -3257,12 +3257,14 @@ rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
        {
          int i;
          CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
+         CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0);
+
          for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
            {
              cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
-              cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
+             cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off;
              ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
-            }
+           }
        }
     }