m5: Added PROTOCOL default for regress fix

diff --git a/build_opts/ALPHA_FS b/build_opts/ALPHA_FS
index e69cff04b90e8f6631d97a2a2c3a49a8b00cfa81..3908039d1a6a8adf41a8c50b5535fca341a81cc4 100644 (file)
--- a/build_opts/ALPHA_FS
+++ b/build_opts/ALPHA_FS
@@ -1,3 +1,4 @@
 TARGET_ISA = 'alpha'
 FULL_SYSTEM = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
+PROTOCOL = 'MI_example'

diff --git a/build_opts/ALPHA_SE b/build_opts/ALPHA_SE
index dcd8559fc1f3f94d263610184fe4da8d0f5f475d..b21fec4cbced5d324100d9672aba36f9889313b8 100644 (file)
--- a/build_opts/ALPHA_SE
+++ b/build_opts/ALPHA_SE
@@ -1,3 +1,4 @@
 FULL_SYSTEM = 0
 SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MI_example'

diff --git a/build_opts/ARM_FS b/build_opts/ARM_FS
index 508bad76ebdb5b8e2a79d77420ab1e07686c0311..9d518142d43f801befc8d6d5ace6c9db9d0a1b51 100644 (file)
--- a/build_opts/ARM_FS
+++ b/build_opts/ARM_FS
@@ -1,3 +1,4 @@
 TARGET_ISA = 'arm'
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
 FULL_SYSTEM = 1
+PROTOCOL = 'MI_example'

diff --git a/build_opts/ARM_SE b/build_opts/ARM_SE
index 93770ac80f3e72093832f2d9254c421f15f98e7c..5019edb0a3d8134f3e9df443bb291ba844f09ac8 100644 (file)
--- a/build_opts/ARM_SE
+++ b/build_opts/ARM_SE
@@ -1,3 +1,4 @@
 TARGET_ISA = 'arm'
 FULL_SYSTEM = 0
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
+PROTOCOL = 'MI_example'

diff --git a/build_opts/MIPS_FS b/build_opts/MIPS_FS
index 81d7fd7a195225c6fae9f57b86d4b7d6f7356219..3e08a2fcd33d66e48b82b7527ca9c0df773c8284 100644 (file)
--- a/build_opts/MIPS_FS
+++ b/build_opts/MIPS_FS
@@ -1,2 +1,3 @@
 TARGET_ISA = 'mips'
 FULL_SYSTEM = 1
+PROTOCOL = 'MI_example'

diff --git a/build_opts/MIPS_SE b/build_opts/MIPS_SE
index d3e449f42356453def0513dcec1ad56393a02bbe..0855578983f1b6396c767244ae372f64559cb141 100644 (file)
--- a/build_opts/MIPS_SE
+++ b/build_opts/MIPS_SE
@@ -1,3 +1,4 @@
 TARGET_ISA = 'mips'
 FULL_SYSTEM = 0
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
\ No newline at end of file
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MI_example'

diff --git a/build_opts/POWER_SE b/build_opts/POWER_SE
index d76ca7180de4ef2914c3185b248c7fa9657f6563..13e175ebcdb55cefd4b1cba83cca92087195cc81 100644 (file)
--- a/build_opts/POWER_SE
+++ b/build_opts/POWER_SE
@@ -1,3 +1,4 @@
 TARGET_ISA = 'power'
 FULL_SYSTEM = 0
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
+PROTOCOL = 'MI_example'

diff --git a/build_opts/SPARC_FS b/build_opts/SPARC_FS
index 7c8bda0ceba306e9cab3ea67262a9462f9e89ecb..f1dd81481f3956b0bf8ad42d0d8e6c99105ef1c1 100644 (file)
--- a/build_opts/SPARC_FS
+++ b/build_opts/SPARC_FS
@@ -1,3 +1,4 @@
 TARGET_ISA = 'sparc'
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
 FULL_SYSTEM = 1
+PROTOCOL = 'MI_example'

diff --git a/build_opts/SPARC_SE b/build_opts/SPARC_SE
index b288d390850a48696958cc0372b381dd2ca901d4..802176bd0470c096d2021ac293a45b8684d4c15b 100644 (file)
--- a/build_opts/SPARC_SE
+++ b/build_opts/SPARC_SE
@@ -1,3 +1,4 @@
 TARGET_ISA = 'sparc'
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
 FULL_SYSTEM = 0
+PROTOCOL = 'MI_example'

diff --git a/build_opts/X86_FS b/build_opts/X86_FS
index 7cc6847f299e4f80009d042a8726f1efb2c73abe..72cba7443a8a879a50c7cc69258ef811fad38693 100644 (file)
--- a/build_opts/X86_FS
+++ b/build_opts/X86_FS
@@ -1,3 +1,4 @@
 TARGET_ISA = 'x86'
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
 FULL_SYSTEM = 1
+PROTOCOL = 'MI_example'

diff --git a/build_opts/X86_SE b/build_opts/X86_SE
index 5913cde1e41089d2d8f5edd9d151d6ac859e9f82..3e372726ddf8e8273c2be1aeb69992dcddaf9b37 100644 (file)
--- a/build_opts/X86_SE
+++ b/build_opts/X86_SE
@@ -1,3 +1,4 @@
 TARGET_ISA = 'x86'
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
 FULL_SYSTEM = 0
+PROTOCOL = 'MI_example'