Fixed sign handling in ternary operator

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 791ee986761aeea34eb7ee4b9543a50e93e0171f..a9574254dac33640301cfa0056587cbdf7d4706e 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1007,8 +1007,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
                        int width = std::max(val1.width, val2.width);
                        is_signed = children[1]->is_signed && children[2]->is_signed;
-                       val1.extend(width);
-                       val2.extend(width);
+                       val1.extend(width, is_signed);
+                       val2.extend(width, is_signed);
 
                        return mux2rtlil(this, cond, val1, val2);
                }

diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v
index eb0e15d029eaaecf370ace2b426735a0f2d22ab8..c97a2be50b71c74b179fb32a969db4c16123d564 100644 (file)
--- a/tests/simple/vloghammer.v
+++ b/tests/simple/vloghammer.v
@@ -57,3 +57,11 @@ module test08(a, b, y);
   assign y = a == ($signed(b) >>> 1);
 endmodule
 
+module test09(a, b, c, y);
+  input a;
+  input signed [1:0] b;
+  input signed [2:0] c;
+  output [3:0] y;
+  assign y = a ? b : c;
+endmodule
+