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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 015fcc2cdcb30184ac6b7185d830d2d6d7e5927c..a70389608ddc6bf37a17e8cac5a712ad5c239b7a 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -34,9 +34,10 @@ this task, and what, in Computer Science, actually needs solving?
 
 First hints are that whilst memory bitcells have not increased in speed
 since the 90s (around 150 mhz), increasing the bank width, striping, and
-datapath widths and speeds to the same has allowed
-significant apparent speed increases: 3200 mhz DDR4 and even faster DDR5,
-and other advanced Memory interfaces such as HBM, Gen-Z, and OpenCAPI,
+datapath widths and speeds to the same has, with significant relative
+latency penalties, allowed
+apparent speed increases: 3200 mhz DDR4 and even faster DDR5,
+and other advanced Memory interfaces such as HBM, Gen-Z, and OpenCAPI's OMI,
 all make an effort (all simply increasing the parallel deployment of
 the underlying 150 mhz bitcells), but these efforts are dwarfed by the
 two nearly three orders of magnitude increase in CPU horsepower