#
# Authors: Gabe Black
-from m5.SimObject import SimObject
+from m5.SimObject import SimObject, cxxMethod
# This class represents the systemc kernel. There should be exactly one in the
# simulation. It receives gem5 SimObject lifecycle callbacks (init, regStats,
cxx_class = 'sc_core::sc_module'
cxx_header = 'systemc/ext/core/sc_module.hh'
+ @cxxMethod(return_value_policy="reference", cxx_name="gem5_getPort")
+ def getPort(self, if_name, iex):
+ return None
+
try:
import _m5
except:
#include <string>
#include <vector>
+#include "base/logging.hh"
#include "systemc/core/event.hh"
#include "systemc/core/kernel.hh"
#include "systemc/core/module.hh"
const sc_bind_proxy SC_BIND_PROXY_NIL;
+::Port &
+sc_module::gem5_getPort(const std::string &if_name, int idx)
+{
+ fatal("%s does not have any port named %s\n", name(), if_name);
+}
+
sc_module::~sc_module() { delete _gem5_module; }
void
#ifndef __SYSTEMC_CORE_EXT_SC_MODULE_HH__
#define __SYSTEMC_CORE_EXT_SC_MODULE_HH__
+#include <string>
#include <vector>
#include "sc_object.hh"
} // namespace sc_gem5
+// Gem5 prototype
+class Port;
+
namespace sc_core
{
class sc_module : public sc_object
{
+ public:
+ // Gem5 specific extensions
+ virtual ::Port &gem5_getPort(const std::string &if_name, int idx=-1);
+
public:
friend class ::sc_gem5::Kernel;
friend class ::sc_gem5::Module;