Minor regression fixes.

src/python/m5/objects/BaseCPU.py:
    bug fix
tests/SConscript:
    fix up diff ignore strings to reflect changes
    in m5 output

--HG--
extra : convert_revision : b8e4acee34599ddd431b69fc9d40b6f6e440d128

diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 7906156a25d56e92716e40d6dd55942ad3ad45e6..01458aeb48e7607a4c7440a3bee50b301176deb5 100644 (file)
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -49,5 +49,5 @@ class BaseCPU(SimObject):
         self.toL2Bus = Bus()
         self.connectMemPorts(self.toL2Bus)
         self.l2cache = l2c
-        self.l2cache.cpu_side = toL2Bus.port
+        self.l2cache.cpu_side = self.toL2Bus.port
         self._mem_ports = ['l2cache.mem_side']

diff --git a/tests/SConscript b/tests/SConscript
index 8720939de36b7003e4ae1a1ffbb81a2988199d5f..d5968d3e3a8a90b8b3e26a1a0e43af5b454763f4 100644 (file)
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -61,8 +61,9 @@ def check_test(target, source, env):
     # Exclude m5stats.txt since we will use diff-out on that.
     Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' +
                       '-I "^command line:" ' +         # for stdout file
-                      '-I "^M5 compiled on" ' +                # for stderr file
-                      '-I "^M5 simulation started" ' + # for stderr file
+                      '-I "^M5 compiled " ' +          # for stderr file
+                      '-I "^M5 started " ' +           # for stderr file
+                      '-I "^M5 executing on " ' +      # for stderr file
                       '-I "^Simulation complete at" ' +        # for stderr file
                       '-I "^Listening for" ' +         # for stderr file
                       '--exclude=m5stats.txt --exclude=SCCS ' +