+2011-07-24 Chao-ying Fu <fu@mips.com>
+ Ilie Garbacea <ilie@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+ Joseph Myers <joseph@codesourcery.com>
+ Catherine Moore <clm@codesourcery.com>
+ Richard Sandiford <rdsandiford@googlemail.com>
+
+ * archures.c (bfd_mach_mips_micromips): New macro.
+ * cpu-mips.c (I_micromips): New enum value.
+ (arch_info_struct): Add bfd_mach_mips_micromips.
+ * elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
+ prototype.
+ (_bfd_mips_elf_relax_section): Likewise.
+ (_bfd_mips16_elf_reloc_unshuffle): Rename to...
+ (_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
+ ASE.
+ (_bfd_mips16_elf_reloc_shuffle): Rename to...
+ (_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
+ (gprel16_reloc_p): Handle microMIPS ASE.
+ (literal_reloc_p): New function.
+ * elf32-mips.c (elf_micromips_howto_table_rel): New variable.
+ (_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
+ (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
+ and _bfd_mips_elf_reloc_shuffle changes.
+ (mips_elf_gprel32_reloc): Update comment.
+ (micromips_reloc_map): New variable.
+ (bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
+ (mips_elf32_rtype_to_howto): Likewise.
+ (mips_info_to_howto_rel): Likewise.
+ (bfd_elf32_bfd_is_target_special_symbol): Define.
+ (bfd_elf32_bfd_relax_section): Likewise.
+ * elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
+ (micromips_elf64_howto_table_rela): Likewise.
+ (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
+ and _bfd_mips_elf_reloc_shuffle changes.
+ (micromips_reloc_map): Likewise.
+ (bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
+ (bfd_elf64_bfd_reloc_name_lookup): Likewise.
+ (mips_elf64_rtype_to_howto): Likewise.
+ (bfd_elf64_bfd_is_target_special_symbol): Define.
+ * elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
+ (elf_micromips_howto_table_rela): Likewise.
+ (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
+ and _bfd_mips_elf_reloc_shuffle changes.
+ (micromips_reloc_map): Likewise.
+ (bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
+ (bfd_elf32_bfd_reloc_name_lookup): Likewise.
+ (mips_elf_n32_rtype_to_howto): Likewise.
+ (bfd_elf32_bfd_is_target_special_symbol): Define.
+ * elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
+ (LA25_LUI_MICROMIPS_2): Likewise.
+ (LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
+ (LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
+ (TLS_RELOC_P): Handle microMIPS ASE.
+ (mips_elf_create_stub_symbol): Adjust value of stub symbol if
+ target is a microMIPS function.
+ (micromips_reloc_p): New function.
+ (micromips_reloc_shuffle_p): Likewise.
+ (got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
+ (got_disp_reloc_p, got_page_reloc_p): New functions.
+ (got_ofst_reloc_p): Likewise.
+ (got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
+ (call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
+ (hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
+ (micromips_branch_reloc_p): New function.
+ (tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
+ (tls_gottprel_reloc_p): Likewise.
+ (_bfd_mips16_elf_reloc_unshuffle): Rename to...
+ (_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
+ ASE.
+ (_bfd_mips16_elf_reloc_shuffle): Rename to...
+ (_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
+ (_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
+ (mips_tls_got_index, mips_elf_got_page): Likewise.
+ (mips_elf_create_local_got_entry): Likewise.
+ (mips_elf_relocation_needs_la25_stub): Likewise.
+ (mips_elf_calculate_relocation): Likewise.
+ (mips_elf_perform_relocation): Likewise.
+ (_bfd_mips_elf_symbol_processing): Likewise.
+ (_bfd_mips_elf_add_symbol_hook): Likewise.
+ (_bfd_mips_elf_link_output_symbol_hook): Likewise.
+ (mips_elf_add_lo16_rel_addend): Likewise.
+ (_bfd_mips_elf_check_relocs): Likewise.
+ (mips_elf_adjust_addend): Likewise.
+ (_bfd_mips_elf_relocate_section): Likewise.
+ (mips_elf_create_la25_stub): Likewise.
+ (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
+ (_bfd_mips_elf_gc_sweep_hook): Likewise.
+ (_bfd_mips_elf_is_target_special_symbol): New function.
+ (mips_elf_relax_delete_bytes): Likewise.
+ (opcode_descriptor): New structure.
+ (RA): New macro.
+ (OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
+ (b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
+ (beq_insn_32): Likewise.
+ (b_insn_16, bz_insn_16): New variables.
+ (BZC32_REG_FIELD): New macro.
+ (bz_rs_insns_32, bz_rt_insns_32): New variables.
+ (bzc_insns_32, bz_insns_16):Likewise.
+ (BZ16_REG, BZ16_REG_FIELD): New macros.
+ (jal_insn_32_bd16, jal_insn_32_bd32): New variables.
+ (jal_x_insn_32_bd32): Likewise.
+ (j_insn_32, jalr_insn_32): Likewise.
+ (ds_insns_32_bd16, ds_insns_32_bd32): Likewise.
+ (jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
+ (JR16_REG): New macro.
+ (ds_insns_16_bd16): New variable.
+ (lui_insn): Likewise.
+ (addiu_insn, addiupc_insn): Likewise.
+ (ADDIUPC_REG_FIELD): New macro.
+ (MOVE32_RD, MOVE32_RS): Likewise.
+ (MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
+ (move_insns_32, move_insns_16): New variables.
+ (nop_insn_32, nop_insn_16): Likewise.
+ (MATCH): New macro.
+ (find_match): New function.
+ (check_br16_dslot, check_br32_dslot): Likewise.
+ (check_br16, check_br32): Likewise.
+ (IS_BITSIZE): New macro.
+ (check_4byte_branch): New function.
+ (_bfd_mips_elf_relax_section): Likewise.
+ (_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
+ and microMIPS modules together.
+ (_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE.
+ * reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
+ (BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
+ (BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
+ (BFD_RELOC_MICROMIPS_GPREL16): Likewise.
+ (BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
+ (BFD_RELOC_MICROMIPS_HI16_S): Likewise.
+ (BFD_RELOC_MICROMIPS_LO16): Likewise.
+ (BFD_RELOC_MICROMIPS_LITERAL): Likewise.
+ (BFD_RELOC_MICROMIPS_GOT16): Likewise.
+ (BFD_RELOC_MICROMIPS_CALL16): Likewise.
+ (BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
+ (BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
+ (BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
+ (BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
+ (BFD_RELOC_MICROMIPS_SUB): Likewise.
+ (BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
+ (BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
+ (BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
+ (BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
+ (BFD_RELOC_MICROMIPS_HIGHER): Likewise.
+ (BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
+ (BFD_RELOC_MICROMIPS_JALR): Likewise.
+ (BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
+ (BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
+ (BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
+ (BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
+ (BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
+ (BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
+ (BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
+ * bfd-in2.h: Regenerate.
+ * libbfd.h: Regenerate.
+
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am (ALL_MACHINES): Add cpu-k1om.lo.
.#define bfd_mach_mipsisa32r2 33
.#define bfd_mach_mipsisa64 64
.#define bfd_mach_mipsisa64r2 65
+.#define bfd_mach_mips_micromips 96
. bfd_arch_i386, {* Intel 386 *}
.#define bfd_mach_i386_i386 1
.#define bfd_mach_i386_i8086 2
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa64 64
#define bfd_mach_mipsisa64r2 65
+#define bfd_mach_mips_micromips 96
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 1
#define bfd_mach_i386_i8086 2
BFD_RELOC_ALPHA_TPREL_LO16,
BFD_RELOC_ALPHA_TPREL16,
-/* Bits 27..2 of the relocation address shifted right 2 bits;
-simple reloc otherwise. */
+/* The MIPS jump instruction. */
BFD_RELOC_MIPS_JMP,
+ BFD_RELOC_MICROMIPS_JMP,
/* The MIPS16 jump instruction. */
BFD_RELOC_MIPS16_JMP,
/* Relocation against a MIPS literal section. */
BFD_RELOC_MIPS_LITERAL,
+ BFD_RELOC_MICROMIPS_LITERAL,
+
+/* microMIPS PC-relative relocations. */
+ BFD_RELOC_MICROMIPS_7_PCREL_S1,
+ BFD_RELOC_MICROMIPS_10_PCREL_S1,
+ BFD_RELOC_MICROMIPS_16_PCREL_S1,
+
+/* microMIPS versions of generic BFD relocs. */
+ BFD_RELOC_MICROMIPS_GPREL16,
+ BFD_RELOC_MICROMIPS_HI16,
+ BFD_RELOC_MICROMIPS_HI16_S,
+ BFD_RELOC_MICROMIPS_LO16,
/* MIPS ELF relocations. */
BFD_RELOC_MIPS_GOT16,
+ BFD_RELOC_MICROMIPS_GOT16,
BFD_RELOC_MIPS_CALL16,
+ BFD_RELOC_MICROMIPS_CALL16,
BFD_RELOC_MIPS_GOT_HI16,
+ BFD_RELOC_MICROMIPS_GOT_HI16,
BFD_RELOC_MIPS_GOT_LO16,
+ BFD_RELOC_MICROMIPS_GOT_LO16,
BFD_RELOC_MIPS_CALL_HI16,
+ BFD_RELOC_MICROMIPS_CALL_HI16,
BFD_RELOC_MIPS_CALL_LO16,
+ BFD_RELOC_MICROMIPS_CALL_LO16,
BFD_RELOC_MIPS_SUB,
+ BFD_RELOC_MICROMIPS_SUB,
BFD_RELOC_MIPS_GOT_PAGE,
+ BFD_RELOC_MICROMIPS_GOT_PAGE,
BFD_RELOC_MIPS_GOT_OFST,
+ BFD_RELOC_MICROMIPS_GOT_OFST,
BFD_RELOC_MIPS_GOT_DISP,
+ BFD_RELOC_MICROMIPS_GOT_DISP,
BFD_RELOC_MIPS_SHIFT5,
BFD_RELOC_MIPS_SHIFT6,
BFD_RELOC_MIPS_INSERT_A,
BFD_RELOC_MIPS_INSERT_B,
BFD_RELOC_MIPS_DELETE,
BFD_RELOC_MIPS_HIGHEST,
+ BFD_RELOC_MICROMIPS_HIGHEST,
BFD_RELOC_MIPS_HIGHER,
+ BFD_RELOC_MICROMIPS_HIGHER,
BFD_RELOC_MIPS_SCN_DISP,
+ BFD_RELOC_MICROMIPS_SCN_DISP,
BFD_RELOC_MIPS_REL16,
BFD_RELOC_MIPS_RELGOT,
BFD_RELOC_MIPS_JALR,
+ BFD_RELOC_MICROMIPS_JALR,
BFD_RELOC_MIPS_TLS_DTPMOD32,
BFD_RELOC_MIPS_TLS_DTPREL32,
BFD_RELOC_MIPS_TLS_DTPMOD64,
BFD_RELOC_MIPS_TLS_DTPREL64,
BFD_RELOC_MIPS_TLS_GD,
+ BFD_RELOC_MICROMIPS_TLS_GD,
BFD_RELOC_MIPS_TLS_LDM,
+ BFD_RELOC_MICROMIPS_TLS_LDM,
BFD_RELOC_MIPS_TLS_DTPREL_HI16,
+ BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16,
BFD_RELOC_MIPS_TLS_DTPREL_LO16,
+ BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16,
BFD_RELOC_MIPS_TLS_GOTTPREL,
+ BFD_RELOC_MICROMIPS_TLS_GOTTPREL,
BFD_RELOC_MIPS_TLS_TPREL32,
BFD_RELOC_MIPS_TLS_TPREL64,
BFD_RELOC_MIPS_TLS_TPREL_HI16,
+ BFD_RELOC_MICROMIPS_TLS_TPREL_HI16,
BFD_RELOC_MIPS_TLS_TPREL_LO16,
+ BFD_RELOC_MICROMIPS_TLS_TPREL_LO16,
/* MIPS ELF relocations (VxWorks and PLT extensions). */
I_loongson_2f,
I_loongson_3a,
I_mipsocteon,
- I_xlr
+ I_xlr,
+ I_micromips
};
#define NN(index) (&arch_info_struct[(index) + 1])
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
- N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, 0)
+ N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
+ N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
};
/* The default architecture is mips:3000, but with a machine number of
FALSE), /* pcrel_offset */
};
+static reloc_howto_type elf_micromips_howto_table_rel[] =
+{
+ EMPTY_HOWTO (130),
+ EMPTY_HOWTO (131),
+ EMPTY_HOWTO (132),
+
+ /* 26 bit jump address. */
+ HOWTO (R_MICROMIPS_26_S1, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 26, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ /* This needs complex overflow
+ detection, because the upper four
+ bits must match the PC. */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_26_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x3ffffff, /* src_mask */
+ 0x3ffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of symbol value. */
+ HOWTO (R_MICROMIPS_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_hi16_reloc, /* special_function */
+ "R_MICROMIPS_HI16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of symbol value. */
+ HOWTO (R_MICROMIPS_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_lo16_reloc, /* special_function */
+ "R_MICROMIPS_LO16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* GP relative reference. */
+ HOWTO (R_MICROMIPS_GPREL16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_GPREL16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reference to literal section. */
+ HOWTO (R_MICROMIPS_LITERAL, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_LITERAL", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reference to global offset table. */
+ HOWTO (R_MICROMIPS_GOT16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_got16_reloc, /* special_function */
+ "R_MICROMIPS_GOT16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* This is for microMIPS branches. */
+ HOWTO (R_MICROMIPS_PC7_S1, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 7, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC7_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000007f, /* src_mask */
+ 0x0000007f, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC10_S1, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 10, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC10_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x000003ff, /* src_mask */
+ 0x000003ff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC16_S1, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC16_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 16 bit call through global offset table. */
+ HOWTO (R_MICROMIPS_CALL16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (143),
+ EMPTY_HOWTO (144),
+
+ /* Displacement in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_DISP, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_DISP",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Displacement to page pointer in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_PAGE, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_PAGE",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Offset from page pointer in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_OFST, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_OFST",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_GOT_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_HI16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_GOT_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_LO16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 64 bit subtraction. Used in the N32 ABI. */
+ HOWTO (R_MICROMIPS_SUB, /* type */
+ 0, /* rightshift */
+ 4, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_SUB", /* name */
+ TRUE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Get the higher value of a 64 bit addend. */
+ HOWTO (R_MICROMIPS_HIGHER, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_HIGHER", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Get the highest value of a 64 bit addend. */
+ HOWTO (R_MICROMIPS_HIGHEST, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_HIGHEST", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_CALL_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL_HI16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_CALL_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL_LO16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Section displacement. */
+ HOWTO (R_MICROMIPS_SCN_DISP, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_SCN_DISP",/* name */
+ TRUE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Protected jump conversion. This is an optimization hint. No
+ relocation is required for correctness. */
+ HOWTO (R_MICROMIPS_JALR, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_JALR", /* name */
+ FALSE, /* partial_inplace */
+ 0x00000000, /* src_mask */
+ 0x00000000, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of symbol value. Note that the high 16 bits of symbol values
+ must be zero. This is used for relaxation. */
+ HOWTO (R_MICROMIPS_HI0_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_HI0_LO16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (158),
+ EMPTY_HOWTO (159),
+ EMPTY_HOWTO (160),
+ EMPTY_HOWTO (161),
+
+ /* TLS general dynamic variable reference. */
+ HOWTO (R_MICROMIPS_TLS_GD, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_TLS_GD", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* TLS local dynamic variable reference. */
+ HOWTO (R_MICROMIPS_TLS_LDM, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_TLS_LDM", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* TLS local dynamic offset. */
+ HOWTO (R_MICROMIPS_TLS_DTPREL_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_TLS_DTPREL_HI16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* TLS local dynamic offset. */
+ HOWTO (R_MICROMIPS_TLS_DTPREL_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_TLS_DTPREL_LO16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* TLS thread pointer offset. */
+ HOWTO (R_MICROMIPS_TLS_GOTTPREL, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_TLS_GOTTPREL", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (167),
+ EMPTY_HOWTO (168),
+
+ /* TLS thread pointer offset. */
+ HOWTO (R_MICROMIPS_TLS_TPREL_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_TLS_TPREL_HI16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* TLS thread pointer offset. */
+ HOWTO (R_MICROMIPS_TLS_TPREL_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_TLS_TPREL_LO16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (171),
+
+ /* GP- and PC-relative relocations. */
+ HOWTO (R_MICROMIPS_GPREL7_S2, /* type */
+ 2, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 7, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_GPREL7_S2", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000007f, /* src_mask */
+ 0x0000007f, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC23_S2, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 23, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC23_S2", /* name */
+ TRUE, /* partial_inplace */
+ 0x007fffff, /* src_mask */
+ 0x007fffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+};
+
/* 16 bit offset for pc-relative branches. */
static reloc_howto_type elf_mips_gnu_rel16_s2 =
HOWTO (R_MIPS_GNU_REL16_S2, /* type */
{
bfd_boolean relocatable;
bfd_reloc_status_type ret;
+ bfd_byte *location;
bfd_vma gp;
- /* R_MIPS_LITERAL relocations are defined for local symbols only. */
- if (reloc_entry->howto->type == R_MIPS_LITERAL
+ /* R_MIPS_LITERAL/R_MICROMIPS_LITERAL relocations are defined for local
+ symbols only. */
+ if (literal_reloc_p (reloc_entry->howto->type)
&& output_bfd != NULL
&& (symbol->flags & BSF_SECTION_SYM) == 0
&& (symbol->flags & BSF_LOCAL) != 0)
if (ret != bfd_reloc_ok)
return ret;
- return _bfd_mips_elf_gprel16_with_gp (abfd, symbol, reloc_entry,
- input_section, relocatable,
- data, gp);
+ location = (bfd_byte *) data + reloc_entry->address;
+ _bfd_mips_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
+ ret = _bfd_mips_elf_gprel16_with_gp (abfd, symbol, reloc_entry,
+ input_section, relocatable,
+ data, gp);
+ _bfd_mips_elf_reloc_shuffle (abfd, reloc_entry->howto->type, !relocatable,
+ location);
+
+ return ret;
}
/* Do a R_MIPS_GPREL32 relocation. This is a 32 bit value which must
return ret;
location = (bfd_byte *) data + reloc_entry->address;
- _bfd_mips16_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
- location);
+ _bfd_mips_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
ret = _bfd_mips_elf_gprel16_with_gp (abfd, symbol, reloc_entry,
input_section, relocatable,
data, gp);
- _bfd_mips16_elf_reloc_shuffle (abfd, reloc_entry->howto->type, !relocatable,
- location);
+ _bfd_mips_elf_reloc_shuffle (abfd, reloc_entry->howto->type, !relocatable,
+ location);
return ret;
}
{ BFD_RELOC_MIPS16_LO16, R_MIPS16_LO16 - R_MIPS16_min },
};
+static const struct elf_reloc_map micromips_reloc_map[] =
+{
+ { BFD_RELOC_MICROMIPS_JMP, R_MICROMIPS_26_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_HI16_S, R_MICROMIPS_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_LO16, R_MICROMIPS_LO16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GPREL16, R_MICROMIPS_GPREL16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_LITERAL, R_MICROMIPS_LITERAL - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT16, R_MICROMIPS_GOT16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_7_PCREL_S1, R_MICROMIPS_PC7_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_10_PCREL_S1, R_MICROMIPS_PC10_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_16_PCREL_S1, R_MICROMIPS_PC16_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_CALL16, R_MICROMIPS_CALL16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_DISP, R_MICROMIPS_GOT_DISP - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_PAGE - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_OFST, R_MICROMIPS_GOT_OFST - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_LO16, R_MICROMIPS_GOT_LO16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_SUB, R_MICROMIPS_SUB - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_HIGHER, R_MICROMIPS_HIGHER - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_HIGHEST, R_MICROMIPS_HIGHEST - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_CALL_HI16, R_MICROMIPS_CALL_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_CALL_LO16, R_MICROMIPS_CALL_LO16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_SCN_DISP, R_MICROMIPS_SCN_DISP - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_JALR, R_MICROMIPS_JALR - R_MICROMIPS_min },
+ /* There is no BFD reloc for R_MICROMIPS_HI0_LO16. */
+ { BFD_RELOC_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_GD - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_TLS_LDM, R_MICROMIPS_TLS_LDM - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16,
+ R_MICROMIPS_TLS_DTPREL_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16,
+ R_MICROMIPS_TLS_DTPREL_LO16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_TLS_GOTTPREL,
+ R_MICROMIPS_TLS_GOTTPREL - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_TLS_TPREL_HI16,
+ R_MICROMIPS_TLS_TPREL_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_TLS_TPREL_LO16,
+ R_MICROMIPS_TLS_TPREL_LO16 - R_MICROMIPS_min },
+ /* There is no BFD reloc for R_MICROMIPS_GPREL7_S2. */
+ /* There is no BFD reloc for R_MICROMIPS_PC23_S2. */
+};
+
/* Given a BFD reloc type, return a howto structure. */
static reloc_howto_type *
unsigned int i;
reloc_howto_type *howto_table = elf_mips_howto_table_rel;
reloc_howto_type *howto16_table = elf_mips16_howto_table_rel;
+ reloc_howto_type *howto_micromips_table = elf_micromips_howto_table_rel;
for (i = 0; i < sizeof (mips_reloc_map) / sizeof (struct elf_reloc_map);
i++)
return &howto16_table[(int) mips16_reloc_map[i].elf_val];
}
+ for (i = 0; i < sizeof (micromips_reloc_map) / sizeof (struct elf_reloc_map);
+ i++)
+ {
+ if (micromips_reloc_map[i].bfd_val == code)
+ return &howto_micromips_table[(int) micromips_reloc_map[i].elf_val];
+ }
+
switch (code)
{
default:
&& strcasecmp (elf_mips16_howto_table_rel[i].name, r_name) == 0)
return &elf_mips16_howto_table_rel[i];
+ for (i = 0;
+ i < (sizeof (elf_micromips_howto_table_rel)
+ / sizeof (elf_micromips_howto_table_rel[0]));
+ i++)
+ if (elf_micromips_howto_table_rel[i].name != NULL
+ && strcasecmp (elf_micromips_howto_table_rel[i].name, r_name) == 0)
+ return &elf_micromips_howto_table_rel[i];
+
if (strcasecmp (elf_mips_gnu_pcrel32.name, r_name) == 0)
return &elf_mips_gnu_pcrel32;
if (strcasecmp (elf_mips_gnu_rel16_s2.name, r_name) == 0)
case R_MIPS_JUMP_SLOT:
return &elf_mips_jump_slot_howto;
default:
+ if (r_type >= R_MICROMIPS_min && r_type < R_MICROMIPS_max)
+ return &elf_micromips_howto_table_rel[r_type - R_MICROMIPS_min];
if (r_type >= R_MIPS16_min && r_type < R_MIPS16_max)
return &elf_mips16_howto_table_rel[r_type - R_MIPS16_min];
BFD_ASSERT (r_type < (unsigned int) R_MIPS_max);
when we do the relocation, because the symbol manipulations done
by the linker may cause us to lose track of the input BFD. */
if (((*cache_ptr->sym_ptr_ptr)->flags & BSF_SECTION_SYM) != 0
- && (gprel16_reloc_p (r_type) || r_type == (unsigned int) R_MIPS_LITERAL))
+ && (gprel16_reloc_p (r_type) || literal_reloc_p (r_type)))
cache_ptr->addend = elf_gp (abfd);
}
#define elf_backend_mips_rtype_to_howto mips_elf32_rtype_to_howto
#define bfd_elf32_bfd_is_local_label_name \
mips_elf_is_local_label_name
+#define bfd_elf32_bfd_is_target_special_symbol \
+ _bfd_mips_elf_is_target_special_symbol
#define bfd_elf32_find_nearest_line _bfd_mips_elf_find_nearest_line
#define bfd_elf32_find_inliner_info _bfd_mips_elf_find_inliner_info
#define bfd_elf32_new_section_hook _bfd_mips_elf_new_section_hook
#define bfd_elf32_bfd_set_private_flags _bfd_mips_elf_set_private_flags
#define bfd_elf32_bfd_print_private_bfd_data \
_bfd_mips_elf_print_private_bfd_data
+#define bfd_elf32_bfd_relax_section _bfd_mips_elf_relax_section
/* Support for SGI-ish mips targets. */
#define TARGET_LITTLE_SYM bfd_elf32_littlemips_vec
FALSE), /* pcrel_offset */
};
+static reloc_howto_type micromips_elf64_howto_table_rel[] =
+{
+ EMPTY_HOWTO (130),
+ EMPTY_HOWTO (131),
+ EMPTY_HOWTO (132),
+
+ /* 26 bit jump address. */
+ HOWTO (R_MICROMIPS_26_S1, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 26, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ /* This needs complex overflow
+ detection, because the upper four
+ bits must match the PC. */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_26_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x3ffffff, /* src_mask */
+ 0x3ffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of symbol value. */
+ HOWTO (R_MICROMIPS_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_hi16_reloc, /* special_function */
+ "R_MICROMIPS_HI16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of symbol value. */
+ HOWTO (R_MICROMIPS_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_lo16_reloc, /* special_function */
+ "R_MICROMIPS_LO16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* GP relative reference. */
+ HOWTO (R_MICROMIPS_GPREL16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_GPREL16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reference to literal section. */
+ HOWTO (R_MICROMIPS_LITERAL, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_LITERAL", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reference to global offset table. */
+ HOWTO (R_MICROMIPS_GOT16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_got16_reloc, /* special_function */
+ "R_MICROMIPS_GOT16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* This is for microMIPS branches. */
+ HOWTO (R_MICROMIPS_PC7_S1, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 7, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC7_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000007f, /* src_mask */
+ 0x0000007f, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC10_S1, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 10, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC10_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x000003ff, /* src_mask */
+ 0x000003ff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC16_S1, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC16_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 16 bit call through global offset table. */
+ HOWTO (R_MICROMIPS_CALL16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (143),
+ EMPTY_HOWTO (144),
+
+ /* Displacement in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_DISP, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_DISP",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Displacement to page pointer in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_PAGE, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_PAGE",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Offset from page pointer in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_OFST, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_OFST",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_GOT_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_HI16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_GOT_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_LO16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 64 bit subtraction. Used in the N32 ABI. */
+ HOWTO (R_MICROMIPS_SUB, /* type */
+ 0, /* rightshift */
+ 4, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_SUB", /* name */
+ TRUE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* We don't support these for REL relocations, because it means building
+ the addend from a R_MICROMIPS_HIGHEST/R_MICROMIPS_HIGHER/
+ R_MICROMIPS_HI16/R_MICROMIPS_LO16 sequence with varying ordering,
+ using fallable heuristics. */
+ EMPTY_HOWTO (R_MICROMIPS_HIGHER),
+ EMPTY_HOWTO (R_MICROMIPS_HIGHEST),
+
+ /* High 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_CALL_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL_HI16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_CALL_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL_LO16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
+
+static reloc_howto_type micromips_elf64_howto_table_rela[] =
+{
+ EMPTY_HOWTO (130),
+ EMPTY_HOWTO (131),
+ EMPTY_HOWTO (132),
+
+ /* 26 bit jump address. */
+ HOWTO (R_MICROMIPS_26_S1, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 26, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ /* This needs complex overflow
+ detection, because the upper four
+ bits must match the PC. */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_26_S1", /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffffff, /* src_mask */
+ 0x3ffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of symbol value. */
+ HOWTO (R_MICROMIPS_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_hi16_reloc, /* special_function */
+ "R_MICROMIPS_HI16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of symbol value. */
+ HOWTO (R_MICROMIPS_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_lo16_reloc, /* special_function */
+ "R_MICROMIPS_LO16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* GP relative reference. */
+ HOWTO (R_MICROMIPS_GPREL16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_GPREL16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reference to literal section. */
+ HOWTO (R_MICROMIPS_LITERAL, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_LITERAL", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reference to global offset table. */
+ HOWTO (R_MICROMIPS_GOT16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_got16_reloc, /* special_function */
+ "R_MICROMIPS_GOT16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* This is for microMIPS branches. */
+ HOWTO (R_MICROMIPS_PC7_S1, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 7, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC7_S1", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000007f, /* src_mask */
+ 0x0000007f, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC10_S1, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 10, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC10_S1", /* name */
+ FALSE, /* partial_inplace */
+ 0x000003ff, /* src_mask */
+ 0x000003ff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC16_S1, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC16_S1", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 16 bit call through global offset table. */
+ HOWTO (R_MICROMIPS_CALL16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (143),
+ EMPTY_HOWTO (144),
+
+ /* Displacement in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_DISP, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_DISP",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Displacement to page pointer in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_PAGE, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_PAGE",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Offset from page pointer in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_OFST, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_OFST",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_GOT_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_HI16",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_GOT_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_LO16",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 64 bit subtraction. Used in the N32 ABI. */
+ HOWTO (R_MICROMIPS_SUB, /* type */
+ 0, /* rightshift */
+ 4, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_SUB", /* name */
+ FALSE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Get the higher value of a 64 bit addend. */
+ HOWTO (R_MICROMIPS_HIGHER, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_HIGHER", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Get the highest value of a 64 bit addend. */
+ HOWTO (R_MICROMIPS_HIGHEST, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_HIGHEST", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_CALL_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL_HI16",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_CALL_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL_LO16",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
+
/* GNU extension to record C++ vtable hierarchy */
static reloc_howto_type elf_mips_gnu_vtinherit_howto =
HOWTO (R_MIPS_GNU_VTINHERIT, /* type */
return ret;
location = (bfd_byte *) data + reloc_entry->address;
- _bfd_mips16_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
- location);
+ _bfd_mips_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
ret = _bfd_mips_elf_gprel16_with_gp (abfd, symbol, reloc_entry,
input_section, relocatable,
data, gp);
- _bfd_mips16_elf_reloc_shuffle (abfd, reloc_entry->howto->type, !relocatable,
- location);
+ _bfd_mips_elf_reloc_shuffle (abfd, reloc_entry->howto->type, !relocatable,
+ location);
return ret;
}
{ BFD_RELOC_MIPS16_LO16, R_MIPS16_LO16 - R_MIPS16_min },
};
+static const struct elf_reloc_map micromips_reloc_map[] =
+{
+ { BFD_RELOC_MICROMIPS_JMP, R_MICROMIPS_26_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_HI16_S, R_MICROMIPS_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_LO16, R_MICROMIPS_LO16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GPREL16, R_MICROMIPS_GPREL16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_LITERAL, R_MICROMIPS_LITERAL - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT16, R_MICROMIPS_GOT16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_7_PCREL_S1, R_MICROMIPS_PC7_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_10_PCREL_S1, R_MICROMIPS_PC10_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_16_PCREL_S1, R_MICROMIPS_PC16_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_CALL16, R_MICROMIPS_CALL16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_DISP, R_MICROMIPS_GOT_DISP - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_PAGE - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_OFST, R_MICROMIPS_GOT_OFST - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_LO16, R_MICROMIPS_GOT_LO16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_SUB, R_MICROMIPS_SUB - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_HIGHER, R_MICROMIPS_HIGHER - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_HIGHEST, R_MICROMIPS_HIGHEST - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_CALL_HI16, R_MICROMIPS_CALL_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_CALL_LO16, R_MICROMIPS_CALL_LO16 - R_MICROMIPS_min },
+};
/* Given a BFD reloc type, return a howto structure. */
static reloc_howto_type *
relocation variant. */
reloc_howto_type *howto_table = mips_elf64_howto_table_rela;
reloc_howto_type *howto16_table = mips16_elf64_howto_table_rela;
+ reloc_howto_type *howto_micromips_table = micromips_elf64_howto_table_rela;
for (i = 0; i < sizeof (mips_reloc_map) / sizeof (struct elf_reloc_map);
i++)
return &howto16_table[(int) mips16_reloc_map[i].elf_val];
}
+ for (i = 0; i < sizeof (micromips_reloc_map) / sizeof (struct elf_reloc_map);
+ i++)
+ {
+ if (micromips_reloc_map[i].bfd_val == code)
+ return &howto_micromips_table[(int) micromips_reloc_map[i].elf_val];
+ }
+
switch (code)
{
case BFD_RELOC_VTABLE_INHERIT:
&& strcasecmp (mips16_elf64_howto_table_rela[i].name, r_name) == 0)
return &mips16_elf64_howto_table_rela[i];
+ for (i = 0;
+ i < (sizeof (micromips_elf64_howto_table_rela)
+ / sizeof (micromips_elf64_howto_table_rela[0]));
+ i++)
+ if (micromips_elf64_howto_table_rela[i].name != NULL
+ && strcasecmp (micromips_elf64_howto_table_rela[i].name, r_name) == 0)
+ return µmips_elf64_howto_table_rela[i];
+
if (strcasecmp (elf_mips_gnu_vtinherit_howto.name, r_name) == 0)
return &elf_mips_gnu_vtinherit_howto;
if (strcasecmp (elf_mips_gnu_vtentry_howto.name, r_name) == 0)
case R_MIPS_JUMP_SLOT:
return &elf_mips_jump_slot_howto;
default:
+ if (r_type >= R_MICROMIPS_min && r_type < R_MICROMIPS_max)
+ {
+ if (rela_p)
+ return µmips_elf64_howto_table_rela[r_type - R_MICROMIPS_min];
+ else
+ return µmips_elf64_howto_table_rel[r_type - R_MICROMIPS_min];
+ }
if (r_type >= R_MIPS16_min && r_type < R_MIPS16_max)
{
if (rela_p)
/* We don't set bfd_elf64_bfd_is_local_label_name because the 32-bit
MIPS-specific function only applies to IRIX5, which had no 64-bit
ABI. */
+#define bfd_elf64_bfd_is_target_special_symbol \
+ _bfd_mips_elf_is_target_special_symbol
#define bfd_elf64_find_nearest_line _bfd_mips_elf_find_nearest_line
#define bfd_elf64_find_inliner_info _bfd_mips_elf_find_inliner_info
#define bfd_elf64_new_section_hook _bfd_mips_elf_new_section_hook
FALSE), /* pcrel_offset */
};
+static reloc_howto_type elf_micromips_howto_table_rel[] =
+{
+ EMPTY_HOWTO (130),
+ EMPTY_HOWTO (131),
+ EMPTY_HOWTO (132),
+
+ /* 26 bit jump address. */
+ HOWTO (R_MICROMIPS_26_S1, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 26, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ /* This needs complex overflow
+ detection, because the upper four
+ bits must match the PC. */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_26_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x3ffffff, /* src_mask */
+ 0x3ffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of symbol value. */
+ HOWTO (R_MICROMIPS_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_hi16_reloc, /* special_function */
+ "R_MICROMIPS_HI16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of symbol value. */
+ HOWTO (R_MICROMIPS_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_lo16_reloc, /* special_function */
+ "R_MICROMIPS_LO16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* GP relative reference. */
+ HOWTO (R_MICROMIPS_GPREL16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_GPREL16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reference to literal section. */
+ HOWTO (R_MICROMIPS_LITERAL, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_LITERAL", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reference to global offset table. */
+ HOWTO (R_MICROMIPS_GOT16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_got16_reloc, /* special_function */
+ "R_MICROMIPS_GOT16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* This is for microMIPS branches. */
+ HOWTO (R_MICROMIPS_PC7_S1, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 7, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC7_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000007f, /* src_mask */
+ 0x0000007f, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC10_S1, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 10, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC10_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x000003ff, /* src_mask */
+ 0x000003ff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC16_S1, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC16_S1", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 16 bit call through global offset table. */
+ HOWTO (R_MICROMIPS_CALL16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (143),
+ EMPTY_HOWTO (144),
+
+ /* Displacement in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_DISP, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_DISP",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Displacement to page pointer in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_PAGE, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_PAGE",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Offset from page pointer in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_OFST, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_OFST",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_GOT_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_HI16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_GOT_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_LO16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 64 bit subtraction. Used in the N32 ABI. */
+ HOWTO (R_MICROMIPS_SUB, /* type */
+ 0, /* rightshift */
+ 4, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_SUB", /* name */
+ TRUE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* We don't support these for REL relocations, because it means building
+ the addend from a R_MICROMIPS_HIGHEST/R_MICROMIPS_HIGHER/
+ R_MICROMIPS_HI16/R_MICROMIPS_LO16 sequence with varying ordering,
+ using fallable heuristics. */
+ EMPTY_HOWTO (R_MICROMIPS_HIGHER),
+ EMPTY_HOWTO (R_MICROMIPS_HIGHEST),
+
+ /* High 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_CALL_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL_HI16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_CALL_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL_LO16",/* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
+
+static reloc_howto_type elf_micromips_howto_table_rela[] =
+{
+ EMPTY_HOWTO (130),
+ EMPTY_HOWTO (131),
+ EMPTY_HOWTO (132),
+
+ /* 26 bit jump address. */
+ HOWTO (R_MICROMIPS_26_S1, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 26, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ /* This needs complex overflow
+ detection, because the upper four
+ bits must match the PC. */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_26_S1", /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffffff, /* src_mask */
+ 0x3ffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of symbol value. */
+ HOWTO (R_MICROMIPS_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_hi16_reloc, /* special_function */
+ "R_MICROMIPS_HI16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of symbol value. */
+ HOWTO (R_MICROMIPS_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_lo16_reloc, /* special_function */
+ "R_MICROMIPS_LO16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* GP relative reference. */
+ HOWTO (R_MICROMIPS_GPREL16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_GPREL16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reference to literal section. */
+ HOWTO (R_MICROMIPS_LITERAL, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf32_gprel16_reloc, /* special_function */
+ "R_MICROMIPS_LITERAL", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reference to global offset table. */
+ HOWTO (R_MICROMIPS_GOT16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_got16_reloc, /* special_function */
+ "R_MICROMIPS_GOT16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* This is for microMIPS branches. */
+ HOWTO (R_MICROMIPS_PC7_S1, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 7, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC7_S1", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000007f, /* src_mask */
+ 0x0000007f, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC10_S1, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 10, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC10_S1", /* name */
+ FALSE, /* partial_inplace */
+ 0x000003ff, /* src_mask */
+ 0x000003ff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ HOWTO (R_MICROMIPS_PC16_S1, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_PC16_S1", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 16 bit call through global offset table. */
+ HOWTO (R_MICROMIPS_CALL16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (143),
+ EMPTY_HOWTO (144),
+
+ /* Displacement in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_DISP, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_DISP",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Displacement to page pointer in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_PAGE, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_PAGE",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Offset from page pointer in the global offset table. */
+ HOWTO (R_MICROMIPS_GOT_OFST, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_OFST",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_GOT_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_HI16",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_GOT_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_GOT_LO16",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 64 bit subtraction. Used in the N32 ABI. */
+ HOWTO (R_MICROMIPS_SUB, /* type */
+ 0, /* rightshift */
+ 4, /* size (0 = byte, 1 = short, 2 = long) */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_SUB", /* name */
+ FALSE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Get the higher value of a 64 bit addend. */
+ HOWTO (R_MICROMIPS_HIGHER, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_HIGHER", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Get the highest value of a 64 bit addend. */
+ HOWTO (R_MICROMIPS_HIGHEST, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_HIGHEST", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_CALL_HI16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL_HI16",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 16 bits of displacement in global offset table. */
+ HOWTO (R_MICROMIPS_CALL_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_generic_reloc, /* special_function */
+ "R_MICROMIPS_CALL_LO16",/* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
+
/* GNU extension to record C++ vtable hierarchy */
static reloc_howto_type elf_mips_gnu_vtinherit_howto =
HOWTO (R_MIPS_GNU_VTINHERIT, /* type */
return ret;
location = (bfd_byte *) data + reloc_entry->address;
- _bfd_mips16_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
- location);
+ _bfd_mips_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
ret = _bfd_mips_elf_gprel16_with_gp (abfd, symbol, reloc_entry,
input_section, relocatable,
data, gp);
- _bfd_mips16_elf_reloc_shuffle (abfd, reloc_entry->howto->type, !relocatable,
- location);
+ _bfd_mips_elf_reloc_shuffle (abfd, reloc_entry->howto->type, !relocatable,
+ location);
return ret;
}
{ BFD_RELOC_MIPS16_LO16, R_MIPS16_LO16 - R_MIPS16_min },
};
+static const struct elf_reloc_map micromips_reloc_map[] =
+{
+ { BFD_RELOC_MICROMIPS_JMP, R_MICROMIPS_26_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_HI16_S, R_MICROMIPS_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_LO16, R_MICROMIPS_LO16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GPREL16, R_MICROMIPS_GPREL16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_LITERAL, R_MICROMIPS_LITERAL - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT16, R_MICROMIPS_GOT16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_7_PCREL_S1, R_MICROMIPS_PC7_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_10_PCREL_S1, R_MICROMIPS_PC10_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_16_PCREL_S1, R_MICROMIPS_PC16_S1 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_CALL16, R_MICROMIPS_CALL16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_DISP, R_MICROMIPS_GOT_DISP - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_PAGE - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_OFST, R_MICROMIPS_GOT_OFST - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_GOT_LO16, R_MICROMIPS_GOT_LO16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_SUB, R_MICROMIPS_SUB - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_HIGHER, R_MICROMIPS_HIGHER - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_HIGHEST, R_MICROMIPS_HIGHEST - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_CALL_HI16, R_MICROMIPS_CALL_HI16 - R_MICROMIPS_min },
+ { BFD_RELOC_MICROMIPS_CALL_LO16, R_MICROMIPS_CALL_LO16 - R_MICROMIPS_min },
+};
+
/* Given a BFD reloc type, return a howto structure. */
static reloc_howto_type *
relocation variant. */
reloc_howto_type *howto_table = elf_mips_howto_table_rela;
reloc_howto_type *howto16_table = elf_mips16_howto_table_rela;
+ reloc_howto_type *howto_micromips_table = elf_micromips_howto_table_rela;
for (i = 0; i < sizeof (mips_reloc_map) / sizeof (struct elf_reloc_map);
i++)
return &howto16_table[(int) mips16_reloc_map[i].elf_val];
}
+ for (i = 0; i < sizeof (micromips_reloc_map) / sizeof (struct elf_reloc_map);
+ i++)
+ {
+ if (micromips_reloc_map[i].bfd_val == code)
+ return &howto_micromips_table[(int) micromips_reloc_map[i].elf_val];
+ }
+
switch (code)
{
case BFD_RELOC_VTABLE_INHERIT:
&& strcasecmp (elf_mips16_howto_table_rela[i].name, r_name) == 0)
return &elf_mips16_howto_table_rela[i];
+ for (i = 0;
+ i < (sizeof (elf_micromips_howto_table_rela)
+ / sizeof (elf_micromips_howto_table_rela[0]));
+ i++)
+ if (elf_micromips_howto_table_rela[i].name != NULL
+ && strcasecmp (elf_micromips_howto_table_rela[i].name, r_name) == 0)
+ return &elf_micromips_howto_table_rela[i];
+
if (strcasecmp (elf_mips_gnu_vtinherit_howto.name, r_name) == 0)
return &elf_mips_gnu_vtinherit_howto;
if (strcasecmp (elf_mips_gnu_vtentry_howto.name, r_name) == 0)
case R_MIPS_JUMP_SLOT:
return &elf_mips_jump_slot_howto;
default:
+ if (r_type >= R_MICROMIPS_min && r_type < R_MICROMIPS_max)
+ {
+ if (rela_p)
+ return &elf_micromips_howto_table_rela[r_type - R_MICROMIPS_min];
+ else
+ return &elf_micromips_howto_table_rel[r_type - R_MICROMIPS_min];
+ }
if (r_type >= R_MIPS16_min && r_type < R_MIPS16_max)
{
if (rela_p)
#define elf_backend_write_section _bfd_mips_elf_write_section
#define elf_backend_mips_irix_compat elf_n32_mips_irix_compat
#define elf_backend_mips_rtype_to_howto mips_elf_n32_rtype_to_howto
+#define bfd_elf32_bfd_is_target_special_symbol \
+ _bfd_mips_elf_is_target_special_symbol
#define bfd_elf32_find_nearest_line _bfd_mips_elf_find_nearest_line
#define bfd_elf32_find_inliner_info _bfd_mips_elf_find_inliner_info
#define bfd_elf32_new_section_hook _bfd_mips_elf_new_section_hook
#define LA25_LUI(VAL) (0x3c190000 | (VAL)) /* lui t9,VAL */
#define LA25_J(VAL) (0x08000000 | (((VAL) >> 2) & 0x3ffffff)) /* j VAL */
#define LA25_ADDIU(VAL) (0x27390000 | (VAL)) /* addiu t9,t9,VAL */
+#define LA25_LUI_MICROMIPS_1(VAL) (0x41b9) /* lui t9,VAL */
+#define LA25_LUI_MICROMIPS_2(VAL) (VAL)
+#define LA25_J_MICROMIPS_1(VAL) (0xd400 | (((VAL) >> 17) & 0x3ff)) /* j VAL */
+#define LA25_J_MICROMIPS_2(VAL) ((VAL) >> 1)
+#define LA25_ADDIU_MICROMIPS_1(VAL) (0x3339) /* addiu t9,t9,VAL */
+#define LA25_ADDIU_MICROMIPS_2(VAL) (VAL)
/* This structure is passed to mips_elf_sort_hash_table_f when sorting
the dynamic symbols. */
|| r_type == R_MIPS_TLS_TPREL32 \
|| r_type == R_MIPS_TLS_TPREL64 \
|| r_type == R_MIPS_TLS_TPREL_HI16 \
- || r_type == R_MIPS_TLS_TPREL_LO16)
+ || r_type == R_MIPS_TLS_TPREL_LO16 \
+ || r_type == R_MICROMIPS_TLS_GD \
+ || r_type == R_MICROMIPS_TLS_LDM \
+ || r_type == R_MICROMIPS_TLS_DTPREL_HI16 \
+ || r_type == R_MICROMIPS_TLS_DTPREL_LO16 \
+ || r_type == R_MICROMIPS_TLS_GOTTPREL \
+ || r_type == R_MICROMIPS_TLS_TPREL_HI16 \
+ || r_type == R_MICROMIPS_TLS_TPREL_LO16)
/* Structure used to pass information to mips_elf_output_extsym. */
struct elf_link_hash_entry *elfh;
const char *name;
+ if (ELF_ST_IS_MICROMIPS (h->root.other))
+ value |= 1;
+
/* Create a new symbol. */
name = ACONCAT ((prefix, h->root.root.root.string, NULL));
bh = NULL;
}
}
+/* Check if a microMIPS reloc. */
+
+static inline bfd_boolean
+micromips_reloc_p (unsigned int r_type)
+{
+ return r_type >= R_MICROMIPS_min && r_type < R_MICROMIPS_max;
+}
+
+/* Similar to MIPS16, the two 16-bit halves in microMIPS must be swapped
+ on a little-endian system. This does not apply to R_MICROMIPS_PC7_S1
+ and R_MICROMIPS_PC10_S1 relocs that apply to 16-bit instructions. */
+
+static inline bfd_boolean
+micromips_reloc_shuffle_p (unsigned int r_type)
+{
+ return (micromips_reloc_p (r_type)
+ && r_type != R_MICROMIPS_PC7_S1
+ && r_type != R_MICROMIPS_PC10_S1);
+}
+
static inline bfd_boolean
got16_reloc_p (int r_type)
{
- return r_type == R_MIPS_GOT16 || r_type == R_MIPS16_GOT16;
+ return (r_type == R_MIPS_GOT16
+ || r_type == R_MIPS16_GOT16
+ || r_type == R_MICROMIPS_GOT16);
}
static inline bfd_boolean
call16_reloc_p (int r_type)
{
- return r_type == R_MIPS_CALL16 || r_type == R_MIPS16_CALL16;
+ return (r_type == R_MIPS_CALL16
+ || r_type == R_MIPS16_CALL16
+ || r_type == R_MICROMIPS_CALL16);
+}
+
+static inline bfd_boolean
+got_disp_reloc_p (unsigned int r_type)
+{
+ return r_type == R_MIPS_GOT_DISP || r_type == R_MICROMIPS_GOT_DISP;
+}
+
+static inline bfd_boolean
+got_page_reloc_p (unsigned int r_type)
+{
+ return r_type == R_MIPS_GOT_PAGE || r_type == R_MICROMIPS_GOT_PAGE;
+}
+
+static inline bfd_boolean
+got_ofst_reloc_p (unsigned int r_type)
+{
+ return r_type == R_MIPS_GOT_OFST || r_type == R_MICROMIPS_GOT_OFST;
+}
+
+static inline bfd_boolean
+got_hi16_reloc_p (unsigned int r_type)
+{
+ return r_type == R_MIPS_GOT_HI16 || r_type == R_MICROMIPS_GOT_HI16;
+}
+
+static inline bfd_boolean
+got_lo16_reloc_p (unsigned int r_type)
+{
+ return r_type == R_MIPS_GOT_LO16 || r_type == R_MICROMIPS_GOT_LO16;
+}
+
+static inline bfd_boolean
+call_hi16_reloc_p (unsigned int r_type)
+{
+ return r_type == R_MIPS_CALL_HI16 || r_type == R_MICROMIPS_CALL_HI16;
+}
+
+static inline bfd_boolean
+call_lo16_reloc_p (unsigned int r_type)
+{
+ return r_type == R_MIPS_CALL_LO16 || r_type == R_MICROMIPS_CALL_LO16;
}
static inline bfd_boolean
hi16_reloc_p (int r_type)
{
- return r_type == R_MIPS_HI16 || r_type == R_MIPS16_HI16;
+ return (r_type == R_MIPS_HI16
+ || r_type == R_MIPS16_HI16
+ || r_type == R_MICROMIPS_HI16);
}
static inline bfd_boolean
lo16_reloc_p (int r_type)
{
- return r_type == R_MIPS_LO16 || r_type == R_MIPS16_LO16;
+ return (r_type == R_MIPS_LO16
+ || r_type == R_MIPS16_LO16
+ || r_type == R_MICROMIPS_LO16);
}
static inline bfd_boolean
static inline bfd_boolean
jal_reloc_p (int r_type)
{
- return r_type == R_MIPS_26 || r_type == R_MIPS16_26;
+ return (r_type == R_MIPS_26
+ || r_type == R_MIPS16_26
+ || r_type == R_MICROMIPS_26_S1);
+}
+
+static inline bfd_boolean
+micromips_branch_reloc_p (int r_type)
+{
+ return (r_type == R_MICROMIPS_26_S1
+ || r_type == R_MICROMIPS_PC16_S1
+ || r_type == R_MICROMIPS_PC10_S1
+ || r_type == R_MICROMIPS_PC7_S1);
+}
+
+static inline bfd_boolean
+tls_gd_reloc_p (unsigned int r_type)
+{
+ return r_type == R_MIPS_TLS_GD || r_type == R_MICROMIPS_TLS_GD;
+}
+
+static inline bfd_boolean
+tls_ldm_reloc_p (unsigned int r_type)
+{
+ return r_type == R_MIPS_TLS_LDM || r_type == R_MICROMIPS_TLS_LDM;
+}
+
+static inline bfd_boolean
+tls_gottprel_reloc_p (unsigned int r_type)
+{
+ return r_type == R_MIPS_TLS_GOTTPREL || r_type == R_MICROMIPS_TLS_GOTTPREL;
}
void
-_bfd_mips16_elf_reloc_unshuffle (bfd *abfd, int r_type,
- bfd_boolean jal_shuffle, bfd_byte *data)
+_bfd_mips_elf_reloc_unshuffle (bfd *abfd, int r_type,
+ bfd_boolean jal_shuffle, bfd_byte *data)
{
- bfd_vma extend, insn, val;
+ bfd_vma first, second, val;
- if (!mips16_reloc_p (r_type))
+ if (!mips16_reloc_p (r_type) && !micromips_reloc_shuffle_p (r_type))
return;
- /* Pick up the mips16 extend instruction and the real instruction. */
- extend = bfd_get_16 (abfd, data);
- insn = bfd_get_16 (abfd, data + 2);
- if (r_type == R_MIPS16_26)
- {
- if (jal_shuffle)
- val = ((extend & 0xfc00) << 16) | ((extend & 0x3e0) << 11)
- | ((extend & 0x1f) << 21) | insn;
- else
- val = extend << 16 | insn;
- }
+ /* Pick up the first and second halfwords of the instruction. */
+ first = bfd_get_16 (abfd, data);
+ second = bfd_get_16 (abfd, data + 2);
+ if (micromips_reloc_p (r_type) || (r_type == R_MIPS16_26 && !jal_shuffle))
+ val = first << 16 | second;
+ else if (r_type != R_MIPS16_26)
+ val = (((first & 0xf800) << 16) | ((second & 0xffe0) << 11)
+ | ((first & 0x1f) << 11) | (first & 0x7e0) | (second & 0x1f));
else
- val = ((extend & 0xf800) << 16) | ((insn & 0xffe0) << 11)
- | ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f);
+ val = (((first & 0xfc00) << 16) | ((first & 0x3e0) << 11)
+ | ((first & 0x1f) << 21) | second);
bfd_put_32 (abfd, val, data);
}
void
-_bfd_mips16_elf_reloc_shuffle (bfd *abfd, int r_type,
- bfd_boolean jal_shuffle, bfd_byte *data)
+_bfd_mips_elf_reloc_shuffle (bfd *abfd, int r_type,
+ bfd_boolean jal_shuffle, bfd_byte *data)
{
- bfd_vma extend, insn, val;
+ bfd_vma first, second, val;
- if (!mips16_reloc_p (r_type))
+ if (!mips16_reloc_p (r_type) && !micromips_reloc_shuffle_p (r_type))
return;
val = bfd_get_32 (abfd, data);
- if (r_type == R_MIPS16_26)
+ if (micromips_reloc_p (r_type) || (r_type == R_MIPS16_26 && !jal_shuffle))
{
- if (jal_shuffle)
- {
- insn = val & 0xffff;
- extend = ((val >> 16) & 0xfc00) | ((val >> 11) & 0x3e0)
- | ((val >> 21) & 0x1f);
- }
- else
- {
- insn = val & 0xffff;
- extend = val >> 16;
- }
+ second = val & 0xffff;
+ first = val >> 16;
+ }
+ else if (r_type != R_MIPS16_26)
+ {
+ second = ((val >> 11) & 0xffe0) | (val & 0x1f);
+ first = ((val >> 16) & 0xf800) | ((val >> 11) & 0x1f) | (val & 0x7e0);
}
else
{
- insn = ((val >> 11) & 0xffe0) | (val & 0x1f);
- extend = ((val >> 16) & 0xf800) | ((val >> 11) & 0x1f) | (val & 0x7e0);
+ second = val & 0xffff;
+ first = ((val >> 16) & 0xfc00) | ((val >> 11) & 0x3e0)
+ | ((val >> 21) & 0x1f);
}
- bfd_put_16 (abfd, insn, data + 2);
- bfd_put_16 (abfd, extend, data);
+ bfd_put_16 (abfd, second, data + 2);
+ bfd_put_16 (abfd, first, data);
}
bfd_reloc_status_type
if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
return bfd_reloc_outofrange;
- _bfd_mips16_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
- location);
- vallo = bfd_get_32 (abfd, location);
- _bfd_mips16_elf_reloc_shuffle (abfd, reloc_entry->howto->type, FALSE,
+ _bfd_mips_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
location);
+ vallo = bfd_get_32 (abfd, location);
+ _bfd_mips_elf_reloc_shuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
while (mips_hi16_list != NULL)
{
hi->rel.howto = MIPS_ELF_RTYPE_TO_HOWTO (abfd, R_MIPS_HI16, FALSE);
else if (hi->rel.howto->type == R_MIPS16_GOT16)
hi->rel.howto = MIPS_ELF_RTYPE_TO_HOWTO (abfd, R_MIPS16_HI16, FALSE);
+ else if (hi->rel.howto->type == R_MICROMIPS_GOT16)
+ hi->rel.howto = MIPS_ELF_RTYPE_TO_HOWTO (abfd, R_MICROMIPS_HI16, FALSE);
/* VALLO is a signed 16-bit number. Bias it by 0x8000 so that any
carry or borrow will induce a change of +1 or -1 in the high part. */
val += reloc_entry->addend;
/* Add VAL to the relocation field. */
- _bfd_mips16_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
- location);
+ _bfd_mips_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
status = _bfd_relocate_contents (reloc_entry->howto, abfd, val,
location);
- _bfd_mips16_elf_reloc_shuffle (abfd, reloc_entry->howto->type, FALSE,
- location);
+ _bfd_mips_elf_reloc_shuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
if (status != bfd_reloc_ok)
return status;
int r_type, struct bfd_link_info *info,
struct mips_elf_link_hash_entry *h, bfd_vma symbol)
{
- BFD_ASSERT (r_type == R_MIPS_TLS_GOTTPREL || r_type == R_MIPS_TLS_GD
- || r_type == R_MIPS_TLS_LDM);
+ BFD_ASSERT (tls_gottprel_reloc_p (r_type)
+ || tls_gd_reloc_p (r_type)
+ || tls_ldm_reloc_p (r_type));
mips_elf_initialize_tls_slots (abfd, got_index, tls_type, info, h, symbol);
- if (r_type == R_MIPS_TLS_GOTTPREL)
+ if (tls_gottprel_reloc_p (r_type))
{
BFD_ASSERT (*tls_type & GOT_TLS_IE);
if (*tls_type & GOT_TLS_GD)
return got_index;
}
- if (r_type == R_MIPS_TLS_GD)
+ if (tls_gd_reloc_p (r_type))
{
BFD_ASSERT (*tls_type & GOT_TLS_GD);
return got_index;
}
- if (r_type == R_MIPS_TLS_LDM)
+ if (tls_ldm_reloc_p (r_type))
{
BFD_ASSERT (*tls_type & GOT_TLS_LDM);
return got_index;
struct mips_got_entry *p;
entry.abfd = ibfd;
- if (r_type == R_MIPS_TLS_LDM)
+ if (tls_ldm_reloc_p (r_type))
{
entry.tls_type = GOT_TLS_LDM;
entry.symndx = 0;
case R_MIPS_26:
case R_MIPS_PC16:
case R_MIPS16_26:
+ case R_MICROMIPS_26_S1:
+ case R_MICROMIPS_PC7_S1:
+ case R_MICROMIPS_PC10_S1:
+ case R_MICROMIPS_PC16_S1:
+ case R_MICROMIPS_PC23_S2:
return TRUE;
default:
The result of the relocation calculation is stored in VALUEP.
On exit, set *CROSS_MODE_JUMP_P to true if the relocation field
- is a MIPS16 jump to non-MIPS16 code, or vice versa.
+ is a MIPS16 or microMIPS jump to standard MIPS code, or vice versa.
This function returns bfd_reloc_continue if the caller need take no
further action regarding this relocation, bfd_reloc_notsupported if
bfd_boolean overflowed_p;
/* TRUE if this relocation refers to a MIPS16 function. */
bfd_boolean target_is_16_bit_code_p = FALSE;
+ bfd_boolean target_is_micromips_code_p = FALSE;
struct mips_elf_link_hash_table *htab;
bfd *dynobj;
addend += sec->output_section->vma + sec->output_offset;
}
- /* MIPS16 text labels should be treated as odd. */
- if (ELF_ST_IS_MIPS16 (sym->st_other))
+ /* MIPS16/microMIPS text labels should be treated as odd. */
+ if (ELF_ST_IS_COMPRESSED (sym->st_other))
++symbol;
/* Record the name of this symbol, for our caller. */
*namep = bfd_section_name (input_bfd, sec);
target_is_16_bit_code_p = ELF_ST_IS_MIPS16 (sym->st_other);
+ target_is_micromips_code_p = ELF_ST_IS_MICROMIPS (sym->st_other);
}
else
{
}
target_is_16_bit_code_p = ELF_ST_IS_MIPS16 (h->root.other);
+ /* If the output section is the PLT section,
+ then the target is not microMIPS. */
+ target_is_micromips_code_p = (htab->splt != sec
+ && ELF_ST_IS_MICROMIPS (h->root.other));
}
/* If this is a reference to a 16-bit function with a stub, we need
+ h->la25_stub->stub_section->output_offset
+ h->la25_stub->offset);
+ /* Make sure MIPS16 and microMIPS are not used together. */
+ if ((r_type == R_MIPS16_26 && target_is_micromips_code_p)
+ || (micromips_branch_reloc_p (r_type) && target_is_16_bit_code_p))
+ {
+ (*_bfd_error_handler)
+ (_("MIPS16 and microMIPS functions cannot call each other"));
+ return bfd_reloc_notsupported;
+ }
+
/* Calls from 16-bit code to 32-bit code and vice versa require the
- mode change. */
- *cross_mode_jump_p = !info->relocatable
- && ((r_type == R_MIPS16_26 && !target_is_16_bit_code_p)
- || ((r_type == R_MIPS_26 || r_type == R_MIPS_JALR)
- && target_is_16_bit_code_p));
+ mode change. However, we can ignore calls to undefined weak symbols,
+ which should never be executed at runtime. This exception is important
+ because the assembly writer may have "known" that any definition of the
+ symbol would be 16-bit code, and that direct jumps were therefore
+ acceptable. */
+ *cross_mode_jump_p = (!info->relocatable
+ && !(h && h->root.root.type == bfd_link_hash_undefweak)
+ && ((r_type == R_MIPS16_26 && !target_is_16_bit_code_p)
+ || (r_type == R_MICROMIPS_26_S1
+ && !target_is_micromips_code_p)
+ || ((r_type == R_MIPS_26 || r_type == R_MIPS_JALR)
+ && (target_is_16_bit_code_p
+ || target_is_micromips_code_p))));
local_p = h == NULL || SYMBOL_REFERENCES_LOCAL (info, &h->root);
if (gnu_local_gp_p)
symbol = gp;
- /* Global R_MIPS_GOT_PAGE relocations are equivalent to R_MIPS_GOT_DISP.
- The addend is applied by the corresponding R_MIPS_GOT_OFST. */
- if (r_type == R_MIPS_GOT_PAGE && !local_p)
+ /* Global R_MIPS_GOT_PAGE/R_MICROMIPS_GOT_PAGE relocations are equivalent
+ to R_MIPS_GOT_DISP/R_MICROMIPS_GOT_DISP. The addend is applied by the
+ corresponding R_MIPS_GOT_OFST/R_MICROMIPS_GOT_OFST. */
+ if (got_page_reloc_p (r_type) && !local_p)
{
- r_type = R_MIPS_GOT_DISP;
+ r_type = (micromips_reloc_p (r_type)
+ ? R_MICROMIPS_GOT_DISP : R_MIPS_GOT_DISP);
addend = 0;
}
case R_MIPS_CALL_HI16:
case R_MIPS_GOT_LO16:
case R_MIPS_CALL_LO16:
+ case R_MICROMIPS_CALL16:
+ case R_MICROMIPS_GOT16:
+ case R_MICROMIPS_GOT_DISP:
+ case R_MICROMIPS_GOT_HI16:
+ case R_MICROMIPS_CALL_HI16:
+ case R_MICROMIPS_GOT_LO16:
+ case R_MICROMIPS_CALL_LO16:
case R_MIPS_TLS_GD:
case R_MIPS_TLS_GOTTPREL:
case R_MIPS_TLS_LDM:
+ case R_MICROMIPS_TLS_GD:
+ case R_MICROMIPS_TLS_GOTTPREL:
+ case R_MICROMIPS_TLS_LDM:
/* Find the index into the GOT where this value is located. */
- if (r_type == R_MIPS_TLS_LDM)
+ if (tls_ldm_reloc_p (r_type))
{
g = mips_elf_local_got_index (abfd, input_bfd, info,
0, 0, NULL, r_type);
/* On VxWorks, CALL relocations should refer to the .got.plt
entry, which is initialized to point at the PLT stub. */
if (htab->is_vxworks
- && (r_type == R_MIPS_CALL_HI16
- || r_type == R_MIPS_CALL_LO16
+ && (call_hi16_reloc_p (r_type)
+ || call_lo16_reloc_p (r_type)
|| call16_reloc_p (r_type)))
{
BFD_ASSERT (addend == 0);
mips_elf_perform_relocation. So, we just fall through to the
R_MIPS_26 case here. */
case R_MIPS_26:
- if (was_local_p)
- value = ((addend | ((p + 4) & 0xf0000000)) + symbol) >> 2;
- else
- {
- value = (_bfd_mips_elf_sign_extend (addend, 28) + symbol) >> 2;
- if (h->root.root.type != bfd_link_hash_undefweak)
- overflowed_p = (value >> 26) != ((p + 4) >> 28);
- }
- value &= howto->dst_mask;
+ case R_MICROMIPS_26_S1:
+ {
+ unsigned int shift;
+
+ /* Make sure the target of JALX is word-aligned. Bit 0 must be
+ the correct ISA mode selector and bit 1 must be 0. */
+ if (*cross_mode_jump_p && (symbol & 3) != (r_type == R_MIPS_26))
+ return bfd_reloc_outofrange;
+
+ /* Shift is 2, unusually, for microMIPS JALX. */
+ shift = (!*cross_mode_jump_p && r_type == R_MICROMIPS_26_S1) ? 1 : 2;
+
+ if (was_local_p)
+ value = addend | ((p + 4) & (0xfc000000 << shift));
+ else
+ value = _bfd_mips_elf_sign_extend (addend, 26 + shift);
+ value = (value + symbol) >> shift;
+ if (!was_local_p && h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = (value >> 26) != ((p + 4) >> (26 + shift));
+ value &= howto->dst_mask;
+ }
break;
case R_MIPS_TLS_DTPREL_HI16:
+ case R_MICROMIPS_TLS_DTPREL_HI16:
value = (mips_elf_high (addend + symbol - dtprel_base (info))
& howto->dst_mask);
break;
case R_MIPS_TLS_DTPREL_LO16:
case R_MIPS_TLS_DTPREL32:
case R_MIPS_TLS_DTPREL64:
+ case R_MICROMIPS_TLS_DTPREL_LO16:
value = (symbol + addend - dtprel_base (info)) & howto->dst_mask;
break;
case R_MIPS_TLS_TPREL_HI16:
+ case R_MICROMIPS_TLS_TPREL_HI16:
value = (mips_elf_high (addend + symbol - tprel_base (info))
& howto->dst_mask);
break;
case R_MIPS_TLS_TPREL_LO16:
+ case R_MICROMIPS_TLS_TPREL_LO16:
value = (symbol + addend - tprel_base (info)) & howto->dst_mask;
break;
case R_MIPS_HI16:
case R_MIPS16_HI16:
+ case R_MICROMIPS_HI16:
if (!gp_disp_p)
{
value = mips_elf_high (addend + symbol);
both reloc addends by 4. */
if (r_type == R_MIPS16_HI16)
value = mips_elf_high (addend + gp - p - 4);
+ /* The microMIPS .cpload sequence uses the same assembly
+ instructions as the traditional psABI version, but the
+ incoming $t9 has the low bit set. */
+ else if (r_type == R_MICROMIPS_HI16)
+ value = mips_elf_high (addend + gp - p - 1);
else
value = mips_elf_high (addend + gp - p);
overflowed_p = mips_elf_overflow_p (value, 16);
case R_MIPS_LO16:
case R_MIPS16_LO16:
+ case R_MICROMIPS_LO16:
+ case R_MICROMIPS_HI0_LO16:
if (!gp_disp_p)
value = (symbol + addend) & howto->dst_mask;
else
for this conditional. */
if (r_type == R_MIPS16_LO16)
value = addend + gp - p;
+ else if (r_type == R_MICROMIPS_LO16
+ || r_type == R_MICROMIPS_HI0_LO16)
+ value = addend + gp - p + 3;
else
value = addend + gp - p + 4;
/* The MIPS ABI requires checking the R_MIPS_LO16 relocation
break;
case R_MIPS_LITERAL:
+ case R_MICROMIPS_LITERAL:
/* Because we don't merge literal sections, we can handle this
just like R_MIPS_GPREL16. In the long run, we should merge
shared literals, and then we will need to additional work
order. We don't need to do anything special here; the
differences are handled in mips_elf_perform_relocation. */
case R_MIPS_GPREL16:
+ case R_MICROMIPS_GPREL7_S2:
+ case R_MICROMIPS_GPREL16:
/* Only sign-extend the addend if it was extracted from the
instruction. If the addend was separate, leave it alone,
otherwise we may lose significant bits. */
case R_MIPS16_CALL16:
case R_MIPS_GOT16:
case R_MIPS_CALL16:
+ case R_MICROMIPS_GOT16:
+ case R_MICROMIPS_CALL16:
/* VxWorks does not have separate local and global semantics for
R_MIPS*_GOT16; every relocation evaluates to "G". */
if (!htab->is_vxworks && local_p)
case R_MIPS_TLS_GOTTPREL:
case R_MIPS_TLS_LDM:
case R_MIPS_GOT_DISP:
+ case R_MICROMIPS_TLS_GD:
+ case R_MICROMIPS_TLS_GOTTPREL:
+ case R_MICROMIPS_TLS_LDM:
+ case R_MICROMIPS_GOT_DISP:
value = g;
overflowed_p = mips_elf_overflow_p (value, 16);
break;
value &= howto->dst_mask;
break;
+ case R_MICROMIPS_PC7_S1:
+ value = symbol + _bfd_mips_elf_sign_extend (addend, 8) - p;
+ overflowed_p = mips_elf_overflow_p (value, 8);
+ value >>= howto->rightshift;
+ value &= howto->dst_mask;
+ break;
+
+ case R_MICROMIPS_PC10_S1:
+ value = symbol + _bfd_mips_elf_sign_extend (addend, 11) - p;
+ overflowed_p = mips_elf_overflow_p (value, 11);
+ value >>= howto->rightshift;
+ value &= howto->dst_mask;
+ break;
+
+ case R_MICROMIPS_PC16_S1:
+ value = symbol + _bfd_mips_elf_sign_extend (addend, 17) - p;
+ overflowed_p = mips_elf_overflow_p (value, 17);
+ value >>= howto->rightshift;
+ value &= howto->dst_mask;
+ break;
+
+ case R_MICROMIPS_PC23_S2:
+ value = symbol + _bfd_mips_elf_sign_extend (addend, 25) - ((p | 3) ^ 3);
+ overflowed_p = mips_elf_overflow_p (value, 25);
+ value >>= howto->rightshift;
+ value &= howto->dst_mask;
+ break;
+
case R_MIPS_GOT_HI16:
case R_MIPS_CALL_HI16:
+ case R_MICROMIPS_GOT_HI16:
+ case R_MICROMIPS_CALL_HI16:
/* We're allowed to handle these two relocations identically.
The dynamic linker is allowed to handle the CALL relocations
differently by creating a lazy evaluation stub. */
case R_MIPS_GOT_LO16:
case R_MIPS_CALL_LO16:
+ case R_MICROMIPS_GOT_LO16:
+ case R_MICROMIPS_CALL_LO16:
value = g & howto->dst_mask;
break;
case R_MIPS_GOT_PAGE:
+ case R_MICROMIPS_GOT_PAGE:
value = mips_elf_got_page (abfd, input_bfd, info, symbol + addend, NULL);
if (value == MINUS_ONE)
return bfd_reloc_outofrange;
break;
case R_MIPS_GOT_OFST:
+ case R_MICROMIPS_GOT_OFST:
if (local_p)
mips_elf_got_page (abfd, input_bfd, info, symbol + addend, &value);
else
break;
case R_MIPS_SUB:
+ case R_MICROMIPS_SUB:
value = symbol - addend;
value &= howto->dst_mask;
break;
case R_MIPS_HIGHER:
+ case R_MICROMIPS_HIGHER:
value = mips_elf_higher (addend + symbol);
value &= howto->dst_mask;
break;
case R_MIPS_HIGHEST:
+ case R_MICROMIPS_HIGHEST:
value = mips_elf_highest (addend + symbol);
value &= howto->dst_mask;
break;
case R_MIPS_SCN_DISP:
+ case R_MICROMIPS_SCN_DISP:
value = symbol + addend - sec->output_offset;
value &= howto->dst_mask;
break;
case R_MIPS_JALR:
+ case R_MICROMIPS_JALR:
/* This relocation is only a hint. In some cases, we optimize
it into a bal instruction. But we don't try to optimize
when the symbol does not resolve locally. */
appropriate position. The SECTION is the section to which the
relocation applies.
CROSS_MODE_JUMP_P is true if the relocation field
- is a MIPS16 jump to non-MIPS16 code, or vice versa.
+ is a MIPS16 or microMIPS jump to standard MIPS code, or vice versa.
Returns FALSE if anything goes wrong. */
/* Figure out where the relocation is occurring. */
location = contents + relocation->r_offset;
- _bfd_mips16_elf_reloc_unshuffle (input_bfd, r_type, FALSE, location);
+ _bfd_mips_elf_reloc_unshuffle (input_bfd, r_type, FALSE, location);
/* Obtain the current value. */
x = mips_elf_obtain_contents (howto, relocation, input_bfd, contents);
ok = ((opcode == 0x6) || (opcode == 0x7));
jalx_opcode = 0x7;
}
+ else if (r_type == R_MICROMIPS_26_S1)
+ {
+ ok = ((opcode == 0x3d) || (opcode == 0x3c));
+ jalx_opcode = 0x3c;
+ }
else
{
ok = ((opcode == 0x3) || (opcode == 0x1d));
/* Put the value into the output. */
bfd_put (8 * bfd_get_reloc_size (howto), input_bfd, x, location);
- _bfd_mips16_elf_reloc_shuffle(input_bfd, r_type, !info->relocatable,
- location);
+ _bfd_mips_elf_reloc_shuffle (input_bfd, r_type, !info->relocatable,
+ location);
return TRUE;
}
break;
}
- /* If this is an odd-valued function symbol, assume it's a MIPS16 one. */
+ /* If this is an odd-valued function symbol, assume it's a MIPS16
+ or microMIPS one. */
if (ELF_ST_TYPE (elfsym->internal_elf_sym.st_info) == STT_FUNC
&& (asym->value & 1) != 0)
{
asym->value--;
- elfsym->internal_elf_sym.st_other
- = ELF_ST_SET_MIPS16 (elfsym->internal_elf_sym.st_other);
+ if (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS)
+ elfsym->internal_elf_sym.st_other
+ = ELF_ST_SET_MICROMIPS (elfsym->internal_elf_sym.st_other);
+ else
+ elfsym->internal_elf_sym.st_other
+ = ELF_ST_SET_MIPS16 (elfsym->internal_elf_sym.st_other);
}
}
\f
/* If this is a mips16 text symbol, add 1 to the value to make it
odd. This will cause something like .word SYM to come up with
the right value when it is loaded into the PC. */
- if (ELF_ST_IS_MIPS16 (sym->st_other))
+ if (ELF_ST_IS_COMPRESSED (sym->st_other))
++*valp;
return TRUE;
&& strcmp (input_sec->name, ".scommon") == 0)
sym->st_shndx = SHN_MIPS_SCOMMON;
- if (ELF_ST_IS_MIPS16 (sym->st_other))
+ if (ELF_ST_IS_COMPRESSED (sym->st_other))
sym->st_value &= ~1;
return 1;
location = contents + rel->r_offset;
/* Get the addend, which is stored in the input file. */
- _bfd_mips16_elf_reloc_unshuffle (abfd, r_type, FALSE, location);
+ _bfd_mips_elf_reloc_unshuffle (abfd, r_type, FALSE, location);
addend = mips_elf_obtain_contents (howto, rel, abfd, contents);
- _bfd_mips16_elf_reloc_shuffle (abfd, r_type, FALSE, location);
+ _bfd_mips_elf_reloc_shuffle (abfd, r_type, FALSE, location);
return addend & howto->src_mask;
}
r_type = ELF_R_TYPE (abfd, rel->r_info);
if (mips16_reloc_p (r_type))
lo16_type = R_MIPS16_LO16;
+ else if (micromips_reloc_p (r_type))
+ lo16_type = R_MICROMIPS_LO16;
else
lo16_type = R_MIPS_LO16;
case R_MIPS_TLS_GOTTPREL:
case R_MIPS_TLS_GD:
case R_MIPS_TLS_LDM:
+ case R_MICROMIPS_GOT16:
+ case R_MICROMIPS_CALL16:
+ case R_MICROMIPS_CALL_HI16:
+ case R_MICROMIPS_CALL_LO16:
+ case R_MICROMIPS_GOT_HI16:
+ case R_MICROMIPS_GOT_LO16:
+ case R_MICROMIPS_GOT_PAGE:
+ case R_MICROMIPS_GOT_OFST:
+ case R_MICROMIPS_GOT_DISP:
+ case R_MICROMIPS_TLS_GOTTPREL:
+ case R_MICROMIPS_TLS_GD:
+ case R_MICROMIPS_TLS_LDM:
if (dynobj == NULL)
elf_hash_table (info)->dynobj = dynobj = abfd;
if (!mips_elf_create_got_section (dynobj, info))
/* This is just a hint; it can safely be ignored. Don't set
has_static_relocs for the corresponding symbol. */
case R_MIPS_JALR:
+ case R_MICROMIPS_JALR:
break;
case R_MIPS_32:
case R_MIPS_26:
case R_MIPS_PC16:
case R_MIPS16_26:
+ case R_MICROMIPS_26_S1:
+ case R_MICROMIPS_PC7_S1:
+ case R_MICROMIPS_PC10_S1:
+ case R_MICROMIPS_PC16_S1:
+ case R_MICROMIPS_PC23_S2:
if (h)
((struct mips_elf_link_hash_entry *) h)->has_static_relocs = TRUE;
break;
info->flags |= DF_TEXTREL;
}
}
- else if (r_type == R_MIPS_CALL_LO16
- || r_type == R_MIPS_GOT_LO16
- || r_type == R_MIPS_GOT_DISP
+ else if (call_lo16_reloc_p (r_type)
+ || got_lo16_reloc_p (r_type)
+ || got_disp_reloc_p (r_type)
|| (got16_reloc_p (r_type) && htab->is_vxworks))
{
/* We may need a local GOT entry for this relocation. We
{
case R_MIPS_CALL16:
case R_MIPS16_CALL16:
+ case R_MICROMIPS_CALL16:
if (h == NULL)
{
(*_bfd_error_handler)
case R_MIPS_CALL_HI16:
case R_MIPS_CALL_LO16:
+ case R_MICROMIPS_CALL_HI16:
+ case R_MICROMIPS_CALL_LO16:
if (h != NULL)
{
/* Make sure there is room in the regular GOT to hold the
break;
case R_MIPS_GOT_PAGE:
+ case R_MICROMIPS_GOT_PAGE:
/* If this is a global, overridable symbol, GOT_PAGE will
decay to GOT_DISP, so we'll need a GOT entry for it. */
if (h)
case R_MIPS_GOT16:
case R_MIPS_GOT_HI16:
case R_MIPS_GOT_LO16:
- if (!h || r_type == R_MIPS_GOT_PAGE)
+ case R_MICROMIPS_GOT16:
+ case R_MICROMIPS_GOT_HI16:
+ case R_MICROMIPS_GOT_LO16:
+ if (!h || got_page_reloc_p (r_type))
{
/* This relocation needs (or may need, if h != NULL) a
page entry in the GOT. For R_MIPS_GOT_PAGE we do not
/* Fall through. */
case R_MIPS_GOT_DISP:
+ case R_MICROMIPS_GOT_DISP:
if (h && !mips_elf_record_global_got_symbol (h, abfd, info,
FALSE, 0))
return FALSE;
break;
case R_MIPS_TLS_GOTTPREL:
+ case R_MICROMIPS_TLS_GOTTPREL:
if (info->shared)
info->flags |= DF_STATIC_TLS;
/* Fall through */
case R_MIPS_TLS_LDM:
- if (r_type == R_MIPS_TLS_LDM)
+ case R_MICROMIPS_TLS_LDM:
+ if (tls_ldm_reloc_p (r_type))
{
r_symndx = STN_UNDEF;
h = NULL;
/* Fall through */
case R_MIPS_TLS_GD:
+ case R_MICROMIPS_TLS_GD:
/* This symbol requires a global offset table entry, or two
for TLS GD relocations. */
{
- unsigned char flag = (r_type == R_MIPS_TLS_GD
- ? GOT_TLS_GD
- : r_type == R_MIPS_TLS_LDM
- ? GOT_TLS_LDM
- : GOT_TLS_IE);
+ unsigned char flag;
+
+ flag = (tls_gd_reloc_p (r_type)
+ ? GOT_TLS_GD
+ : tls_ldm_reloc_p (r_type) ? GOT_TLS_LDM : GOT_TLS_IE);
if (h != NULL)
{
struct mips_elf_link_hash_entry *hmips =
case R_MIPS_GPREL16:
case R_MIPS_LITERAL:
case R_MIPS_GPREL32:
+ case R_MICROMIPS_26_S1:
+ case R_MICROMIPS_GPREL16:
+ case R_MICROMIPS_LITERAL:
+ case R_MICROMIPS_GPREL7_S2:
if (SGI_COMPAT (abfd))
mips_elf_hash_table (info)->compact_rel_size +=
sizeof (Elf32_External_crinfo);
case R_MIPS_CALL_HI16:
case R_MIPS_CALL_LO16:
case R_MIPS_JALR:
+ case R_MICROMIPS_CALL16:
+ case R_MICROMIPS_CALL_HI16:
+ case R_MICROMIPS_CALL_LO16:
+ case R_MICROMIPS_JALR:
break;
}
case R_MIPS_HI16:
case R_MIPS_HIGHER:
case R_MIPS_HIGHEST:
+ case R_MICROMIPS_HI16:
+ case R_MICROMIPS_HIGHER:
+ case R_MICROMIPS_HIGHEST:
/* Don't refuse a high part relocation if it's against
no symbol (e.g. part of a compound relocation). */
if (r_symndx == STN_UNDEF)
case R_MIPS16_26:
case R_MIPS_26:
+ case R_MICROMIPS_26_S1:
howto = MIPS_ELF_RTYPE_TO_HOWTO (abfd, r_type, FALSE);
(*_bfd_error_handler)
(_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
if (mips_elf_local_relocation_p (input_bfd, rel, local_sections))
{
r_type = ELF_R_TYPE (output_bfd, rel->r_info);
- if (r_type == R_MIPS16_GPREL
- || r_type == R_MIPS_GPREL16
+ if (gprel16_reloc_p (r_type)
|| r_type == R_MIPS_GPREL32
- || r_type == R_MIPS_LITERAL)
+ || literal_reloc_p (r_type))
{
rel->r_addend += _bfd_get_gp_value (input_bfd);
rel->r_addend -= _bfd_get_gp_value (output_bfd);
BFD_ASSERT (name != NULL);
if (!htab->small_data_overflow_reported
&& (gprel16_reloc_p (howto->type)
- || howto->type == R_MIPS_LITERAL))
+ || literal_reloc_p (howto->type)))
{
msg = _("small-data section exceeds 64KB;"
" lower small-data size limit (see option -G)");
case bfd_reloc_ok:
break;
+ case bfd_reloc_outofrange:
+ if (jal_reloc_p (howto->type))
+ {
+ msg = _("JALX to a non-word-aligned address");
+ info->callbacks->warning
+ (info, msg, name, input_bfd, input_section, rel->r_offset);
+ return FALSE;
+ }
+ /* Fall through. */
+
default:
abort ();
break;
if (stub->stub_section != htab->strampoline)
{
- /* This is a simple LUI/ADIDU stub. Zero out the beginning
+ /* This is a simple LUI/ADDIU stub. Zero out the beginning
of the section and write the two instructions at the end. */
memset (loc, 0, offset);
loc += offset;
- bfd_put_32 (hti->output_bfd, LA25_LUI (target_high), loc);
- bfd_put_32 (hti->output_bfd, LA25_ADDIU (target_low), loc + 4);
+ if (ELF_ST_IS_MICROMIPS (stub->h->root.other))
+ {
+ bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_1 (target_high),
+ loc);
+ bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_2 (target_high),
+ loc + 2);
+ bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_1 (target_low),
+ loc + 4);
+ bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_2 (target_low),
+ loc + 6);
+ }
+ else
+ {
+ bfd_put_32 (hti->output_bfd, LA25_LUI (target_high), loc);
+ bfd_put_32 (hti->output_bfd, LA25_ADDIU (target_low), loc + 4);
+ }
}
else
{
/* This is trampoline. */
loc += offset;
- bfd_put_32 (hti->output_bfd, LA25_LUI (target_high), loc);
- bfd_put_32 (hti->output_bfd, LA25_J (target), loc + 4);
- bfd_put_32 (hti->output_bfd, LA25_ADDIU (target_low), loc + 8);
- bfd_put_32 (hti->output_bfd, 0, loc + 12);
+ if (ELF_ST_IS_MICROMIPS (stub->h->root.other))
+ {
+ bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_1 (target_high),
+ loc);
+ bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_2 (target_high),
+ loc + 2);
+ bfd_put_16 (hti->output_bfd, LA25_J_MICROMIPS_1 (target), loc + 4);
+ bfd_put_16 (hti->output_bfd, LA25_J_MICROMIPS_2 (target), loc + 6);
+ bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_1 (target_low),
+ loc + 8);
+ bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_2 (target_low),
+ loc + 10);
+ bfd_put_32 (hti->output_bfd, 0, loc + 12);
+ }
+ else
+ {
+ bfd_put_32 (hti->output_bfd, LA25_LUI (target_high), loc);
+ bfd_put_32 (hti->output_bfd, LA25_J (target), loc + 4);
+ bfd_put_32 (hti->output_bfd, LA25_ADDIU (target_low), loc + 8);
+ bfd_put_32 (hti->output_bfd, 0, loc + 12);
+ }
}
return TRUE;
}
++htab->srelbss->reloc_count;
}
- /* If this is a mips16 symbol, force the value to be even. */
- if (ELF_ST_IS_MIPS16 (sym->st_other))
+ /* If this is a mips16/microMIPS symbol, force the value to be even. */
+ if (ELF_ST_IS_COMPRESSED (sym->st_other))
sym->st_value &= ~1;
return TRUE;
case R_MIPS_GOT_DISP:
case R_MIPS_GOT_PAGE:
case R_MIPS_GOT_OFST:
+ case R_MICROMIPS_GOT16:
+ case R_MICROMIPS_CALL16:
+ case R_MICROMIPS_CALL_HI16:
+ case R_MICROMIPS_CALL_LO16:
+ case R_MICROMIPS_GOT_HI16:
+ case R_MICROMIPS_GOT_LO16:
+ case R_MICROMIPS_GOT_DISP:
+ case R_MICROMIPS_GOT_PAGE:
+ case R_MICROMIPS_GOT_OFST:
/* ??? It would seem that the existing MIPS code does no sort
of reference counting or whatnot on its GOT and PLT entries,
so it is not possible to garbage collect them at this time. */
return TRUE;
}
\f
+/* microMIPS code retains local labels for linker relaxation. Omit them
+ from output by default for clarity. */
+
+bfd_boolean
+_bfd_mips_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
+{
+ return _bfd_elf_is_local_label_name (abfd, sym->name);
+}
+
/* MIPS ELF uses a special find_nearest_line routine in order the
handle the ECOFF debugging information. */
return NULL;
}
\f
+static bfd_boolean
+mips_elf_relax_delete_bytes (bfd *abfd,
+ asection *sec, bfd_vma addr, int count)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ unsigned int sec_shndx;
+ bfd_byte *contents;
+ Elf_Internal_Rela *irel, *irelend;
+ Elf_Internal_Sym *isym;
+ Elf_Internal_Sym *isymend;
+ struct elf_link_hash_entry **sym_hashes;
+ struct elf_link_hash_entry **end_hashes;
+ struct elf_link_hash_entry **start_hashes;
+ unsigned int symcount;
+
+ sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
+ contents = elf_section_data (sec)->this_hdr.contents;
+
+ irel = elf_section_data (sec)->relocs;
+ irelend = irel + sec->reloc_count;
+
+ /* Actually delete the bytes. */
+ memmove (contents + addr, contents + addr + count,
+ (size_t) (sec->size - addr - count));
+ sec->size -= count;
+
+ /* Adjust all the relocs. */
+ for (irel = elf_section_data (sec)->relocs; irel < irelend; irel++)
+ {
+ /* Get the new reloc address. */
+ if (irel->r_offset > addr)
+ irel->r_offset -= count;
+ }
+
+ BFD_ASSERT (addr % 2 == 0);
+ BFD_ASSERT (count % 2 == 0);
+
+ /* Adjust the local symbols defined in this section. */
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ isym = (Elf_Internal_Sym *) symtab_hdr->contents;
+ for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
+ if (isym->st_shndx == sec_shndx
+ && isym->st_value > addr)
+ isym->st_value -= count;
+
+ /* Now adjust the global symbols defined in this section. */
+ symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
+ - symtab_hdr->sh_info);
+ sym_hashes = start_hashes = elf_sym_hashes (abfd);
+ end_hashes = sym_hashes + symcount;
+
+ for (; sym_hashes < end_hashes; sym_hashes++)
+ {
+ struct elf_link_hash_entry *sym_hash = *sym_hashes;
+
+ if ((sym_hash->root.type == bfd_link_hash_defined
+ || sym_hash->root.type == bfd_link_hash_defweak)
+ && sym_hash->root.u.def.section == sec)
+ {
+ bfd_vma value;
+
+ value = sym_hash->root.u.def.value;
+ if (ELF_ST_IS_MICROMIPS (sym_hash->other))
+ value &= MINUS_TWO;
+ if (value > addr)
+ sym_hash->root.u.def.value -= count;
+ }
+ }
+
+ return TRUE;
+}
+
+
+/* Opcodes needed for microMIPS relaxation as found in
+ opcodes/micromips-opc.c. */
+
+struct opcode_descriptor {
+ unsigned long match;
+ unsigned long mask;
+};
+
+/* The $ra register aka $31. */
+
+#define RA 31
+
+/* 32-bit instruction format register fields. */
+
+#define OP32_SREG(opcode) (((opcode) >> 16) & 0x1f)
+#define OP32_TREG(opcode) (((opcode) >> 21) & 0x1f)
+
+/* Check if a 5-bit register index can be abbreviated to 3 bits. */
+
+#define OP16_VALID_REG(r) \
+ ((2 <= (r) && (r) <= 7) || (16 <= (r) && (r) <= 17))
+
+
+/* 32-bit and 16-bit branches. */
+
+static const struct opcode_descriptor b_insns_32[] = {
+ { /* "b", "p", */ 0x40400000, 0xffff0000 }, /* bgez 0 */
+ { /* "b", "p", */ 0x94000000, 0xffff0000 }, /* beq 0, 0 */
+ { 0, 0 } /* End marker for find_match(). */
+};
+
+static const struct opcode_descriptor bc_insn_32 =
+ { /* "bc(1|2)(ft)", "N,p", */ 0x42800000, 0xfec30000 };
+
+static const struct opcode_descriptor bz_insn_32 =
+ { /* "b(g|l)(e|t)z", "s,p", */ 0x40000000, 0xff200000 };
+
+static const struct opcode_descriptor bzal_insn_32 =
+ { /* "b(ge|lt)zal", "s,p", */ 0x40200000, 0xffa00000 };
+
+static const struct opcode_descriptor beq_insn_32 =
+ { /* "b(eq|ne)", "s,t,p", */ 0x94000000, 0xdc000000 };
+
+static const struct opcode_descriptor b_insn_16 =
+ { /* "b", "mD", */ 0xcc00, 0xfc00 };
+
+static const struct opcode_descriptor bz_insn_16 =
+ { /* "b(eq|ne)z", "md,mE", */ 0x8c00, 0xac00 };
+
+
+/* 32-bit and 16-bit branch EQ and NE zero. */
+
+/* NOTE: All opcode tables have BEQ/BNE in the same order: first the
+ eq and second the ne. This convention is used when replacing a
+ 32-bit BEQ/BNE with the 16-bit version. */
+
+#define BZC32_REG_FIELD(r) (((r) & 0x1f) << 16)
+
+static const struct opcode_descriptor bz_rs_insns_32[] = {
+ { /* "beqz", "s,p", */ 0x94000000, 0xffe00000 },
+ { /* "bnez", "s,p", */ 0xb4000000, 0xffe00000 },
+ { 0, 0 } /* End marker for find_match(). */
+};
+
+static const struct opcode_descriptor bz_rt_insns_32[] = {
+ { /* "beqz", "t,p", */ 0x94000000, 0xfc01f000 },
+ { /* "bnez", "t,p", */ 0xb4000000, 0xfc01f000 },
+ { 0, 0 } /* End marker for find_match(). */
+};
+
+static const struct opcode_descriptor bzc_insns_32[] = {
+ { /* "beqzc", "s,p", */ 0x40e00000, 0xffe00000 },
+ { /* "bnezc", "s,p", */ 0x40a00000, 0xffe00000 },
+ { 0, 0 } /* End marker for find_match(). */
+};
+
+static const struct opcode_descriptor bz_insns_16[] = {
+ { /* "beqz", "md,mE", */ 0x8c00, 0xfc00 },
+ { /* "bnez", "md,mE", */ 0xac00, 0xfc00 },
+ { 0, 0 } /* End marker for find_match(). */
+};
+
+/* Switch between a 5-bit register index and its 3-bit shorthand. */
+
+#define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0x17) + 2)
+#define BZ16_REG_FIELD(r) \
+ (((2 <= (r) && (r) <= 7) ? (r) : ((r) - 16)) << 7)
+
+
+/* 32-bit instructions with a delay slot. */
+
+static const struct opcode_descriptor jal_insn_32_bd16 =
+ { /* "jals", "a", */ 0x74000000, 0xfc000000 };
+
+static const struct opcode_descriptor jal_insn_32_bd32 =
+ { /* "jal", "a", */ 0xf4000000, 0xfc000000 };
+
+static const struct opcode_descriptor jal_x_insn_32_bd32 =
+ { /* "jal[x]", "a", */ 0xf0000000, 0xf8000000 };
+
+static const struct opcode_descriptor j_insn_32 =
+ { /* "j", "a", */ 0xd4000000, 0xfc000000 };
+
+static const struct opcode_descriptor jalr_insn_32 =
+ { /* "jalr[.hb]", "t,s", */ 0x00000f3c, 0xfc00efff };
+
+/* This table can be compacted, because no opcode replacement is made. */
+
+static const struct opcode_descriptor ds_insns_32_bd16[] = {
+ { /* "jals", "a", */ 0x74000000, 0xfc000000 },
+
+ { /* "jalrs[.hb]", "t,s", */ 0x00004f3c, 0xfc00efff },
+ { /* "b(ge|lt)zals", "s,p", */ 0x42200000, 0xffa00000 },
+
+ { /* "b(g|l)(e|t)z", "s,p", */ 0x40000000, 0xff200000 },
+ { /* "b(eq|ne)", "s,t,p", */ 0x94000000, 0xdc000000 },
+ { /* "j", "a", */ 0xd4000000, 0xfc000000 },
+ { 0, 0 } /* End marker for find_match(). */
+};
+
+/* This table can be compacted, because no opcode replacement is made. */
+
+static const struct opcode_descriptor ds_insns_32_bd32[] = {
+ { /* "jal[x]", "a", */ 0xf0000000, 0xf8000000 },
+
+ { /* "jalr[.hb]", "t,s", */ 0x00000f3c, 0xfc00efff },
+ { /* "b(ge|lt)zal", "s,p", */ 0x40200000, 0xffa00000 },
+ { 0, 0 } /* End marker for find_match(). */
+};
+
+
+/* 16-bit instructions with a delay slot. */
+
+static const struct opcode_descriptor jalr_insn_16_bd16 =
+ { /* "jalrs", "my,mj", */ 0x45e0, 0xffe0 };
+
+static const struct opcode_descriptor jalr_insn_16_bd32 =
+ { /* "jalr", "my,mj", */ 0x45c0, 0xffe0 };
+
+static const struct opcode_descriptor jr_insn_16 =
+ { /* "jr", "mj", */ 0x4580, 0xffe0 };
+
+#define JR16_REG(opcode) ((opcode) & 0x1f)
+
+/* This table can be compacted, because no opcode replacement is made. */
+
+static const struct opcode_descriptor ds_insns_16_bd16[] = {
+ { /* "jalrs", "my,mj", */ 0x45e0, 0xffe0 },
+
+ { /* "b", "mD", */ 0xcc00, 0xfc00 },
+ { /* "b(eq|ne)z", "md,mE", */ 0x8c00, 0xdc00 },
+ { /* "jr", "mj", */ 0x4580, 0xffe0 },
+ { 0, 0 } /* End marker for find_match(). */
+};
+
+
+/* LUI instruction. */
+
+static const struct opcode_descriptor lui_insn =
+ { /* "lui", "s,u", */ 0x41a00000, 0xffe00000 };
+
+
+/* ADDIU instruction. */
+
+static const struct opcode_descriptor addiu_insn =
+ { /* "addiu", "t,r,j", */ 0x30000000, 0xfc000000 };
+
+static const struct opcode_descriptor addiupc_insn =
+ { /* "addiu", "mb,$pc,mQ", */ 0x78000000, 0xfc000000 };
+
+#define ADDIUPC_REG_FIELD(r) \
+ (((2 <= (r) && (r) <= 7) ? (r) : ((r) - 16)) << 23)
+
+
+/* Relaxable instructions in a JAL delay slot: MOVE. */
+
+/* The 16-bit move has rd in 9:5 and rs in 4:0. The 32-bit moves
+ (ADDU, OR) have rd in 15:11 and rs in 10:16. */
+#define MOVE32_RD(opcode) (((opcode) >> 11) & 0x1f)
+#define MOVE32_RS(opcode) (((opcode) >> 16) & 0x1f)
+
+#define MOVE16_RD_FIELD(r) (((r) & 0x1f) << 5)
+#define MOVE16_RS_FIELD(r) (((r) & 0x1f) )
+
+static const struct opcode_descriptor move_insns_32[] = {
+ { /* "move", "d,s", */ 0x00000150, 0xffe007ff }, /* addu d,s,$0 */
+ { /* "move", "d,s", */ 0x00000290, 0xffe007ff }, /* or d,s,$0 */
+ { 0, 0 } /* End marker for find_match(). */
+};
+
+static const struct opcode_descriptor move_insn_16 =
+ { /* "move", "mp,mj", */ 0x0c00, 0xfc00 };
+
+
+/* NOP instructions. */
+
+static const struct opcode_descriptor nop_insn_32 =
+ { /* "nop", "", */ 0x00000000, 0xffffffff };
+
+static const struct opcode_descriptor nop_insn_16 =
+ { /* "nop", "", */ 0x0c00, 0xffff };
+
+
+/* Instruction match support. */
+
+#define MATCH(opcode, insn) ((opcode & insn.mask) == insn.match)
+
+static int
+find_match (unsigned long opcode, const struct opcode_descriptor insn[])
+{
+ unsigned long indx;
+
+ for (indx = 0; insn[indx].mask != 0; indx++)
+ if (MATCH (opcode, insn[indx]))
+ return indx;
+
+ return -1;
+}
+
+
+/* Branch and delay slot decoding support. */
+
+/* If PTR points to what *might* be a 16-bit branch or jump, then
+ return the minimum length of its delay slot, otherwise return 0.
+ Non-zero results are not definitive as we might be checking against
+ the second half of another instruction. */
+
+static int
+check_br16_dslot (bfd *abfd, bfd_byte *ptr)
+{
+ unsigned long opcode;
+ int bdsize;
+
+ opcode = bfd_get_16 (abfd, ptr);
+ if (MATCH (opcode, jalr_insn_16_bd32) != 0)
+ /* 16-bit branch/jump with a 32-bit delay slot. */
+ bdsize = 4;
+ else if (MATCH (opcode, jalr_insn_16_bd16) != 0
+ || find_match (opcode, ds_insns_16_bd16) >= 0)
+ /* 16-bit branch/jump with a 16-bit delay slot. */
+ bdsize = 2;
+ else
+ /* No delay slot. */
+ bdsize = 0;
+
+ return bdsize;
+}
+
+/* If PTR points to what *might* be a 32-bit branch or jump, then
+ return the minimum length of its delay slot, otherwise return 0.
+ Non-zero results are not definitive as we might be checking against
+ the second half of another instruction. */
+
+static int
+check_br32_dslot (bfd *abfd, bfd_byte *ptr)
+{
+ unsigned long opcode;
+ int bdsize;
+
+ opcode = (bfd_get_16 (abfd, ptr) << 16) | bfd_get_16 (abfd, ptr + 2);
+ if (find_match (opcode, ds_insns_32_bd32) >= 0)
+ /* 32-bit branch/jump with a 32-bit delay slot. */
+ bdsize = 4;
+ else if (find_match (opcode, ds_insns_32_bd16) >= 0)
+ /* 32-bit branch/jump with a 16-bit delay slot. */
+ bdsize = 2;
+ else
+ /* No delay slot. */
+ bdsize = 0;
+
+ return bdsize;
+}
+
+/* If PTR points to a 16-bit branch or jump with a 32-bit delay slot
+ that doesn't fiddle with REG, then return TRUE, otherwise FALSE. */
+
+static bfd_boolean
+check_br16 (bfd *abfd, bfd_byte *ptr, unsigned long reg)
+{
+ unsigned long opcode;
+
+ opcode = bfd_get_16 (abfd, ptr);
+ if (MATCH (opcode, b_insn_16)
+ /* B16 */
+ || (MATCH (opcode, jr_insn_16) && reg != JR16_REG (opcode))
+ /* JR16 */
+ || (MATCH (opcode, bz_insn_16) && reg != BZ16_REG (opcode))
+ /* BEQZ16, BNEZ16 */
+ || (MATCH (opcode, jalr_insn_16_bd32)
+ /* JALR16 */
+ && reg != JR16_REG (opcode) && reg != RA))
+ return TRUE;
+
+ return FALSE;
+}
+
+/* If PTR points to a 32-bit branch or jump that doesn't fiddle with REG,
+ then return TRUE, otherwise FALSE. */
+
+static int
+check_br32 (bfd *abfd, bfd_byte *ptr, unsigned long reg)
+{
+ unsigned long opcode;
+
+ opcode = (bfd_get_16 (abfd, ptr) << 16) | bfd_get_16 (abfd, ptr + 2);
+ if (MATCH (opcode, j_insn_32)
+ /* J */
+ || MATCH (opcode, bc_insn_32)
+ /* BC1F, BC1T, BC2F, BC2T */
+ || (MATCH (opcode, jal_x_insn_32_bd32) && reg != RA)
+ /* JAL, JALX */
+ || (MATCH (opcode, bz_insn_32) && reg != OP32_SREG (opcode))
+ /* BGEZ, BGTZ, BLEZ, BLTZ */
+ || (MATCH (opcode, bzal_insn_32)
+ /* BGEZAL, BLTZAL */
+ && reg != OP32_SREG (opcode) && reg != RA)
+ || ((MATCH (opcode, jalr_insn_32) || MATCH (opcode, beq_insn_32))
+ /* JALR, JALR.HB, BEQ, BNE */
+ && reg != OP32_SREG (opcode) && reg != OP32_TREG (opcode)))
+ return TRUE;
+
+ return FALSE;
+}
+
+/* Bitsize checking. */
+#define IS_BITSIZE(val, N) \
+ (((((val) & ((1ULL << (N)) - 1)) ^ (1ULL << ((N) - 1))) \
+ - (1ULL << ((N) - 1))) == (val))
+
+/* See if relocations [INTERNAL_RELOCS, IRELEND) confirm that there
+ is a 4-byte branch at offset OFFSET. */
+
+static bfd_boolean
+check_4byte_branch (Elf_Internal_Rela *internal_relocs,
+ Elf_Internal_Rela *irelend, bfd_vma offset)
+{
+ Elf_Internal_Rela *irel;
+ unsigned long r_type;
+
+ for (irel = internal_relocs; irel < irelend; irel++)
+ if (irel->r_offset == offset)
+ {
+ r_type = ELF32_R_TYPE (irel->r_info);
+ if (r_type == R_MICROMIPS_26_S1
+ || r_type == R_MICROMIPS_PC16_S1
+ || r_type == R_MICROMIPS_JALR)
+ return TRUE;
+ }
+ return FALSE;
+}
+\f
+bfd_boolean
+_bfd_mips_elf_relax_section (bfd *abfd, asection *sec,
+ struct bfd_link_info *link_info,
+ bfd_boolean *again)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ Elf_Internal_Rela *internal_relocs;
+ Elf_Internal_Rela *irel, *irelend;
+ bfd_byte *contents = NULL;
+ Elf_Internal_Sym *isymbuf = NULL;
+
+ /* Assume nothing changes. */
+ *again = FALSE;
+
+ /* We don't have to do anything for a relocatable link, if
+ this section does not have relocs, or if this is not a
+ code section. */
+
+ if (link_info->relocatable
+ || (sec->flags & SEC_RELOC) == 0
+ || sec->reloc_count == 0
+ || (sec->flags & SEC_CODE) == 0)
+ return TRUE;
+
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+
+ /* Get a copy of the native relocations. */
+ internal_relocs = (_bfd_elf_link_read_relocs
+ (abfd, sec, (PTR) NULL, (Elf_Internal_Rela *) NULL,
+ link_info->keep_memory));
+ if (internal_relocs == NULL)
+ goto error_return;
+
+ /* Walk through them looking for relaxing opportunities. */
+ irelend = internal_relocs + sec->reloc_count;
+ for (irel = internal_relocs; irel < irelend; irel++)
+ {
+ unsigned long r_symndx = ELF32_R_SYM (irel->r_info);
+ unsigned int r_type = ELF32_R_TYPE (irel->r_info);
+ bfd_boolean target_is_micromips_code_p;
+ unsigned long opcode;
+ bfd_vma symval;
+ bfd_vma pcrval;
+ int fndopc;
+
+ /* The number of bytes to delete for relaxation and from where
+ to delete these bytes starting at irel->r_offset. */
+ int delcnt = 0;
+ int deloff = 0;
+
+ /* If this isn't something that can be relaxed, then ignore
+ this reloc. */
+ if (r_type != R_MICROMIPS_HI16
+ && r_type != R_MICROMIPS_PC16_S1
+ && r_type != R_MICROMIPS_26_S1
+ && r_type != R_MICROMIPS_GPREL16)
+ continue;
+
+ /* Get the section contents if we haven't done so already. */
+ if (contents == NULL)
+ {
+ /* Get cached copy if it exists. */
+ if (elf_section_data (sec)->this_hdr.contents != NULL)
+ contents = elf_section_data (sec)->this_hdr.contents;
+ /* Go get them off disk. */
+ else if (!bfd_malloc_and_get_section (abfd, sec, &contents))
+ goto error_return;
+ }
+
+ /* Read this BFD's local symbols if we haven't done so already. */
+ if (isymbuf == NULL && symtab_hdr->sh_info != 0)
+ {
+ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
+ if (isymbuf == NULL)
+ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
+ symtab_hdr->sh_info, 0,
+ NULL, NULL, NULL);
+ if (isymbuf == NULL)
+ goto error_return;
+ }
+
+ /* Get the value of the symbol referred to by the reloc. */
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ /* A local symbol. */
+ Elf_Internal_Sym *isym;
+ asection *sym_sec;
+
+ isym = isymbuf + r_symndx;
+ if (isym->st_shndx == SHN_UNDEF)
+ sym_sec = bfd_und_section_ptr;
+ else if (isym->st_shndx == SHN_ABS)
+ sym_sec = bfd_abs_section_ptr;
+ else if (isym->st_shndx == SHN_COMMON)
+ sym_sec = bfd_com_section_ptr;
+ else
+ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
+ symval = (isym->st_value
+ + sym_sec->output_section->vma
+ + sym_sec->output_offset);
+ target_is_micromips_code_p = ELF_ST_IS_MICROMIPS (isym->st_other);
+ }
+ else
+ {
+ unsigned long indx;
+ struct elf_link_hash_entry *h;
+
+ /* An external symbol. */
+ indx = r_symndx - symtab_hdr->sh_info;
+ h = elf_sym_hashes (abfd)[indx];
+ BFD_ASSERT (h != NULL);
+
+ if (h->root.type != bfd_link_hash_defined
+ && h->root.type != bfd_link_hash_defweak)
+ /* This appears to be a reference to an undefined
+ symbol. Just ignore it -- it will be caught by the
+ regular reloc processing. */
+ continue;
+
+ symval = (h->root.u.def.value
+ + h->root.u.def.section->output_section->vma
+ + h->root.u.def.section->output_offset);
+ target_is_micromips_code_p = (!h->needs_plt
+ && ELF_ST_IS_MICROMIPS (h->other));
+ }
+
+
+ /* For simplicity of coding, we are going to modify the
+ section contents, the section relocs, and the BFD symbol
+ table. We must tell the rest of the code not to free up this
+ information. It would be possible to instead create a table
+ of changes which have to be made, as is done in coff-mips.c;
+ that would be more work, but would require less memory when
+ the linker is run. */
+
+ /* Only 32-bit instructions relaxed. */
+ if (irel->r_offset + 4 > sec->size)
+ continue;
+
+ opcode = bfd_get_16 (abfd, contents + irel->r_offset ) << 16;
+ opcode |= bfd_get_16 (abfd, contents + irel->r_offset + 2);
+
+ /* This is the pc-relative distance from the instruction the
+ relocation is applied to, to the symbol referred. */
+ pcrval = (symval
+ - (sec->output_section->vma + sec->output_offset)
+ - irel->r_offset);
+
+ /* R_MICROMIPS_HI16 / LUI relaxation to nil, performing relaxation
+ of corresponding R_MICROMIPS_LO16 to R_MICROMIPS_HI0_LO16 or
+ R_MICROMIPS_PC23_S2. The R_MICROMIPS_PC23_S2 condition is
+
+ (symval % 4 == 0 && IS_BITSIZE (pcrval, 25))
+
+ where pcrval has first to be adjusted to apply against the LO16
+ location (we make the adjustment later on, when we have figured
+ out the offset). */
+ if (r_type == R_MICROMIPS_HI16 && MATCH (opcode, lui_insn))
+ {
+ unsigned long nextopc;
+ unsigned long reg;
+ bfd_vma offset;
+
+ /* Give up if the previous reloc was a HI16 against this symbol
+ too. */
+ if (irel > internal_relocs
+ && ELF32_R_TYPE (irel[-1].r_info) == R_MICROMIPS_HI16
+ && ELF32_R_SYM (irel[-1].r_info) == r_symndx)
+ continue;
+
+ /* Or if the next reloc is not a LO16 against this symbol. */
+ if (irel + 1 >= irelend
+ || ELF32_R_TYPE (irel[1].r_info) != R_MICROMIPS_LO16
+ || ELF32_R_SYM (irel[1].r_info) != r_symndx)
+ continue;
+
+ /* Or if the second next reloc is a LO16 against this symbol too. */
+ if (irel + 2 >= irelend
+ && ELF32_R_TYPE (irel[2].r_info) == R_MICROMIPS_LO16
+ && ELF32_R_SYM (irel[2].r_info) == r_symndx)
+ continue;
+
+ /* See if the LUI instruction *might* be in a branch delay slot. */
+ if (irel->r_offset >= 2
+ && check_br16_dslot (abfd, contents + irel->r_offset - 2) > 0
+ && !(irel->r_offset >= 4
+ /* If the instruction is actually a 4-byte branch,
+ the value of check_br16_dslot doesn't matter.
+ We should use check_br32_dslot to check whether
+ the branch has a delay slot. */
+ && check_4byte_branch (internal_relocs, irelend,
+ irel->r_offset - 4)))
+ continue;
+ if (irel->r_offset >= 4
+ && check_br32_dslot (abfd, contents + irel->r_offset - 4) > 0)
+ continue;
+
+ reg = OP32_SREG (opcode);
+
+ /* We only relax adjacent instructions or ones separated with
+ a branch or jump that has a delay slot. The branch or jump
+ must not fiddle with the register used to hold the address.
+ Subtract 4 for the LUI itself. */
+ offset = irel[1].r_offset - irel[0].r_offset;
+ switch (offset - 4)
+ {
+ case 0:
+ break;
+ case 2:
+ if (check_br16 (abfd, contents + irel->r_offset + 4, reg))
+ break;
+ continue;
+ case 4:
+ if (check_br32 (abfd, contents + irel->r_offset + 4, reg))
+ break;
+ continue;
+ default:
+ continue;
+ }
+
+ nextopc = bfd_get_16 (abfd, contents + irel[1].r_offset ) << 16;
+ nextopc |= bfd_get_16 (abfd, contents + irel[1].r_offset + 2);
+
+ /* Give up unless the same register is used with both
+ relocations. */
+ if (OP32_SREG (nextopc) != reg)
+ continue;
+
+ /* Now adjust pcrval, subtracting the offset to the LO16 reloc
+ and rounding up to take masking of the two LSBs into account. */
+ pcrval = ((pcrval - offset + 3) | 3) ^ 3;
+
+ /* R_MICROMIPS_LO16 relaxation to R_MICROMIPS_HI0_LO16. */
+ if (IS_BITSIZE (symval, 16))
+ {
+ /* Fix the relocation's type. */
+ irel[1].r_info = ELF32_R_INFO (r_symndx, R_MICROMIPS_HI0_LO16);
+
+ /* Instructions using R_MICROMIPS_LO16 have the base or
+ source register in bits 20:16. This register becomes $0
+ (zero) as the result of the R_MICROMIPS_HI16 being 0. */
+ nextopc &= ~0x001f0000;
+ bfd_put_16 (abfd, (nextopc >> 16) & 0xffff,
+ contents + irel[1].r_offset);
+ }
+
+ /* R_MICROMIPS_LO16 / ADDIU relaxation to R_MICROMIPS_PC23_S2.
+ We add 4 to take LUI deletion into account while checking
+ the PC-relative distance. */
+ else if (symval % 4 == 0
+ && IS_BITSIZE (pcrval + 4, 25)
+ && MATCH (nextopc, addiu_insn)
+ && OP32_TREG (nextopc) == OP32_SREG (nextopc)
+ && OP16_VALID_REG (OP32_TREG (nextopc)))
+ {
+ /* Fix the relocation's type. */
+ irel[1].r_info = ELF32_R_INFO (r_symndx, R_MICROMIPS_PC23_S2);
+
+ /* Replace ADDIU with the ADDIUPC version. */
+ nextopc = (addiupc_insn.match
+ | ADDIUPC_REG_FIELD (OP32_TREG (nextopc)));
+
+ bfd_put_16 (abfd, (nextopc >> 16) & 0xffff,
+ contents + irel[1].r_offset);
+ bfd_put_16 (abfd, nextopc & 0xffff,
+ contents + irel[1].r_offset + 2);
+ }
+
+ /* Can't do anything, give up, sigh... */
+ else
+ continue;
+
+ /* Fix the relocation's type. */
+ irel->r_info = ELF32_R_INFO (r_symndx, R_MIPS_NONE);
+
+ /* Delete the LUI instruction: 4 bytes at irel->r_offset. */
+ delcnt = 4;
+ deloff = 0;
+ }
+
+ /* Compact branch relaxation -- due to the multitude of macros
+ employed by the compiler/assembler, compact branches are not
+ always generated. Obviously, this can/will be fixed elsewhere,
+ but there is no drawback in double checking it here. */
+ else if (r_type == R_MICROMIPS_PC16_S1
+ && irel->r_offset + 5 < sec->size
+ && ((fndopc = find_match (opcode, bz_rs_insns_32)) >= 0
+ || (fndopc = find_match (opcode, bz_rt_insns_32)) >= 0)
+ && MATCH (bfd_get_16 (abfd, contents + irel->r_offset + 4),
+ nop_insn_16))
+ {
+ unsigned long reg;
+
+ reg = OP32_SREG (opcode) ? OP32_SREG (opcode) : OP32_TREG (opcode);
+
+ /* Replace BEQZ/BNEZ with the compact version. */
+ opcode = (bzc_insns_32[fndopc].match
+ | BZC32_REG_FIELD (reg)
+ | (opcode & 0xffff)); /* Addend value. */
+
+ bfd_put_16 (abfd, (opcode >> 16) & 0xffff,
+ contents + irel->r_offset);
+ bfd_put_16 (abfd, opcode & 0xffff,
+ contents + irel->r_offset + 2);
+
+ /* Delete the 16-bit delay slot NOP: two bytes from
+ irel->offset + 4. */
+ delcnt = 2;
+ deloff = 4;
+ }
+
+ /* R_MICROMIPS_PC16_S1 relaxation to R_MICROMIPS_PC10_S1. We need
+ to check the distance from the next instruction, so subtract 2. */
+ else if (r_type == R_MICROMIPS_PC16_S1
+ && IS_BITSIZE (pcrval - 2, 11)
+ && find_match (opcode, b_insns_32) >= 0)
+ {
+ /* Fix the relocation's type. */
+ irel->r_info = ELF32_R_INFO (r_symndx, R_MICROMIPS_PC10_S1);
+
+ /* Replace the the 32-bit opcode with a 16-bit opcode. */
+ bfd_put_16 (abfd,
+ (b_insn_16.match
+ | (opcode & 0x3ff)), /* Addend value. */
+ contents + irel->r_offset);
+
+ /* Delete 2 bytes from irel->r_offset + 2. */
+ delcnt = 2;
+ deloff = 2;
+ }
+
+ /* R_MICROMIPS_PC16_S1 relaxation to R_MICROMIPS_PC7_S1. We need
+ to check the distance from the next instruction, so subtract 2. */
+ else if (r_type == R_MICROMIPS_PC16_S1
+ && IS_BITSIZE (pcrval - 2, 8)
+ && (((fndopc = find_match (opcode, bz_rs_insns_32)) >= 0
+ && OP16_VALID_REG (OP32_SREG (opcode)))
+ || ((fndopc = find_match (opcode, bz_rt_insns_32)) >= 0
+ && OP16_VALID_REG (OP32_TREG (opcode)))))
+ {
+ unsigned long reg;
+
+ reg = OP32_SREG (opcode) ? OP32_SREG (opcode) : OP32_TREG (opcode);
+
+ /* Fix the relocation's type. */
+ irel->r_info = ELF32_R_INFO (r_symndx, R_MICROMIPS_PC7_S1);
+
+ /* Replace the the 32-bit opcode with a 16-bit opcode. */
+ bfd_put_16 (abfd,
+ (bz_insns_16[fndopc].match
+ | BZ16_REG_FIELD (reg)
+ | (opcode & 0x7f)), /* Addend value. */
+ contents + irel->r_offset);
+
+ /* Delete 2 bytes from irel->r_offset + 2. */
+ delcnt = 2;
+ deloff = 2;
+ }
+
+ /* R_MICROMIPS_26_S1 -- JAL to JALS relaxation for microMIPS targets. */
+ else if (r_type == R_MICROMIPS_26_S1
+ && target_is_micromips_code_p
+ && irel->r_offset + 7 < sec->size
+ && MATCH (opcode, jal_insn_32_bd32))
+ {
+ unsigned long n32opc;
+ bfd_boolean relaxed = FALSE;
+
+ n32opc = bfd_get_16 (abfd, contents + irel->r_offset + 4) << 16;
+ n32opc |= bfd_get_16 (abfd, contents + irel->r_offset + 6);
+
+ if (MATCH (n32opc, nop_insn_32))
+ {
+ /* Replace delay slot 32-bit NOP with a 16-bit NOP. */
+ bfd_put_16 (abfd, nop_insn_16.match,
+ contents + irel->r_offset + 4);
+
+ relaxed = TRUE;
+ }
+ else if (find_match (n32opc, move_insns_32) >= 0)
+ {
+ /* Replace delay slot 32-bit MOVE with 16-bit MOVE. */
+ bfd_put_16 (abfd,
+ (move_insn_16.match
+ | MOVE16_RD_FIELD (MOVE32_RD (n32opc))
+ | MOVE16_RS_FIELD (MOVE32_RS (n32opc))),
+ contents + irel->r_offset + 4);
+
+ relaxed = TRUE;
+ }
+ /* Other 32-bit instructions relaxable to 16-bit
+ instructions will be handled here later. */
+
+ if (relaxed)
+ {
+ /* JAL with 32-bit delay slot that is changed to a JALS
+ with 16-bit delay slot. */
+ bfd_put_16 (abfd, (jal_insn_32_bd16.match >> 16) & 0xffff,
+ contents + irel->r_offset);
+ bfd_put_16 (abfd, jal_insn_32_bd16.match & 0xffff,
+ contents + irel->r_offset + 2);
+
+ /* Delete 2 bytes from irel->r_offset + 6. */
+ delcnt = 2;
+ deloff = 6;
+ }
+ }
+
+ if (delcnt != 0)
+ {
+ /* Note that we've changed the relocs, section contents, etc. */
+ elf_section_data (sec)->relocs = internal_relocs;
+ elf_section_data (sec)->this_hdr.contents = contents;
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+
+ /* Delete bytes depending on the delcnt and deloff. */
+ if (!mips_elf_relax_delete_bytes (abfd, sec,
+ irel->r_offset + deloff, delcnt))
+ goto error_return;
+
+ /* That will change things, so we should relax again.
+ Note that this is not required, and it may be slow. */
+ *again = TRUE;
+ }
+ }
+
+ if (isymbuf != NULL
+ && symtab_hdr->contents != (unsigned char *) isymbuf)
+ {
+ if (! link_info->keep_memory)
+ free (isymbuf);
+ else
+ {
+ /* Cache the symbols for elf_link_input_bfd. */
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+ }
+ }
+
+ if (contents != NULL
+ && elf_section_data (sec)->this_hdr.contents != contents)
+ {
+ if (! link_info->keep_memory)
+ free (contents);
+ else
+ {
+ /* Cache the section contents for elf_link_input_bfd. */
+ elf_section_data (sec)->this_hdr.contents = contents;
+ }
+ }
+
+ if (internal_relocs != NULL
+ && elf_section_data (sec)->relocs != internal_relocs)
+ free (internal_relocs);
+
+ return TRUE;
+
+ error_return:
+ if (isymbuf != NULL
+ && symtab_hdr->contents != (unsigned char *) isymbuf)
+ free (isymbuf);
+ if (contents != NULL
+ && elf_section_data (sec)->this_hdr.contents != contents)
+ free (contents);
+ if (internal_relocs != NULL
+ && elf_section_data (sec)->relocs != internal_relocs)
+ free (internal_relocs);
+
+ return FALSE;
+}
+\f
/* Create a MIPS ELF linker hash table. */
struct bfd_link_hash_table *
old_flags &= ~EF_MIPS_ABI;
}
- /* For now, allow arbitrary mixing of ASEs (retain the union). */
+ /* Compare ASEs. Forbid linking MIPS16 and microMIPS ASE modules together
+ and allow arbitrary mixing of the remaining ASEs (retain the union). */
if ((new_flags & EF_MIPS_ARCH_ASE) != (old_flags & EF_MIPS_ARCH_ASE))
{
+ int old_micro = old_flags & EF_MIPS_ARCH_ASE_MICROMIPS;
+ int new_micro = new_flags & EF_MIPS_ARCH_ASE_MICROMIPS;
+ int old_m16 = old_flags & EF_MIPS_ARCH_ASE_M16;
+ int new_m16 = new_flags & EF_MIPS_ARCH_ASE_M16;
+ int micro_mis = old_m16 && new_micro;
+ int m16_mis = old_micro && new_m16;
+
+ if (m16_mis || micro_mis)
+ {
+ (*_bfd_error_handler)
+ (_("%B: ASE mismatch: linking %s module with previous %s modules"),
+ ibfd,
+ m16_mis ? "MIPS16" : "microMIPS",
+ m16_mis ? "microMIPS" : "MIPS16");
+ ok = FALSE;
+ }
+
elf_elfheader (obfd)->e_flags |= new_flags & EF_MIPS_ARCH_ASE;
new_flags &= ~ EF_MIPS_ARCH_ASE;
if (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_M16)
fprintf (file, " [mips16]");
+ if (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS)
+ fprintf (file, " [micromips]");
+
if (elf_elfheader (abfd)->e_flags & EF_MIPS_32BITMODE)
fprintf (file, " [32bitmode]");
else
struct elf_link_hash_entry *);
extern bfd_boolean _bfd_mips_elf_ignore_discarded_relocs
(asection *);
+extern bfd_boolean _bfd_mips_elf_is_target_special_symbol
+ (bfd *abfd, asymbol *sym);
extern bfd_boolean _bfd_mips_elf_find_nearest_line
(bfd *, asection *, asymbol **, bfd_vma, const char **,
const char **, unsigned int *);
extern bfd_byte *_bfd_elf_mips_get_relocated_section_contents
(bfd *, struct bfd_link_info *, struct bfd_link_order *,
bfd_byte *, bfd_boolean, asymbol **);
+extern bfd_boolean _bfd_mips_elf_relax_section
+ (bfd *abfd, asection *sec, struct bfd_link_info *link_info,
+ bfd_boolean *again);
extern struct bfd_link_hash_table *_bfd_mips_elf_link_hash_table_create
(bfd *);
extern struct bfd_link_hash_table *_bfd_mips_vxworks_link_hash_table_create
extern bfd_boolean _bfd_mips_elf_read_ecoff_info
(bfd *, asection *, struct ecoff_debug_info *);
-extern void _bfd_mips16_elf_reloc_unshuffle
+extern void _bfd_mips_elf_reloc_unshuffle
(bfd *, int, bfd_boolean, bfd_byte *);
-extern void _bfd_mips16_elf_reloc_shuffle
+extern void _bfd_mips_elf_reloc_shuffle
(bfd *, int, bfd_boolean, bfd_byte *);
extern bfd_reloc_status_type _bfd_mips_elf_gprel16_with_gp
(bfd *, asymbol *, arelent *, asection *, bfd_boolean, void *, bfd_vma);
static inline bfd_boolean
gprel16_reloc_p (unsigned int r_type)
{
- return r_type == R_MIPS_GPREL16 || r_type == R_MIPS16_GPREL;
+ return (r_type == R_MIPS_GPREL16
+ || r_type == R_MIPS16_GPREL
+ || r_type == R_MICROMIPS_GPREL16
+ || r_type == R_MICROMIPS_GPREL7_S2);
+}
+
+static inline bfd_boolean
+literal_reloc_p (int r_type)
+{
+ return r_type == R_MIPS_LITERAL || r_type == R_MICROMIPS_LITERAL;
}
#define elf_backend_common_definition _bfd_mips_elf_common_definition
"BFD_RELOC_ALPHA_TPREL_LO16",
"BFD_RELOC_ALPHA_TPREL16",
"BFD_RELOC_MIPS_JMP",
+ "BFD_RELOC_MICROMIPS_JMP",
"BFD_RELOC_MIPS16_JMP",
"BFD_RELOC_MIPS16_GPREL",
"BFD_RELOC_HI16",
"BFD_RELOC_MIPS16_HI16_S",
"BFD_RELOC_MIPS16_LO16",
"BFD_RELOC_MIPS_LITERAL",
+ "BFD_RELOC_MICROMIPS_LITERAL",
+ "BFD_RELOC_MICROMIPS_7_PCREL_S1",
+ "BFD_RELOC_MICROMIPS_10_PCREL_S1",
+ "BFD_RELOC_MICROMIPS_16_PCREL_S1",
+ "BFD_RELOC_MICROMIPS_GPREL16",
+ "BFD_RELOC_MICROMIPS_HI16",
+ "BFD_RELOC_MICROMIPS_HI16_S",
+ "BFD_RELOC_MICROMIPS_LO16",
"BFD_RELOC_MIPS_GOT16",
+ "BFD_RELOC_MICROMIPS_GOT16",
"BFD_RELOC_MIPS_CALL16",
+ "BFD_RELOC_MICROMIPS_CALL16",
"BFD_RELOC_MIPS_GOT_HI16",
+ "BFD_RELOC_MICROMIPS_GOT_HI16",
"BFD_RELOC_MIPS_GOT_LO16",
+ "BFD_RELOC_MICROMIPS_GOT_LO16",
"BFD_RELOC_MIPS_CALL_HI16",
+ "BFD_RELOC_MICROMIPS_CALL_HI16",
"BFD_RELOC_MIPS_CALL_LO16",
+ "BFD_RELOC_MICROMIPS_CALL_LO16",
"BFD_RELOC_MIPS_SUB",
+ "BFD_RELOC_MICROMIPS_SUB",
"BFD_RELOC_MIPS_GOT_PAGE",
+ "BFD_RELOC_MICROMIPS_GOT_PAGE",
"BFD_RELOC_MIPS_GOT_OFST",
+ "BFD_RELOC_MICROMIPS_GOT_OFST",
"BFD_RELOC_MIPS_GOT_DISP",
+ "BFD_RELOC_MICROMIPS_GOT_DISP",
"BFD_RELOC_MIPS_SHIFT5",
"BFD_RELOC_MIPS_SHIFT6",
"BFD_RELOC_MIPS_INSERT_A",
"BFD_RELOC_MIPS_INSERT_B",
"BFD_RELOC_MIPS_DELETE",
"BFD_RELOC_MIPS_HIGHEST",
+ "BFD_RELOC_MICROMIPS_HIGHEST",
"BFD_RELOC_MIPS_HIGHER",
+ "BFD_RELOC_MICROMIPS_HIGHER",
"BFD_RELOC_MIPS_SCN_DISP",
+ "BFD_RELOC_MICROMIPS_SCN_DISP",
"BFD_RELOC_MIPS_REL16",
"BFD_RELOC_MIPS_RELGOT",
"BFD_RELOC_MIPS_JALR",
+ "BFD_RELOC_MICROMIPS_JALR",
"BFD_RELOC_MIPS_TLS_DTPMOD32",
"BFD_RELOC_MIPS_TLS_DTPREL32",
"BFD_RELOC_MIPS_TLS_DTPMOD64",
"BFD_RELOC_MIPS_TLS_DTPREL64",
"BFD_RELOC_MIPS_TLS_GD",
+ "BFD_RELOC_MICROMIPS_TLS_GD",
"BFD_RELOC_MIPS_TLS_LDM",
+ "BFD_RELOC_MICROMIPS_TLS_LDM",
"BFD_RELOC_MIPS_TLS_DTPREL_HI16",
+ "BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16",
"BFD_RELOC_MIPS_TLS_DTPREL_LO16",
+ "BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16",
"BFD_RELOC_MIPS_TLS_GOTTPREL",
+ "BFD_RELOC_MICROMIPS_TLS_GOTTPREL",
"BFD_RELOC_MIPS_TLS_TPREL32",
"BFD_RELOC_MIPS_TLS_TPREL64",
"BFD_RELOC_MIPS_TLS_TPREL_HI16",
+ "BFD_RELOC_MICROMIPS_TLS_TPREL_HI16",
"BFD_RELOC_MIPS_TLS_TPREL_LO16",
+ "BFD_RELOC_MICROMIPS_TLS_TPREL_LO16",
"BFD_RELOC_MIPS_COPY",
"BFD_RELOC_MIPS_JUMP_SLOT",
ENUM
BFD_RELOC_MIPS_JMP
+ENUMX
+ BFD_RELOC_MICROMIPS_JMP
ENUMDOC
- Bits 27..2 of the relocation address shifted right 2 bits;
- simple reloc otherwise.
+ The MIPS jump instruction.
ENUM
BFD_RELOC_MIPS16_JMP
BFD_RELOC_HI16
ENUMDOC
High 16 bits of 32-bit value; simple reloc.
+
ENUM
BFD_RELOC_HI16_S
ENUMDOC
extended and added to form the final result. If the low 16
bits form a negative number, we need to add one to the high value
to compensate for the borrow when the low bits are added.
+
ENUM
BFD_RELOC_LO16
ENUMDOC
ENUM
BFD_RELOC_MIPS_LITERAL
+ENUMX
+ BFD_RELOC_MICROMIPS_LITERAL
ENUMDOC
Relocation against a MIPS literal section.
+ENUM
+ BFD_RELOC_MICROMIPS_7_PCREL_S1
+ENUMX
+ BFD_RELOC_MICROMIPS_10_PCREL_S1
+ENUMX
+ BFD_RELOC_MICROMIPS_16_PCREL_S1
+ENUMDOC
+ microMIPS PC-relative relocations.
+
+ENUM
+ BFD_RELOC_MICROMIPS_GPREL16
+ENUMX
+ BFD_RELOC_MICROMIPS_HI16
+ENUMX
+ BFD_RELOC_MICROMIPS_HI16_S
+ENUMX
+ BFD_RELOC_MICROMIPS_LO16
+ENUMDOC
+ microMIPS versions of generic BFD relocs.
+
ENUM
BFD_RELOC_MIPS_GOT16
+ENUMX
+ BFD_RELOC_MICROMIPS_GOT16
ENUMX
BFD_RELOC_MIPS_CALL16
+ENUMX
+ BFD_RELOC_MICROMIPS_CALL16
ENUMX
BFD_RELOC_MIPS_GOT_HI16
+ENUMX
+ BFD_RELOC_MICROMIPS_GOT_HI16
ENUMX
BFD_RELOC_MIPS_GOT_LO16
+ENUMX
+ BFD_RELOC_MICROMIPS_GOT_LO16
ENUMX
BFD_RELOC_MIPS_CALL_HI16
+ENUMX
+ BFD_RELOC_MICROMIPS_CALL_HI16
ENUMX
BFD_RELOC_MIPS_CALL_LO16
+ENUMX
+ BFD_RELOC_MICROMIPS_CALL_LO16
ENUMX
BFD_RELOC_MIPS_SUB
+ENUMX
+ BFD_RELOC_MICROMIPS_SUB
ENUMX
BFD_RELOC_MIPS_GOT_PAGE
+ENUMX
+ BFD_RELOC_MICROMIPS_GOT_PAGE
ENUMX
BFD_RELOC_MIPS_GOT_OFST
+ENUMX
+ BFD_RELOC_MICROMIPS_GOT_OFST
ENUMX
BFD_RELOC_MIPS_GOT_DISP
+ENUMX
+ BFD_RELOC_MICROMIPS_GOT_DISP
ENUMX
BFD_RELOC_MIPS_SHIFT5
ENUMX
BFD_RELOC_MIPS_DELETE
ENUMX
BFD_RELOC_MIPS_HIGHEST
+ENUMX
+ BFD_RELOC_MICROMIPS_HIGHEST
ENUMX
BFD_RELOC_MIPS_HIGHER
+ENUMX
+ BFD_RELOC_MICROMIPS_HIGHER
ENUMX
BFD_RELOC_MIPS_SCN_DISP
+ENUMX
+ BFD_RELOC_MICROMIPS_SCN_DISP
ENUMX
BFD_RELOC_MIPS_REL16
ENUMX
BFD_RELOC_MIPS_RELGOT
ENUMX
BFD_RELOC_MIPS_JALR
+ENUMX
+ BFD_RELOC_MICROMIPS_JALR
ENUMX
BFD_RELOC_MIPS_TLS_DTPMOD32
ENUMX
BFD_RELOC_MIPS_TLS_DTPREL64
ENUMX
BFD_RELOC_MIPS_TLS_GD
+ENUMX
+ BFD_RELOC_MICROMIPS_TLS_GD
ENUMX
BFD_RELOC_MIPS_TLS_LDM
+ENUMX
+ BFD_RELOC_MICROMIPS_TLS_LDM
ENUMX
BFD_RELOC_MIPS_TLS_DTPREL_HI16
+ENUMX
+ BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
ENUMX
BFD_RELOC_MIPS_TLS_DTPREL_LO16
+ENUMX
+ BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
ENUMX
BFD_RELOC_MIPS_TLS_GOTTPREL
+ENUMX
+ BFD_RELOC_MICROMIPS_TLS_GOTTPREL
ENUMX
BFD_RELOC_MIPS_TLS_TPREL32
ENUMX
BFD_RELOC_MIPS_TLS_TPREL64
ENUMX
BFD_RELOC_MIPS_TLS_TPREL_HI16
+ENUMX
+ BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
ENUMX
BFD_RELOC_MIPS_TLS_TPREL_LO16
+ENUMX
+ BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
ENUMDOC
MIPS ELF relocations.
COMMENT
+2011-07-24 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * readelf.c (get_machine_flags): Handle microMIPS ASE.
+ (get_mips_symbol_other): Likewise.
+
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (init_dwarf_regnames): Handle EM_K1OM.
if (e_flags & EF_MIPS_ARCH_ASE_M16)
strcat (buf, ", mips16");
+ if (e_flags & EF_MIPS_ARCH_ASE_MICROMIPS)
+ strcat (buf, ", micromips");
+
switch ((e_flags & EF_MIPS_ARCH))
{
case E_MIPS_ARCH_1: strcat (buf, ", mips1"); break;
{
switch (other)
{
- case STO_OPTIONAL: return "OPTIONAL";
- case STO_MIPS16: return "MIPS16";
- case STO_MIPS_PLT: return "MIPS PLT";
- case STO_MIPS_PIC: return "MIPS PIC";
- default: return NULL;
+ case STO_OPTIONAL:
+ return "OPTIONAL";
+ case STO_MIPS_PLT:
+ return "MIPS PLT";
+ case STO_MIPS_PIC:
+ return "MIPS PIC";
+ case STO_MICROMIPS:
+ return "MICROMIPS";
+ case STO_MICROMIPS | STO_MIPS_PIC:
+ return "MICROMIPS, MIPS PIC";
+ case STO_MIPS16:
+ return "MIPS16";
+ default:
+ return NULL;
}
}
+2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
+ Chao-ying Fu <fu@mips.com>
+ Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.h (mips_segment_info): Add one bit for
+ microMIPS.
+ (TC_LABEL_IS_LOCAL): New macro.
+ (mips_label_is_local): New prototype.
+ * config/tc-mips.c (S0, S7): New macros.
+ (emit_branch_likely_macro): New variable.
+ (mips_set_options): Add micromips.
+ (mips_opts): Initialise micromips to -1.
+ (file_ase_micromips): New variable.
+ (CPU_HAS_MICROMIPS): New macro.
+ (hilo_interlocks): Set for microMIPS too.
+ (gpr_interlocks): Likewise.
+ (cop_interlocks): Likewise.
+ (cop_mem_interlocks): Likewise.
+ (HAVE_CODE_COMPRESSION): New macro.
+ (micromips_op_hash): New variable.
+ (micromips_nop16_insn, micromips_nop32_insn): New variables.
+ (NOP_INSN): Handle microMIPS ASE.
+ (mips32_to_micromips_reg_b_map): New macro.
+ (mips32_to_micromips_reg_c_map): Likewise.
+ (mips32_to_micromips_reg_d_map): Likewise.
+ (mips32_to_micromips_reg_e_map): Likewise.
+ (mips32_to_micromips_reg_f_map): Likewise.
+ (mips32_to_micromips_reg_g_map): Likewise.
+ (mips32_to_micromips_reg_l_map): Likewise.
+ (mips32_to_micromips_reg_n_map): Likewise.
+ (mips32_to_micromips_reg_h_map): New variable.
+ (mips32_to_micromips_reg_m_map): Likewise.
+ (mips32_to_micromips_reg_q_map): Likewise.
+ (micromips_to_32_reg_h_map): New variable.
+ (micromips_to_32_reg_i_map): Likewise.
+ (micromips_to_32_reg_m_map): Likewise.
+ (micromips_to_32_reg_q_map): Likewise.
+ (micromips_to_32_reg_b_map): New macro.
+ (micromips_to_32_reg_c_map): Likewise.
+ (micromips_to_32_reg_d_map): Likewise.
+ (micromips_to_32_reg_e_map): Likewise.
+ (micromips_to_32_reg_f_map): Likewise.
+ (micromips_to_32_reg_g_map): Likewise.
+ (micromips_to_32_reg_l_map): Likewise.
+ (micromips_to_32_reg_n_map): Likewise.
+ (micromips_imm_b_map, micromips_imm_c_map): New macros.
+ (RELAX_DELAY_SLOT_16BIT): New macro.
+ (RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
+ (RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
+ (RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
+ (RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise.
+ (RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise.
+ (RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
+ (RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise.
+ (RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
+ (RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
+ (RELAX_MICROMIPS_TOOFAR32): Likewise.
+ (RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
+ (RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
+ (INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
+ (mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
+ fsize and insns.
+ (mips_mark_labels): New function.
+ (mips16_small, mips16_ext): Remove variables, replacing with...
+ (forced_insn_size): ... this.
+ (append_insn, mips16_ip): Update accordingly.
+ (micromips_insn_length): New function.
+ (insn_length): Return the length of microMIPS instructions.
+ (mips_record_mips16_mode): Rename to...
+ (mips_record_compressed_mode): ... this. Handle microMIPS ASE.
+ (install_insn): Handle microMIPS ASE.
+ (reglist_lookup): New function.
+ (is_size_valid, is_delay_slot_valid): Likewise.
+ (md_begin): Handle microMIPS ASE.
+ (md_assemble): Likewise. Update for append_insn interface change.
+ (micromips_reloc_p): New function.
+ (got16_reloc_p): Handle microMIPS ASE.
+ (hi16_reloc_p): Likewise.
+ (lo16_reloc_p): Likewise.
+ (jmp_reloc_p): New function.
+ (jalr_reloc_p): Likewise.
+ (matching_lo_reloc): Handle microMIPS ASE.
+ (insn_uses_reg, reg_needs_delay): Likewise.
+ (mips_move_labels): Likewise.
+ (mips16_mark_labels): Rename to...
+ (mips_compressed_mark_labels): ... this. Handle microMIPS ASE.
+ (gpr_mod_mask): New function.
+ (gpr_read_mask, gpr_write_mask): Handle microMIPS ASE.
+ (fpr_read_mask, fpr_write_mask): Likewise.
+ (insns_between, nops_for_vr4130, nops_for_insn): Likewise.
+ (fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
+ (MICROMIPS_LABEL_CHAR): New macro.
+ (micromips_target_label, micromips_target_name): New variables.
+ (micromips_label_name, micromips_label_expr): New functions.
+ (micromips_label_inc, micromips_add_label): Likewise.
+ (mips_label_is_local): Likewise.
+ (micromips_map_reloc): Likewise.
+ (can_swap_branch_p): Handle microMIPS ASE.
+ (append_insn): Add expansionp argument. Handle microMIPS ASE.
+ (start_noreorder, end_noreorder): Handle microMIPS ASE.
+ (macro_start, macro_warning, macro_end): Likewise.
+ (brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
+ (mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
+ (BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
+ (MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
+ (macro_build): Handle microMIPS ASE. Update for append_insn
+ interface change.
+ (mips16_macro_build): Update for append_insn interface change.
+ (macro_build_jalr): Handle microMIPS ASE.
+ (macro_build_lui): Likewise. Simplify.
+ (load_register): Handle microMIPS ASE.
+ (load_address): Likewise.
+ (move_register): Likewise.
+ (macro_build_branch_likely): New function.
+ (macro_build_branch_ccl): Likewise.
+ (macro_build_branch_rs): Likewise.
+ (macro_build_branch_rsrt): Likewise.
+ (macro): Handle microMIPS ASE.
+ (validate_micromips_insn): New function.
+ (expr_const_in_range): Likewise.
+ (mips_ip): Handle microMIPS ASE.
+ (options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
+ (md_longopts): Add mmicromips and mno-micromips.
+ (md_parse_option): Handle OPTION_MICROMIPS and
+ OPTION_NO_MICROMIPS.
+ (mips_after_parse_args): Handle microMIPS ASE.
+ (md_pcrel_from): Handle microMIPS relocations.
+ (mips_force_relocation): Likewise.
+ (md_apply_fix): Likewise.
+ (mips_align): Handle microMIPS ASE.
+ (s_mipsset): Likewise.
+ (s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
+ (s_dtprel_internal): Likewise.
+ (s_gpword, s_gpdword): Likewise.
+ (s_insn): Handle microMIPS ASE.
+ (s_mips_stab): Likewise.
+ (relaxed_micromips_32bit_branch_length): New function.
+ (relaxed_micromips_16bit_branch_length): New function.
+ (md_estimate_size_before_relax): Handle microMIPS ASE.
+ (mips_fix_adjustable): Likewise.
+ (tc_gen_reloc): Handle microMIPS relocations.
+ (mips_relax_frag): Handle microMIPS ASE.
+ (md_convert_frag): Likewise.
+ (mips_frob_file_after_relocs): Likewise.
+ (mips_elf_final_processing): Likewise.
+ (mips_nop_opcode): Likewise.
+ (mips_handle_align): Likewise.
+ (md_show_usage): Handle microMIPS options.
+ * symbols.c (TC_LABEL_IS_LOCAL): New macro.
+ (S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.
+
+ * doc/as.texinfo (Target MIPS options): Add -mmicromips and
+ -mno-micromips.
+ (-mmicromips, -mno-micromips): New options.
+ * doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
+ (MIPS ISA): Document .set micromips and .set nomicromips.
+ (MIPS insn): Update for microMIPS support.
+
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (mips_ip): Make a copy of the instruction's
#define ZERO 0
#define ATREG 1
+#define S0 16
+#define S7 23
#define TREG 24
#define PIC_CALL_REG 25
#define KT0 26
Changed by `.set mips16' and `.set nomips16', and the -mips16 and
-nomips16 command line options, and the default CPU. */
int mips16;
+ /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
+ 1 if we are, and -1 if the value has not been initialized. Changed
+ by `.set micromips' and `.set nomicromips', and the -mmicromips
+ and -mno-micromips command line options, and the default CPU. */
+ int micromips;
/* Non-zero if we should not reorder instructions. Changed by `.set
reorder' and `.set noreorder'. */
int noreorder;
{
/* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
/* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
- /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
+ /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, /* at */ ATREG,
/* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
/* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
/* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
|| mips_opts.isa == ISA_MIPS64 \
|| mips_opts.isa == ISA_MIPS64R2)
+/* True if any microMIPS code was produced. */
+static int file_ase_micromips;
+
/* True if we want to create R_MIPS_JALR for jalr $25. */
#ifdef TE_IRIX
#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
/* Return true if ISA supports 64-bit right rotate (dror et al.)
instructions. */
#define ISA_HAS_DROR(ISA) \
- ((ISA) == ISA_MIPS64R2)
+ ((ISA) == ISA_MIPS64R2 \
+ || (mips_opts.micromips \
+ && ISA_HAS_64BIT_REGS (ISA)) \
+ )
/* Return true if ISA supports 32-bit right rotate (ror et al.)
instructions. */
#define ISA_HAS_ROR(ISA) \
((ISA) == ISA_MIPS32R2 \
|| (ISA) == ISA_MIPS64R2 \
- || mips_opts.ase_smartmips)
+ || mips_opts.ase_smartmips \
+ || mips_opts.micromips \
+ )
/* Return true if ISA supports single-precision floats in odd registers. */
#define ISA_HAS_ODD_SINGLE_FPR(ISA) \
(strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
|| strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
+/* Return true if the given CPU supports microMIPS. */
+#define CPU_HAS_MICROMIPS(cpu) 0
+
/* True if CPU has a dror instruction. */
#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
|| mips_opts.arch == CPU_R16000 \
|| mips_opts.arch == CPU_RM7000 \
|| mips_opts.arch == CPU_VR5500 \
+ || mips_opts.micromips \
)
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs after they are loaded from memory, and thus does not
require nops to be inserted. This applies to instructions marked
INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
- level I. */
-#define gpr_interlocks \
- (mips_opts.isa != ISA_MIPS1 \
- || mips_opts.arch == CPU_R3900)
+ level I and microMIPS mode instructions are always interlocked. */
+#define gpr_interlocks \
+ (mips_opts.isa != ISA_MIPS1 \
+ || mips_opts.arch == CPU_R3900 \
+ || mips_opts.micromips \
+ )
/* Whether the processor uses hardware interlocks to avoid delays
required by coprocessor instructions, and thus does not require
INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
between instructions marked INSN_WRITE_COND_CODE and ones marked
INSN_READ_COND_CODE. These nops are only required at MIPS ISA
- levels I, II, and III. */
+ levels I, II, and III and microMIPS mode instructions are always
+ interlocked. */
/* Itbl support may require additional care here. */
#define cop_interlocks \
((mips_opts.isa != ISA_MIPS1 \
&& mips_opts.isa != ISA_MIPS2 \
&& mips_opts.isa != ISA_MIPS3) \
|| mips_opts.arch == CPU_R4300 \
+ || mips_opts.micromips \
)
/* Whether the processor uses hardware interlocks to protect reads
from coprocessor registers after they are loaded from memory, and
thus does not require nops to be inserted. This applies to
instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
- requires at MIPS ISA level I. */
-#define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
+ requires at MIPS ISA level I and microMIPS mode instructions are
+ always interlocked. */
+#define cop_mem_interlocks \
+ (mips_opts.isa != ISA_MIPS1 \
+ || mips_opts.micromips \
+ )
/* Is this a mfhi or mflo instruction? */
#define MF_HILO_INSN(PINFO) \
&& ((PINFO) & (FP_S | FP_D)) == 0 \
&& ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
+/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
+ has been selected. This implies, in particular, that addresses of text
+ labels have their LSB set. */
+#define HAVE_CODE_COMPRESSION \
+ ((mips_opts.mips16 | mips_opts.micromips) != 0)
+
/* MIPS PIC level. */
enum mips_pic_level mips_pic;
/* The opcode hash table we use for the mips16. */
static struct hash_control *mips16_op_hash = NULL;
+/* The opcode hash table we use for the microMIPS ASE. */
+static struct hash_control *micromips_op_hash = NULL;
+
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful */
const char comment_chars[] = "#";
static struct mips_cl_insn history[1 + MAX_NOPS];
/* Nop instructions used by emit_nop. */
-static struct mips_cl_insn nop_insn, mips16_nop_insn;
+static struct mips_cl_insn nop_insn;
+static struct mips_cl_insn mips16_nop_insn;
+static struct mips_cl_insn micromips_nop16_insn;
+static struct mips_cl_insn micromips_nop32_insn;
/* The appropriate nop for the current mode. */
-#define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
+#define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
+ : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
+
+/* The size of NOP_INSN in bytes. */
+#define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
/* If this is set, it points to a frag holding nop instructions which
were inserted before the start of a noreorder section. If those
16, 17, 2, 3, 4, 5, 6, 7
};
+/* Map normal MIPS register numbers to microMIPS register numbers. */
+
+#define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
+#define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
+#define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
+#define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
+#define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
+#define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
+#define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
+
+#define X ILLEGAL_REG
+/* reg type h: 4, 5, 6. */
+static const int mips32_to_micromips_reg_h_map[] =
+{
+ X, X, X, X, 4, 5, 6, X,
+ X, X, X, X, X, X, X, X,
+ X, X, X, X, X, X, X, X,
+ X, X, X, X, X, X, X, X
+};
+
+/* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
+static const int mips32_to_micromips_reg_m_map[] =
+{
+ 0, X, 2, 3, X, X, X, X,
+ X, X, X, X, X, X, X, X,
+ 4, 1, 5, 6, 7, X, X, X,
+ X, X, X, X, X, X, X, X
+};
+
+/* reg type q: 0, 2-7. 17. */
+static const int mips32_to_micromips_reg_q_map[] =
+{
+ 0, X, 2, 3, 4, 5, 6, 7,
+ X, X, X, X, X, X, X, X,
+ X, 1, X, X, X, X, X, X,
+ X, X, X, X, X, X, X, X
+};
+
+#define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
+#undef X
+
+/* Map microMIPS register numbers to normal MIPS register numbers. */
+
+#define micromips_to_32_reg_b_map mips16_to_32_reg_map
+#define micromips_to_32_reg_c_map mips16_to_32_reg_map
+#define micromips_to_32_reg_d_map mips16_to_32_reg_map
+#define micromips_to_32_reg_e_map mips16_to_32_reg_map
+#define micromips_to_32_reg_f_map mips16_to_32_reg_map
+#define micromips_to_32_reg_g_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type h. */
+static const unsigned int micromips_to_32_reg_h_map[] =
+{
+ 5, 5, 6, 4, 4, 4, 4, 4
+};
+
+/* The microMIPS registers with type i. */
+static const unsigned int micromips_to_32_reg_i_map[] =
+{
+ 6, 7, 7, 21, 22, 5, 6, 7
+};
+
+#define micromips_to_32_reg_l_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type m. */
+static const unsigned int micromips_to_32_reg_m_map[] =
+{
+ 0, 17, 2, 3, 16, 18, 19, 20
+};
+
+#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
+
+/* The microMIPS registers with type q. */
+static const unsigned int micromips_to_32_reg_q_map[] =
+{
+ 0, 17, 2, 3, 4, 5, 6, 7
+};
+
+/* microMIPS imm type B. */
+static const int micromips_imm_b_map[] =
+{
+ 1, 4, 8, 12, 16, 20, 24, -1
+};
+
+/* microMIPS imm type C. */
+static const int micromips_imm_c_map[] =
+{
+ 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
+};
+
/* Classifies the kind of instructions we're interested in when
implementing -mfix-vr4120. */
enum fix_vr4120_class
Like RELAX_NOMACRO, but indicates that the macro appears in a branch
delay slot.
+ RELAX_DELAY_SLOT_16BIT
+ Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
+ 16-bit instruction.
+
+ RELAX_DELAY_SLOT_SIZE_FIRST
+ Like RELAX_DELAY_SLOT, but indicates that the first implementation of
+ the macro is of the wrong size for the branch delay slot.
+
+ RELAX_DELAY_SLOT_SIZE_SECOND
+ Like RELAX_DELAY_SLOT, but indicates that the second implementation of
+ the macro is of the wrong size for the branch delay slot.
+
The frag's "opcode" points to the first fixup for relaxable code.
Relaxable macros are generated using a sequence such as:
#define RELAX_SECOND_LONGER 0x20000
#define RELAX_NOMACRO 0x40000
#define RELAX_DELAY_SLOT 0x80000
+#define RELAX_DELAY_SLOT_16BIT 0x100000
+#define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
+#define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
/* Branch without likely bit. If label is out of range, we turn:
#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
+/* For microMIPS code, we use relaxation similar to one we use for
+ MIPS16 code. Some instructions that take immediate values support
+ two encodings: a small one which takes some small value, and a
+ larger one which takes a 16 bit value. As some branches also follow
+ this pattern, relaxing these values is required.
+
+ We can assemble both microMIPS and normal MIPS code in a single
+ object. Therefore, we need to support this type of relaxation at
+ the same time that we support the relaxation described above. We
+ use one of the high bits of the subtype field to distinguish these
+ cases.
+
+ The information we store for this type of relaxation is the argument
+ code found in the opcode file for this relocation, the register
+ selected as the assembler temporary, whether the user explicitly
+ requested a 16-bit form, whether the branch is unconditional, whether
+ it is compact, whether it stores the link address implicitly in $ra,
+ whether relaxation of out-of-range 32-bit branches to a sequence of
+ instructions is enabled, and whether the displacement of a branch is
+ too large to fit as an immediate argument of a 16-bit and a 32-bit
+ branch, respectively. */
+#define RELAX_MICROMIPS_ENCODE(type, at, u16bit, uncond, compact, link, \
+ relax32, toofar16, toofar32) \
+ (0x40000000 \
+ | ((type) & 0xff) \
+ | (((at) & 0x1f) << 8) \
+ | ((u16bit) ? 0x2000 : 0) \
+ | ((uncond) ? 0x4000 : 0) \
+ | ((compact) ? 0x8000 : 0) \
+ | ((link) ? 0x10000 : 0) \
+ | ((relax32) ? 0x20000 : 0) \
+ | ((toofar16) ? 0x40000 : 0) \
+ | ((toofar32) ? 0x80000 : 0))
+#define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
+#define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
+#define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
+#define RELAX_MICROMIPS_U16BIT(i) (((i) & 0x2000) != 0)
+#define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x4000) != 0)
+#define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x8000) != 0)
+#define RELAX_MICROMIPS_LINK(i) (((i) & 0x10000) != 0)
+#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x20000) != 0)
+
+#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x40000) != 0)
+#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x40000)
+#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x40000)
+#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x80000) != 0)
+#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x80000)
+#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x80000)
+
/* Is the given value a sign-extended 32-bit value? */
#define IS_SEXT_32BIT_NUM(x) \
(((x) &~ (offsetT) 0x7fffffff) == 0 \
(((x) &~ (offsetT) 0x7fff) == 0 \
|| (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
+/* Is the given value a sign-extended 12-bit value? */
+#define IS_SEXT_12BIT_NUM(x) \
+ (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
+
/* Is the given value a zero-extended 32-bit value? Or a negated one? */
#define IS_ZEXT_32BIT_NUM(x) \
(((x) &~ (offsetT) 0xffffffff) == 0 \
include/opcode/mips.h specifies operand fields using the macros
OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
with "MIPS16OP" instead of "OP". */
-#define INSERT_OPERAND(FIELD, INSN, VALUE) \
- INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
+#define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
+ do \
+ if (!(MICROMIPS)) \
+ INSERT_BITS ((INSN).insn_opcode, VALUE, \
+ OP_MASK_##FIELD, OP_SH_##FIELD); \
+ else \
+ INSERT_BITS ((INSN).insn_opcode, VALUE, \
+ MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
+ while (0)
#define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
INSERT_BITS ((INSN).insn_opcode, VALUE, \
MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
/* Extract the operand given by FIELD from mips_cl_insn INSN. */
-#define EXTRACT_OPERAND(FIELD, INSN) \
- EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
+#define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
+ (!(MICROMIPS) \
+ ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
+ : EXTRACT_BITS ((INSN).insn_opcode, \
+ MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
EXTRACT_BITS ((INSN).insn_opcode, \
MIPS16OP_MASK_##FIELD, \
MIPS16OP_SH_##FIELD)
\f
+/* Whether or not we are emitting a branch-likely macro. */
+static bfd_boolean emit_branch_likely_macro = FALSE;
+
/* Global variables used when generating relaxable macros. See the
comment above RELAX_ENCODE for more details about how relaxation
is used. */
/* True if the macro is in a branch delay slot. */
bfd_boolean delay_slot_p;
+ /* Set to the length in bytes required if the macro is in a delay slot
+ that requires a specific length of instruction, otherwise zero. */
+ unsigned int delay_slot_length;
+
/* For relaxable macros, sizes[0] is the length of the first alternative
in bytes and sizes[1] is the length of the second alternative.
For non-relaxable macros, both elements give the length of the
macro in bytes. */
unsigned int sizes[2];
+ /* For relaxable macros, first_insn_sizes[0] is the length of the first
+ instruction of the first alternative in bytes and first_insn_sizes[1]
+ is the length of the first instruction of the second alternative.
+ For non-relaxable macros, both elements give the length of the first
+ instruction in bytes.
+
+ Set to zero if we haven't yet seen the first instruction. */
+ unsigned int first_insn_sizes[2];
+
+ /* For relaxable macros, insns[0] is the number of instructions for the
+ first alternative and insns[1] is the number of instructions for the
+ second alternative.
+
+ For non-relaxable macros, both elements give the number of
+ instructions for the macro. */
+ unsigned int insns[2];
+
/* The first variant frag for this macro. */
fragS *first_frag;
} mips_macro_warning;
enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
static void append_insn
- (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
+ (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
+ bfd_boolean expansionp);
static void mips_no_prev_insn (void);
static void macro_build (expressionS *, const char *, const char *, ...);
static void mips16_macro_build
static bfd_boolean pic_need_relax (symbolS *, asection *);
static int relaxed_branch_length (fragS *, asection *, int);
static int validate_mips_insn (const struct mips_opcode *);
+static int validate_micromips_insn (const struct mips_opcode *);
+static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
+static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
/* Table and functions used to map between CPU/ISA names, and
ISA levels, and CPU numbers. */
#define label_list tc_segment_info_data.labels
static void mips_clear_insn_labels (void);
+static void mips_mark_labels (void);
+static void mips_compressed_mark_labels (void);
static inline void
mips_clear_insn_labels (void)
}
}
+/* Mark instruction labels in MIPS16/microMIPS mode. */
+
+static inline void
+mips_mark_labels (void)
+{
+ if (HAVE_CODE_COMPRESSION)
+ mips_compressed_mark_labels ();
+}
\f
static char *expr_end;
static bfd_reloc_code_real_type offset_reloc[3]
= {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
-/* These are set by mips16_ip if an explicit extension is used. */
+/* This is set to the resulting size of the instruction to be produced
+ by mips16_ip if an explicit extension is used or by mips_ip if an
+ explicit size is supplied. */
-static bfd_boolean mips16_small, mips16_ext;
+static unsigned int forced_insn_length;
#ifdef OBJ_ELF
/* The pdr segment for per procedure frame/regmask info. Not used for
}
}
+/* Return the length of a microMIPS instruction in bytes. If bits of
+ the mask beyond the low 16 are 0, then it is a 16-bit instruction.
+ Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
+ major opcode) will require further modifications to the opcode
+ table. */
+
+static inline unsigned int
+micromips_insn_length (const struct mips_opcode *mo)
+{
+ return (mo->mask >> 16) == 0 ? 2 : 4;
+}
+
/* Return the length of instruction INSN. */
static inline unsigned int
insn_length (const struct mips_cl_insn *insn)
{
- if (!mips_opts.mips16)
+ if (mips_opts.micromips)
+ return micromips_insn_length (insn->insn_mo);
+ else if (mips_opts.mips16)
+ return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
+ else
return 4;
- return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
}
/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
insn->complete_p = 0;
}
-/* Record the current MIPS16 mode in now_seg. */
+/* Record the current MIPS16/microMIPS mode in now_seg. */
static void
-mips_record_mips16_mode (void)
+mips_record_compressed_mode (void)
{
segment_info_type *si;
si = seg_info (now_seg);
if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
si->tc_segment_info_data.mips16 = mips_opts.mips16;
+ if (si->tc_segment_info_data.micromips != mips_opts.micromips)
+ si->tc_segment_info_data.micromips = mips_opts.micromips;
}
/* Install INSN at the location specified by its "frag" and "where" fields. */
install_insn (const struct mips_cl_insn *insn)
{
char *f = insn->frag->fr_literal + insn->where;
- if (!mips_opts.mips16)
+ if (!HAVE_CODE_COMPRESSION)
md_number_to_chars (f, insn->insn_opcode, 4);
+ else if (mips_opts.micromips)
+ {
+ unsigned int length = insn_length (insn);
+ if (length == 2)
+ md_number_to_chars (f, insn->insn_opcode, 2);
+ else if (length == 4)
+ {
+ md_number_to_chars (f, insn->insn_opcode >> 16, 2);
+ f += 2;
+ md_number_to_chars (f, insn->insn_opcode & 0xffff, 2);
+ }
+ else
+ as_bad (_("48-bit microMIPS instructions are not supported"));
+ }
else if (insn->mips16_absolute_jump_p)
{
md_number_to_chars (f, insn->insn_opcode >> 16, 2);
}
md_number_to_chars (f, insn->insn_opcode, 2);
}
- mips_record_mips16_mode ();
+ mips_record_compressed_mode ();
}
/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
{0, 0}
};
+/* Check if S points at a valid register specifier according to TYPES.
+ If so, then return 1, advance S to consume the specifier and store
+ the register's number in REGNOP, otherwise return 0. */
+
static int
reg_lookup (char **s, unsigned int types, unsigned int *regnop)
{
return reg >= 0;
}
+/* Check if S points at a valid register list according to TYPES.
+ If so, then return 1, advance S to consume the list and store
+ the registers present on the list as a bitmask of ones in REGLISTP,
+ otherwise return 0. A valid list comprises a comma-separated
+ enumeration of valid single registers and/or dash-separated
+ contiguous register ranges as determined by their numbers.
+
+ As a special exception if one of s0-s7 registers is specified as
+ the range's lower delimiter and s8 (fp) is its upper one, then no
+ registers whose numbers place them between s7 and s8 (i.e. $24-$29)
+ are selected; they have to be named separately if needed. */
+
+static int
+reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
+{
+ unsigned int reglist = 0;
+ unsigned int lastregno;
+ bfd_boolean ok = TRUE;
+ unsigned int regmask;
+ unsigned int regno;
+ char *s_reset = *s;
+ char *s_end_of_list = *s;
+
+ while (reg_lookup (s, types, ®no))
+ {
+ lastregno = regno;
+ if (**s == '-')
+ {
+ (*s)++;
+ ok = reg_lookup (s, types, &lastregno);
+ if (ok && lastregno < regno)
+ ok = FALSE;
+ if (!ok)
+ break;
+ }
+
+ if (lastregno == FP && regno >= S0 && regno <= S7)
+ {
+ lastregno = S7;
+ reglist |= 1 << FP;
+ }
+ regmask = 1 << lastregno;
+ regmask = (regmask << 1) - 1;
+ regmask ^= (1 << regno) - 1;
+ reglist |= regmask;
+
+ s_end_of_list = *s;
+ if (**s != ',')
+ break;
+ (*s)++;
+ }
+
+ if (ok)
+ *s = s_end_of_list;
+ else
+ *s = s_reset;
+ if (reglistp)
+ *reglistp = reglist;
+ return ok && reglist != 0;
+}
+
/* Return TRUE if opcode MO is valid on the currently selected ISA and
architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
}
+/* Return TRUE if the size of the microMIPS opcode MO matches one
+ explicitly requested. Always TRUE in the standard MIPS mode. */
+
+static bfd_boolean
+is_size_valid (const struct mips_opcode *mo)
+{
+ if (!mips_opts.micromips)
+ return TRUE;
+
+ if (!forced_insn_length)
+ return TRUE;
+ if (mo->pinfo == INSN_MACRO)
+ return FALSE;
+ return forced_insn_length == micromips_insn_length (mo);
+}
+
+/* Return TRUE if the microMIPS opcode MO is valid for the delay slot
+ of the preceding instruction. Always TRUE in the standard MIPS mode. */
+
+static bfd_boolean
+is_delay_slot_valid (const struct mips_opcode *mo)
+{
+ if (!mips_opts.micromips)
+ return TRUE;
+
+ if (mo->pinfo == INSN_MACRO)
+ return TRUE;
+ if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
+ && micromips_insn_length (mo) != 4)
+ return FALSE;
+ if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
+ && micromips_insn_length (mo) != 2)
+ return FALSE;
+
+ return TRUE;
+}
+
/* This function is called once, at assembler startup time. It should set up
all the tables, etc. that the MD part of the assembler will need. */
&& strcmp (mips16_opcodes[i].name, name) == 0);
}
+ micromips_op_hash = hash_new ();
+
+ i = 0;
+ while (i < bfd_micromips_num_opcodes)
+ {
+ const char *name = micromips_opcodes[i].name;
+
+ retval = hash_insert (micromips_op_hash, name,
+ (void *) µmips_opcodes[i]);
+ if (retval != NULL)
+ as_fatal (_("internal: can't hash `%s': %s"),
+ micromips_opcodes[i].name, retval);
+ do
+ if (micromips_opcodes[i].pinfo != INSN_MACRO)
+ {
+ struct mips_cl_insn *micromips_nop_insn;
+
+ if (!validate_micromips_insn (µmips_opcodes[i]))
+ broken = 1;
+
+ if (micromips_insn_length (micromips_opcodes + i) == 2)
+ micromips_nop_insn = µmips_nop16_insn;
+ else if (micromips_insn_length (micromips_opcodes + i) == 4)
+ micromips_nop_insn = µmips_nop32_insn;
+ else
+ continue;
+
+ if (micromips_nop_insn->insn_mo == NULL
+ && strcmp (name, "nop") == 0)
+ {
+ create_insn (micromips_nop_insn, micromips_opcodes + i);
+ micromips_nop_insn->fixed_p = 1;
+ }
+ }
+ while (++i < bfd_micromips_num_opcodes
+ && strcmp (micromips_opcodes[i].name, name) == 0);
+ }
+
if (broken)
as_fatal (_("Broken assembler. No assembly attempted."));
else
{
if (imm_expr.X_op != O_absent)
- append_insn (&insn, &imm_expr, imm_reloc);
+ append_insn (&insn, &imm_expr, imm_reloc, FALSE);
else if (offset_expr.X_op != O_absent)
- append_insn (&insn, &offset_expr, offset_reloc);
+ append_insn (&insn, &offset_expr, offset_reloc, FALSE);
else
- append_insn (&insn, NULL, unused_reloc);
+ append_insn (&insn, NULL, unused_reloc, FALSE);
}
}
}
}
+static inline bfd_boolean
+micromips_reloc_p (bfd_reloc_code_real_type reloc)
+{
+ switch (reloc)
+ {
+ case BFD_RELOC_MICROMIPS_7_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_10_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_16_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_GPREL16:
+ case BFD_RELOC_MICROMIPS_JMP:
+ case BFD_RELOC_MICROMIPS_HI16:
+ case BFD_RELOC_MICROMIPS_HI16_S:
+ case BFD_RELOC_MICROMIPS_LO16:
+ case BFD_RELOC_MICROMIPS_LITERAL:
+ case BFD_RELOC_MICROMIPS_GOT16:
+ case BFD_RELOC_MICROMIPS_CALL16:
+ case BFD_RELOC_MICROMIPS_GOT_HI16:
+ case BFD_RELOC_MICROMIPS_GOT_LO16:
+ case BFD_RELOC_MICROMIPS_CALL_HI16:
+ case BFD_RELOC_MICROMIPS_CALL_LO16:
+ case BFD_RELOC_MICROMIPS_SUB:
+ case BFD_RELOC_MICROMIPS_GOT_PAGE:
+ case BFD_RELOC_MICROMIPS_GOT_OFST:
+ case BFD_RELOC_MICROMIPS_GOT_DISP:
+ case BFD_RELOC_MICROMIPS_HIGHEST:
+ case BFD_RELOC_MICROMIPS_HIGHER:
+ case BFD_RELOC_MICROMIPS_SCN_DISP:
+ case BFD_RELOC_MICROMIPS_JALR:
+ return TRUE;
+
+ default:
+ return FALSE;
+ }
+}
+
static inline bfd_boolean
got16_reloc_p (bfd_reloc_code_real_type reloc)
{
- return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
+ return (reloc == BFD_RELOC_MIPS_GOT16
+ || reloc == BFD_RELOC_MIPS16_GOT16
+ || reloc == BFD_RELOC_MICROMIPS_GOT16);
}
static inline bfd_boolean
hi16_reloc_p (bfd_reloc_code_real_type reloc)
{
- return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
+ return (reloc == BFD_RELOC_HI16_S
+ || reloc == BFD_RELOC_MIPS16_HI16_S
+ || reloc == BFD_RELOC_MICROMIPS_HI16_S);
}
static inline bfd_boolean
lo16_reloc_p (bfd_reloc_code_real_type reloc)
{
- return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
+ return (reloc == BFD_RELOC_LO16
+ || reloc == BFD_RELOC_MIPS16_LO16
+ || reloc == BFD_RELOC_MICROMIPS_LO16);
+}
+
+static inline bfd_boolean
+jmp_reloc_p (bfd_reloc_code_real_type reloc)
+{
+ return (reloc == BFD_RELOC_MIPS_JMP
+ || reloc == BFD_RELOC_MICROMIPS_JMP);
+}
+
+static inline bfd_boolean
+jalr_reloc_p (bfd_reloc_code_real_type reloc)
+{
+ return (reloc == BFD_RELOC_MIPS_JALR
+ || reloc == BFD_RELOC_MICROMIPS_JALR);
}
/* Return true if the given relocation might need a matching %lo().
static inline bfd_reloc_code_real_type
matching_lo_reloc (bfd_reloc_code_real_type reloc)
{
- return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
+ return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
+ : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
+ : BFD_RELOC_LO16));
}
/* Return true if the given fixup is followed by a matching R_MIPS_LO16
delay the use of general register rt for one instruction. */
/* Itbl support may require additional care here. */
know (prev_pinfo & INSN_WRITE_GPR_T);
- if (reg == EXTRACT_OPERAND (RT, history[0]))
+ if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
return 1;
}
gas_assert (S_GET_SEGMENT (l->label) == now_seg);
symbol_set_frag (l->label, frag_now);
val = (valueT) frag_now_fix ();
- /* mips16 text labels are stored as odd. */
- if (mips_opts.mips16)
+ /* MIPS16/microMIPS text labels are stored as odd. */
+ if (HAVE_CODE_COMPRESSION)
++val;
S_SET_VALUE (l->label, val);
}
return linkonce;
}
-/* Mark instruction labels in mips16 mode. This permits the linker to
- handle them specially, such as generating jalx instructions when
- needed. We also make them odd for the duration of the assembly, in
- order to generate the right sort of code. We will make them even
+/* Mark instruction labels in MIPS16/microMIPS mode. This permits the
+ linker to handle them specially, such as generating jalx instructions
+ when needed. We also make them odd for the duration of the assembly,
+ in order to generate the right sort of code. We will make them even
in the adjust_symtab routine, while leaving them marked. This is
convenient for the debugger and the disassembler. The linker knows
to make them odd again. */
static void
-mips16_mark_labels (void)
+mips_compressed_mark_labels (void)
{
segment_info_type *si = seg_info (now_seg);
struct insn_label_list *l;
- if (!mips_opts.mips16)
- return;
+ gas_assert (HAVE_CODE_COMPRESSION);
for (l = si->label_list; l != NULL; l = l->next)
{
#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
if (IS_ELF)
- S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
+ {
+ if (mips_opts.mips16)
+ S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
+ else
+ S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
+ }
#endif
if ((S_GET_VALUE (label) & 1) == 0
/* Don't adjust the address if the label is global or weak, or
in a link-once section, since we'll be emitting symbol reloc
references to it which will be patched up by the linker, and
- the final value of the symbol may or may not be MIPS16. */
+ the final value of the symbol may or may not be MIPS16/microMIPS. */
&& ! S_IS_WEAK (label)
&& ! S_IS_EXTERNAL (label)
&& ! s_is_linkonce (label, now_seg))
mips_relax.sequence = 0;
}
+/* Return the mask of core registers that instruction IP may
+ read or write. */
+
+static unsigned int
+gpr_mod_mask (const struct mips_cl_insn *ip)
+{
+ unsigned long pinfo, pinfo2;
+ unsigned int mask;
+
+ mask = 0;
+ pinfo = ip->insn_mo->pinfo;
+ pinfo2 = ip->insn_mo->pinfo2;
+ if (mips_opts.micromips)
+ {
+ if (pinfo2 & INSN2_MOD_GPR_MB)
+ mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
+ if (pinfo2 & INSN2_MOD_GPR_MC)
+ mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
+ if (pinfo2 & INSN2_MOD_GPR_MD)
+ mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
+ if (pinfo2 & INSN2_MOD_GPR_ME)
+ mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
+ if (pinfo2 & INSN2_MOD_GPR_MF)
+ mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
+ if (pinfo2 & INSN2_MOD_GPR_MG)
+ mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
+ if (pinfo2 & INSN2_MOD_GPR_MHI)
+ {
+ mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
+ mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
+ }
+ if (pinfo2 & INSN2_MOD_GPR_MJ)
+ mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
+ if (pinfo2 & INSN2_MOD_GPR_MM)
+ mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
+ if (pinfo2 & INSN2_MOD_GPR_MN)
+ mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
+ if (pinfo2 & INSN2_MOD_GPR_MP)
+ mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
+ if (pinfo2 & INSN2_MOD_GPR_MQ)
+ mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
+ if (pinfo2 & INSN2_MOD_SP)
+ mask |= 1 << SP;
+ }
+ return mask;
+}
+
/* Return the mask of core registers that IP reads. */
static unsigned int
unsigned long pinfo, pinfo2;
unsigned int mask;
- mask = 0;
+ mask = gpr_mod_mask (ip);
pinfo = ip->insn_mo->pinfo;
pinfo2 = ip->insn_mo->pinfo2;
if (mips_opts.mips16)
if (pinfo & MIPS16_INSN_READ_GPR_X)
mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
}
+ else if (mips_opts.micromips)
+ {
+ if (pinfo & INSN_READ_GPR_T)
+ mask |= 1 << EXTRACT_OPERAND (1, RT, *ip);
+ if (pinfo & INSN_READ_GPR_S)
+ mask |= 1 << EXTRACT_OPERAND (1, RS, *ip);
+ if (pinfo2 & INSN2_READ_GPR_31)
+ mask |= 1 << RA;
+ if (pinfo2 & INSN2_READ_GP)
+ mask |= 1 << GP;
+ }
else
{
if (pinfo2 & INSN2_READ_GPR_D)
- mask |= 1 << EXTRACT_OPERAND (RD, *ip);
+ mask |= 1 << EXTRACT_OPERAND (0, RD, *ip);
if (pinfo & INSN_READ_GPR_T)
- mask |= 1 << EXTRACT_OPERAND (RT, *ip);
+ mask |= 1 << EXTRACT_OPERAND (0, RT, *ip);
if (pinfo & INSN_READ_GPR_S)
- mask |= 1 << EXTRACT_OPERAND (RS, *ip);
+ mask |= 1 << EXTRACT_OPERAND (0, RS, *ip);
if (pinfo2 & INSN2_READ_GPR_Z)
- mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
+ mask |= 1 << EXTRACT_OPERAND (0, RZ, *ip);
}
/* Don't include register 0. */
return mask & ~1;
unsigned long pinfo, pinfo2;
unsigned int mask;
- mask = 0;
+ mask = gpr_mod_mask (ip);
pinfo = ip->insn_mo->pinfo;
pinfo2 = ip->insn_mo->pinfo2;
if (mips_opts.mips16)
if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
}
+ else if (mips_opts.micromips)
+ {
+ if (pinfo & INSN_WRITE_GPR_D)
+ mask |= 1 << EXTRACT_OPERAND (1, RD, *ip);
+ if (pinfo & INSN_WRITE_GPR_T)
+ mask |= 1 << EXTRACT_OPERAND (1, RT, *ip);
+ if (pinfo2 & INSN2_WRITE_GPR_S)
+ mask |= 1 << EXTRACT_OPERAND (1, RS, *ip);
+ if (pinfo & INSN_WRITE_GPR_31)
+ mask |= 1 << RA;
+ }
else
{
if (pinfo & INSN_WRITE_GPR_D)
- mask |= 1 << EXTRACT_OPERAND (RD, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
if (pinfo & INSN_WRITE_GPR_T)
- mask |= 1 << EXTRACT_OPERAND (RT, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
if (pinfo & INSN_WRITE_GPR_31)
mask |= 1 << RA;
if (pinfo2 & INSN2_WRITE_GPR_Z)
- mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
}
/* Don't include register 0. */
return mask & ~1;
mask = 0;
pinfo = ip->insn_mo->pinfo;
pinfo2 = ip->insn_mo->pinfo2;
- if (!mips_opts.mips16)
+ if (mips_opts.micromips)
+ {
+ if (pinfo2 & INSN2_READ_FPR_D)
+ mask |= 1 << EXTRACT_OPERAND (1, FD, *ip);
+ if (pinfo & INSN_READ_FPR_S)
+ mask |= 1 << EXTRACT_OPERAND (1, FS, *ip);
+ if (pinfo & INSN_READ_FPR_T)
+ mask |= 1 << EXTRACT_OPERAND (1, FT, *ip);
+ if (pinfo & INSN_READ_FPR_R)
+ mask |= 1 << EXTRACT_OPERAND (1, FR, *ip);
+ }
+ else if (!mips_opts.mips16)
{
if (pinfo & INSN_READ_FPR_S)
- mask |= 1 << EXTRACT_OPERAND (FS, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
if (pinfo & INSN_READ_FPR_T)
- mask |= 1 << EXTRACT_OPERAND (FT, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
if (pinfo & INSN_READ_FPR_R)
- mask |= 1 << EXTRACT_OPERAND (FR, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
if (pinfo2 & INSN2_READ_FPR_Z)
- mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
}
/* Conservatively treat all operands to an FP_D instruction are doubles.
(This is overly pessimistic for things like cvt.d.s.) */
mask = 0;
pinfo = ip->insn_mo->pinfo;
pinfo2 = ip->insn_mo->pinfo2;
- if (!mips_opts.mips16)
+ if (mips_opts.micromips)
+ {
+ if (pinfo2 & INSN_WRITE_FPR_D)
+ mask |= 1 << EXTRACT_OPERAND (1, FD, *ip);
+ if (pinfo & INSN_WRITE_FPR_S)
+ mask |= 1 << EXTRACT_OPERAND (1, FS, *ip);
+ if (pinfo & INSN_WRITE_FPR_T)
+ mask |= 1 << EXTRACT_OPERAND (1, FT, *ip);
+ }
+ else if (!mips_opts.mips16)
{
if (pinfo & INSN_WRITE_FPR_D)
- mask |= 1 << EXTRACT_OPERAND (FD, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
if (pinfo & INSN_WRITE_FPR_S)
- mask |= 1 << EXTRACT_OPERAND (FS, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
if (pinfo & INSN_WRITE_FPR_T)
- mask |= 1 << EXTRACT_OPERAND (FT, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
if (pinfo2 & INSN2_WRITE_FPR_Z)
- mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
+ mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
}
/* Conservatively treat all operands to an FP_D instruction are doubles.
(This is overly pessimistic for things like cvt.s.d.) */
/* If we're working around r7000 errata, there must be two instructions
between an mfhi or mflo and any instruction that uses the result. */
if (mips_7000_hilo_fix
+ && !mips_opts.micromips
&& MF_HILO_INSN (pinfo1)
- && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1)))
+ && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
return 2;
/* If we're working around 24K errata, one instruction is required
if an ERET or DERET is followed by a branch instruction. */
- if (mips_fix_24k)
+ if (mips_fix_24k && !mips_opts.micromips)
{
if (insn1->insn_opcode == INSN_ERET
|| insn1->insn_opcode == INSN_DERET)
/* If working around VR4120 errata, check for combinations that need
a single intervening instruction. */
- if (mips_fix_vr4120)
+ if (mips_fix_vr4120 && !mips_opts.micromips)
{
unsigned int class1, class2;
}
}
- if (!mips_opts.mips16)
+ if (!HAVE_CODE_COMPRESSION)
{
/* Check for GPR or coprocessor load delays. All such delays
are on the RT register. */
|| (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
{
know (pinfo1 & INSN_WRITE_GPR_T);
- if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1)))
+ if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
return 1;
}
nops = tmp_nops;
}
- if (mips_fix_vr4130)
+ if (mips_fix_vr4130 && !mips_opts.micromips)
{
tmp_nops = nops_for_vr4130 (ignore, hist, insn);
if (tmp_nops > nops)
nops = tmp_nops;
}
- if (mips_fix_24k)
+ if (mips_fix_24k && !mips_opts.micromips)
{
tmp_nops = nops_for_24k (ignore, hist, insn);
if (tmp_nops > nops)
static void
fix_loongson2f_nop (struct mips_cl_insn * ip)
{
+ gas_assert (!HAVE_CODE_COMPRESSION);
if (strcmp (ip->insn_mo->name, "nop") == 0)
ip->insn_opcode = LOONGSON2F_NOP_INSN;
}
static void
fix_loongson2f_jump (struct mips_cl_insn * ip)
{
+ gas_assert (!HAVE_CODE_COMPRESSION);
if (strcmp (ip->insn_mo->name, "j") == 0
|| strcmp (ip->insn_mo->name, "jr") == 0
|| strcmp (ip->insn_mo->name, "jalr") == 0)
if (! mips_opts.at)
return;
- sreg = EXTRACT_OPERAND (RS, *ip);
+ sreg = EXTRACT_OPERAND (0, RS, *ip);
if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
return;
static bfd_boolean
can_swap_branch_p (struct mips_cl_insn *ip)
{
- unsigned long pinfo, prev_pinfo;
+ unsigned long pinfo, pinfo2, prev_pinfo;
unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
+ /* For microMIPS, disable reordering. */
+ if (mips_opts.micromips)
+ return FALSE;
+
/* -O2 and above is required for this optimization. */
if (mips_optimize < 2)
return FALSE;
/* If the previous instruction is in a variant frag other than this
branch's one, we cannot do the swap. This does not apply to the
mips16, which uses variant frags for different purposes. */
- if (!mips_opts.mips16
+ if (!HAVE_CODE_COMPRESSION
&& history[0].frag
&& history[0].frag->fr_type == rs_machine_dependent)
return FALSE;
if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
return FALSE;
+ /* If the previous instruction has an incorrect size for a fixed
+ branch delay slot in microMIPS mode, we cannot swap. */
+ if (mips_opts.micromips)
+ {
+ pinfo2 = ip->insn_mo->pinfo;
+ if ((pinfo2 & INSN2_BRANCH_DELAY_16BIT)
+ && insn_length (history) != 2)
+ return FALSE;
+
+ if ((pinfo2 & INSN2_BRANCH_DELAY_32BIT)
+ && insn_length (history) != 4)
+ return FALSE;
+ }
return TRUE;
}
abort ();
}
+/* For microMIPS macros, we need to generate a local number label
+ as the target of branches. */
+#define MICROMIPS_LABEL_CHAR '\037'
+static unsigned long micromips_target_label;
+static char micromips_target_name[32];
+
+static char *
+micromips_label_name (void)
+{
+ char *p = micromips_target_name;
+ char symbol_name_temporary[24];
+ unsigned long l;
+ int i;
+
+ if (*p)
+ return p;
+
+ i = 0;
+ l = micromips_target_label;
+#ifdef LOCAL_LABEL_PREFIX
+ *p++ = LOCAL_LABEL_PREFIX;
+#endif
+ *p++ = 'L';
+ *p++ = MICROMIPS_LABEL_CHAR;
+ do
+ {
+ symbol_name_temporary[i++] = l % 10 + '0';
+ l /= 10;
+ }
+ while (l != 0);
+ while (i > 0)
+ *p++ = symbol_name_temporary[--i];
+ *p = '\0';
+
+ return micromips_target_name;
+}
+
+static void
+micromips_label_expr (expressionS *label_expr)
+{
+ label_expr->X_op = O_symbol;
+ label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
+ label_expr->X_add_number = 0;
+}
+
+static void
+micromips_label_inc (void)
+{
+ micromips_target_label++;
+ *micromips_target_name = '\0';
+}
+
+static void
+micromips_add_label (void)
+{
+ symbolS *s;
+
+ s = colon (micromips_label_name ());
+ micromips_label_inc ();
+#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
+ if (IS_ELF)
+ S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
+#endif
+}
+
+/* If assembling microMIPS code, then return the microMIPS reloc
+ corresponding to the requested one if any. Otherwise return
+ the reloc unchanged. */
+
+static bfd_reloc_code_real_type
+micromips_map_reloc (bfd_reloc_code_real_type reloc)
+{
+ static const bfd_reloc_code_real_type relocs[][2] =
+ {
+ /* Keep sorted incrementally by the left-hand key. */
+ { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
+ { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
+ { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
+ { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
+ { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
+ { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
+ { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
+ { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
+ { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
+ { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
+ { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
+ { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
+ { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
+ { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
+ { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
+ { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
+ { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
+ { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
+ { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
+ { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
+ { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
+ { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
+ { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
+ { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
+ { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
+ { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
+ { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
+ };
+ bfd_reloc_code_real_type r;
+ size_t i;
+
+ if (!mips_opts.micromips)
+ return reloc;
+ for (i = 0; i < ARRAY_SIZE (relocs); i++)
+ {
+ r = relocs[i][0];
+ if (r > reloc)
+ return reloc;
+ if (r == reloc)
+ return relocs[i][1];
+ }
+ return reloc;
+}
+
/* Output an instruction. IP is the instruction information.
ADDRESS_EXPR is an operand of the instruction to be used with
- RELOC_TYPE. */
+ RELOC_TYPE. EXPANSIONP is true if the instruction is part of
+ a macro expansion. */
static void
append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
- bfd_reloc_code_real_type *reloc_type)
+ bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
{
- unsigned long prev_pinfo, pinfo;
+ unsigned long prev_pinfo, prev_pinfo2, pinfo, pinfo2;
bfd_boolean relaxed_branch = FALSE;
+ bfd_boolean relax32;
enum append_method method;
- if (mips_fix_loongson2f)
+ if (mips_fix_loongson2f && !mips_opts.micromips)
fix_loongson2f (ip);
- /* Mark instruction labels in mips16 mode. */
- mips16_mark_labels ();
+ mips_mark_labels ();
file_ase_mips16 |= mips_opts.mips16;
+ file_ase_micromips |= mips_opts.micromips;
prev_pinfo = history[0].insn_mo->pinfo;
+ prev_pinfo2 = history[0].insn_mo->pinfo2;
pinfo = ip->insn_mo->pinfo;
+ pinfo2 = ip->insn_mo->pinfo2;
+
+ if (mips_opts.micromips
+ && !expansionp
+ && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
+ && micromips_insn_length (ip->insn_mo) != 2)
+ || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
+ && micromips_insn_length (ip->insn_mo) != 4)))
+ as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
+ (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
if (address_expr == NULL)
ip->complete_p = 1;
break;
case BFD_RELOC_MIPS_JMP:
- if ((address_expr->X_add_number & 3) != 0)
- as_bad (_("jump to misaligned address (0x%lx)"),
- (unsigned long) address_expr->X_add_number);
- ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
- ip->complete_p = 0;
+ {
+ int shift;
+
+ shift = mips_opts.micromips ? 1 : 2;
+ if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
+ as_bad (_("jump to misaligned address (0x%lx)"),
+ (unsigned long) address_expr->X_add_number);
+ ip->insn_opcode |= ((address_expr->X_add_number >> shift)
+ & 0x3ffffff);
+ ip->complete_p = 0;
+ }
break;
case BFD_RELOC_MIPS16_JMP:
break;
case BFD_RELOC_16_PCREL_S2:
- if ((address_expr->X_add_number & 3) != 0)
- as_bad (_("branch to misaligned address (0x%lx)"),
- (unsigned long) address_expr->X_add_number);
- if (!mips_relax_branch)
- {
- if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
- as_bad (_("branch address range overflow (0x%lx)"),
- (unsigned long) address_expr->X_add_number);
- ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
- }
- ip->complete_p = 0;
+ {
+ int shift;
+
+ shift = mips_opts.micromips ? 1 : 2;
+ if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
+ as_bad (_("branch to misaligned address (0x%lx)"),
+ (unsigned long) address_expr->X_add_number);
+ if (!mips_relax_branch)
+ {
+ if ((address_expr->X_add_number + (1 << (shift + 15)))
+ & ~((1 << (shift + 16)) - 1))
+ as_bad (_("branch address range overflow (0x%lx)"),
+ (unsigned long) address_expr->X_add_number);
+ ip->insn_opcode |= ((address_expr->X_add_number >> shift)
+ & 0xffff);
+ }
+ ip->complete_p = 0;
+ }
break;
default:
{
/* Allow this instruction to replace one of the nops that was
tentatively added to prev_nop_frag. */
- prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
+ prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
prev_nop_frag_holds--;
prev_nop_frag_since++;
}
should be recorded in the debug tables. This is normally the
current address.
- For MIPS16 debug info we want to use ISA-encoded addresses,
- so we use -1 for an address higher by one than the current one.
+ For MIPS16/microMIPS debug info we want to use ISA-encoded
+ addresses, so we use -1 for an address higher by one than the
+ current one.
If the instruction produced is a branch that we will swap with
the preceding instruction, then we add the displacement by which
the branch will be moved backwards. This is more appropriate
- and for MIPS16 code also prevents a debugger from placing a
- breakpoint in the middle of the branch (and corrupting code if
+ and for MIPS16/microMIPS code also prevents a debugger from placing
+ a breakpoint in the middle of the branch (and corrupting code if
software breakpoints are used). */
- dwarf2_emit_insn ((mips_opts.mips16 ? -1 : 0)
+ dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0)
+ (method == APPEND_SWAP ? insn_length (history) : 0));
#endif
- if (address_expr
+ relax32 = (mips_relax_branch
+ /* Don't try branch relaxation within .set nomacro, or within
+ .set noat if we use $at for PIC computations. If it turns
+ out that the branch was out-of-range, we'll get an error. */
+ && !mips_opts.warn_about_macros
+ && (mips_opts.at || mips_pic == NO_PIC)
+ /* Don't relax BPOSGE32/64 as they have no complementing
+ branches. */
+ && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
+ /* Don't try 32-bit branch relaxation when users specify
+ 16-bit/32-bit instructions. */
+ && !forced_insn_length);
+
+ if (!HAVE_CODE_COMPRESSION
+ && address_expr
+ && relax32
&& *reloc_type == BFD_RELOC_16_PCREL_S2
&& (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
- || pinfo & INSN_COND_BRANCH_LIKELY)
- && mips_relax_branch
- /* Don't try branch relaxation within .set nomacro, or within
- .set noat if we use $at for PIC computations. If it turns
- out that the branch was out-of-range, we'll get an error. */
- && !mips_opts.warn_about_macros
- && (mips_opts.at || mips_pic == NO_PIC)
- /* Don't relax BPOSGE32/64 as they have no complementing branches. */
- && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
- && !mips_opts.mips16)
+ || pinfo & INSN_COND_BRANCH_LIKELY))
{
relaxed_branch = TRUE;
add_relaxed_insn (ip, (relaxed_branch_length
address_expr->X_add_number);
*reloc_type = BFD_RELOC_UNUSED;
}
- else if (*reloc_type > BFD_RELOC_UNUSED)
+ else if (mips_opts.micromips
+ && address_expr
+ && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
+ || *reloc_type > BFD_RELOC_UNUSED)
+ && (pinfo & INSN_UNCOND_BRANCH_DELAY
+ || pinfo & INSN_COND_BRANCH_DELAY
+ || (pinfo2 & ~INSN2_ALIAS) == INSN2_UNCOND_BRANCH
+ || pinfo2 & INSN2_COND_BRANCH))
+ {
+ bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
+ int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
+ int uncond = (pinfo & INSN_UNCOND_BRANCH_DELAY
+ || pinfo2 & INSN2_UNCOND_BRANCH) ? -1 : 0;
+ int compact = pinfo2 & (INSN2_COND_BRANCH | INSN2_UNCOND_BRANCH);
+ int al = pinfo & INSN_WRITE_GPR_31;
+ int length32;
+
+ gas_assert (address_expr != NULL);
+ gas_assert (!mips_relax.sequence);
+
+ length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
+ add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
+ RELAX_MICROMIPS_ENCODE (type, AT,
+ forced_insn_length == 2,
+ uncond, compact, al, relax32,
+ 0, 0),
+ address_expr->X_add_symbol,
+ address_expr->X_add_number);
+ *reloc_type = BFD_RELOC_UNUSED;
+ }
+ else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
{
/* We need to set up a variant frag. */
- gas_assert (mips_opts.mips16 && address_expr != NULL);
+ gas_assert (address_expr != NULL);
add_relaxed_insn (ip, 4, 0,
RELAX_MIPS16_ENCODE
(*reloc_type - BFD_RELOC_UNUSED,
- mips16_small, mips16_ext,
+ forced_insn_length == 2, forced_insn_length == 4,
prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
history[0].mips16_absolute_jump_p),
make_expr_symbol (address_expr), 0);
written so far. */
if (frag_room () < 4)
relax_close_frag ();
- mips_relax.sizes[mips_relax.sequence - 1] += 4;
+ mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
}
if (mips_relax.sequence != 2)
- mips_macro_warning.sizes[0] += 4;
+ {
+ if (mips_macro_warning.first_insn_sizes[0] == 0)
+ mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
+ mips_macro_warning.sizes[0] += insn_length (ip);
+ mips_macro_warning.insns[0]++;
+ }
if (mips_relax.sequence != 1)
- mips_macro_warning.sizes[1] += 4;
+ {
+ if (mips_macro_warning.first_insn_sizes[1] == 0)
+ mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
+ mips_macro_warning.sizes[1] += insn_length (ip);
+ mips_macro_warning.insns[1]++;
+ }
if (mips_opts.mips16)
{
if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
{
+ bfd_reloc_code_real_type final_type[3];
reloc_howto_type *howto;
int i;
+ /* Perform any necessary conversion to microMIPS relocations
+ and find out how many relocations there actually are. */
+ for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
+ final_type[i] = micromips_map_reloc (reloc_type[i]);
+
/* In a compound relocation, it is the final (outermost)
operator that determines the relocated field. */
- for (i = 1; i < 3; i++)
- if (reloc_type[i] == BFD_RELOC_UNUSED)
- break;
-
- howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
+ howto = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
if (howto == NULL)
{
/* To reproduce this failure try assembling gas/testsuites/
gas/mips/mips16-intermix.s with a mips-ecoff targeted
assembler. */
- as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
+ as_bad (_("Unsupported MIPS relocation number %d"),
+ final_type[i - 1]);
howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
}
+ howto = bfd_reloc_type_lookup (stdoutput, final_type[0]);
ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
bfd_get_reloc_size (howto),
address_expr,
- reloc_type[0] == BFD_RELOC_16_PCREL_S2,
- reloc_type[0]);
+ howto->pc_relative, final_type[0]);
/* Tag symbols that have a R_MIPS16_26 relocation against them. */
if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
{
ip->fixp[i] = fix_new (ip->frag, ip->where,
ip->fixp[0]->fx_size, NULL, 0,
- FALSE, reloc_type[i]);
+ FALSE, final_type[i]);
/* Use fx_tcbit to mark compound relocs. */
ip->fixp[0]->fx_tcbit = 1;
case APPEND_ADD_WITH_NOP:
insert_into_history (0, 1, ip);
- emit_nop ();
- if (mips_relax.sequence)
- mips_relax.sizes[mips_relax.sequence - 1] += 4;
+ if (mips_opts.micromips
+ && (pinfo2 & INSN2_BRANCH_DELAY_32BIT))
+ {
+ add_fixed_insn (µmips_nop32_insn);
+ insert_into_history (0, 1, µmips_nop32_insn);
+ if (mips_relax.sequence)
+ mips_relax.sizes[mips_relax.sequence - 1] += 4;
+ }
+ else
+ {
+ emit_nop ();
+ if (mips_relax.sequence)
+ mips_relax.sizes[mips_relax.sequence - 1] += NOP_INSN_SIZE;
+ }
break;
case APPEND_ADD_COMPACT:
move_insn (ip, delay.frag, delay.where);
move_insn (&delay, ip->frag, ip->where + insn_length (ip));
}
+ else if (mips_opts.micromips)
+ {
+ /* We don't reorder for micromips. */
+ abort ();
+ }
else if (relaxed_branch)
{
/* Add the delay slot instruction to the end of the
&& (history[0].insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH)))
mips_no_prev_insn ();
+ /* We need to emit a label at the end of branch-likely macros. */
+ if (emit_branch_likely_macro)
+ {
+ emit_branch_likely_macro = FALSE;
+ micromips_add_label ();
+ }
+
/* We just output an insn, so the next one doesn't have a label. */
mips_clear_insn_labels ();
}
{
/* Record the frag which holds the nop instructions, so
that we can remove them if we don't need them. */
- frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
+ frag_grow (nops * NOP_INSN_SIZE);
prev_nop_frag = frag_now;
prev_nop_frag_holds = nops;
prev_nop_frag_required = 0;
frag_new (0);
mips_move_labels ();
}
- mips16_mark_labels ();
+ mips_mark_labels ();
mips_clear_insn_labels ();
}
mips_opts.noreorder++;
/* Commit to inserting prev_nop_frag_required nops and go back to
handling nop insertion the .set reorder way. */
prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
- * (mips_opts.mips16 ? 2 : 4));
+ * NOP_INSN_SIZE);
insert_into_history (prev_nop_frag_since,
prev_nop_frag_required, NOP_INSN);
prev_nop_frag = NULL;
macro_start (void)
{
memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
+ memset (&mips_macro_warning.first_insn_sizes, 0,
+ sizeof (mips_macro_warning.first_insn_sizes));
+ memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
mips_macro_warning.delay_slot_p = (mips_opts.noreorder
&& (history[0].insn_mo->pinfo
& (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
| INSN_COND_BRANCH_LIKELY)) != 0);
+ switch (history[0].insn_mo->pinfo2
+ & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
+ {
+ case INSN2_BRANCH_DELAY_32BIT:
+ mips_macro_warning.delay_slot_length = 4;
+ break;
+ case INSN2_BRANCH_DELAY_16BIT:
+ mips_macro_warning.delay_slot_length = 2;
+ break;
+ default:
+ mips_macro_warning.delay_slot_length = 0;
+ break;
+ }
+ mips_macro_warning.first_frag = NULL;
}
-/* Given that a macro is longer than 4 bytes, return the appropriate warning
- for it. Return null if no warning is needed. SUBTYPE is a bitmask of
- RELAX_DELAY_SLOT and RELAX_NOMACRO. */
+/* Given that a macro is longer than one instruction or of the wrong size,
+ return the appropriate warning for it. Return null if no warning is
+ needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
+ RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
+ and RELAX_NOMACRO. */
static const char *
macro_warning (relax_substateT subtype)
" in a branch delay slot");
else if (subtype & RELAX_NOMACRO)
return _("Macro instruction expanded into multiple instructions");
+ else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
+ | RELAX_DELAY_SLOT_SIZE_SECOND))
+ return ((subtype & RELAX_DELAY_SLOT_16BIT)
+ ? _("Macro instruction expanded into a wrong size instruction"
+ " in a 16-bit branch delay slot")
+ : _("Macro instruction expanded into a wrong size instruction"
+ " in a 32-bit branch delay slot"));
else
return 0;
}
static void
macro_end (void)
{
- if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
+ /* Relaxation warning flags. */
+ relax_substateT subtype = 0;
+
+ /* Check delay slot size requirements. */
+ if (mips_macro_warning.delay_slot_length == 2)
+ subtype |= RELAX_DELAY_SLOT_16BIT;
+ if (mips_macro_warning.delay_slot_length != 0)
{
- relax_substateT subtype;
+ if (mips_macro_warning.delay_slot_length
+ != mips_macro_warning.first_insn_sizes[0])
+ subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
+ if (mips_macro_warning.delay_slot_length
+ != mips_macro_warning.first_insn_sizes[1])
+ subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
+ }
- /* Set up the relaxation warning flags. */
- subtype = 0;
- if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
+ /* Check instruction count requirements. */
+ if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
+ {
+ if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
subtype |= RELAX_SECOND_LONGER;
if (mips_opts.warn_about_macros)
subtype |= RELAX_NOMACRO;
if (mips_macro_warning.delay_slot_p)
subtype |= RELAX_DELAY_SLOT;
+ }
- if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
- {
- /* Either the macro has a single implementation or both
- implementations are longer than 4 bytes. Emit the
- warning now. */
- const char *msg = macro_warning (subtype);
- if (msg != 0)
- as_warn ("%s", msg);
- }
- else
- {
- /* One implementation might need a warning but the other
- definitely doesn't. */
- mips_macro_warning.first_frag->fr_subtype |= subtype;
- }
+ /* If both alternatives fail to fill a delay slot correctly,
+ emit the warning now. */
+ if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
+ && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
+ {
+ relax_substateT s;
+ const char *msg;
+
+ s = subtype & (RELAX_DELAY_SLOT_16BIT
+ | RELAX_DELAY_SLOT_SIZE_FIRST
+ | RELAX_DELAY_SLOT_SIZE_SECOND);
+ msg = macro_warning (s);
+ if (msg != NULL)
+ as_warn ("%s", msg);
+ subtype &= ~s;
+ }
+
+ /* If both implementations are longer than 1 instruction, then emit the
+ warning now. */
+ if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
+ {
+ relax_substateT s;
+ const char *msg;
+
+ s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
+ msg = macro_warning (s);
+ if (msg != NULL)
+ as_warn ("%s", msg);
+ subtype &= ~s;
}
+
+ /* If any flags still set, then one implementation might need a warning
+ and the other either will need one of a different kind or none at all.
+ Pass any remaining flags over to relaxation. */
+ if (mips_macro_warning.first_frag != NULL)
+ mips_macro_warning.first_frag->fr_subtype |= subtype;
}
+/* Instruction operand formats used in macros that vary between
+ standard MIPS and microMIPS code. */
+
+static const char * const brk_fmt[2] = { "c", "mF" };
+static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
+static const char * const jalr_fmt[2] = { "d,s", "t,s" };
+static const char * const lui_fmt[2] = { "t,u", "s,u" };
+static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
+static const char * const mfhl_fmt[2] = { "d", "mj" };
+static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
+static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
+
+#define BRK_FMT (brk_fmt[mips_opts.micromips])
+#define COP12_FMT (cop12_fmt[mips_opts.micromips])
+#define JALR_FMT (jalr_fmt[mips_opts.micromips])
+#define LUI_FMT (lui_fmt[mips_opts.micromips])
+#define MEM12_FMT (mem12_fmt[mips_opts.micromips])
+#define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
+#define SHFT_FMT (shft_fmt[mips_opts.micromips])
+#define TRAP_FMT (trap_fmt[mips_opts.micromips])
+
/* Read a macro's relocation codes from *ARGS and store them in *R.
The first argument in *ARGS will be either the code for a single
relocation or -1 followed by the three codes that make up a
static void
macro_build (expressionS *ep, const char *name, const char *fmt, ...)
{
- const struct mips_opcode *mo;
- struct mips_cl_insn insn;
+ const struct mips_opcode *mo = NULL;
bfd_reloc_code_real_type r[3];
+ const struct mips_opcode *amo;
+ struct hash_control *hash;
+ struct mips_cl_insn insn;
va_list args;
va_start (args, fmt);
r[0] = BFD_RELOC_UNUSED;
r[1] = BFD_RELOC_UNUSED;
r[2] = BFD_RELOC_UNUSED;
- mo = (struct mips_opcode *) hash_find (op_hash, name);
- gas_assert (mo);
- gas_assert (strcmp (name, mo->name) == 0);
+ hash = mips_opts.micromips ? micromips_op_hash : op_hash;
+ amo = (struct mips_opcode *) hash_find (hash, name);
+ gas_assert (amo);
+ gas_assert (strcmp (name, amo->name) == 0);
- while (1)
+ do
{
/* Search until we get a match for NAME. It is assumed here that
- macros will never generate MDMX, MIPS-3D, or MT instructions. */
- if (strcmp (fmt, mo->args) == 0
- && mo->pinfo != INSN_MACRO
- && is_opcode_valid (mo))
- break;
+ macros will never generate MDMX, MIPS-3D, or MT instructions.
+ We try to match an instruction that fulfils the branch delay
+ slot instruction length requirement (if any) of the previous
+ instruction. While doing this we record the first instruction
+ seen that matches all the other conditions and use it anyway
+ if the requirement cannot be met; we will issue an appropriate
+ warning later on. */
+ if (strcmp (fmt, amo->args) == 0
+ && amo->pinfo != INSN_MACRO
+ && is_opcode_valid (amo)
+ && is_size_valid (amo))
+ {
+ if (is_delay_slot_valid (amo))
+ {
+ mo = amo;
+ break;
+ }
+ else if (!mo)
+ mo = amo;
+ }
- ++mo;
- gas_assert (mo->name);
- gas_assert (strcmp (name, mo->name) == 0);
+ ++amo;
+ gas_assert (amo->name);
}
+ while (strcmp (name, amo->name) == 0);
+ gas_assert (mo);
create_insn (&insn, mo);
for (;;)
{
{
case 'A':
case 'E':
- INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
+ INSERT_OPERAND (mips_opts.micromips,
+ EXTLSB, insn, va_arg (args, int));
continue;
case 'B':
in MSB form. (When handling the instruction in the
non-macro case, these arguments are sizes from which
MSB values must be calculated.) */
- INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
+ INSERT_OPERAND (mips_opts.micromips,
+ INSMSB, insn, va_arg (args, int));
continue;
case 'C':
in MSBD form. (When handling the instruction in the
non-macro case, these arguments are sizes from which
MSBD values must be calculated.) */
- INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
+ INSERT_OPERAND (mips_opts.micromips,
+ EXTMSBD, insn, va_arg (args, int));
continue;
case 'Q':
- INSERT_OPERAND (SEQI, insn, va_arg (args, int));
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
continue;
default:
continue;
case '2':
- INSERT_OPERAND (BP, insn, va_arg (args, int));
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, BP, insn, va_arg (args, int));
continue;
+ case 'n':
+ gas_assert (mips_opts.micromips);
case 't':
case 'w':
case 'E':
- INSERT_OPERAND (RT, insn, va_arg (args, int));
+ INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
continue;
case 'c':
- INSERT_OPERAND (CODE, insn, va_arg (args, int));
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
continue;
- case 'T':
case 'W':
- INSERT_OPERAND (FT, insn, va_arg (args, int));
+ gas_assert (!mips_opts.micromips);
+ case 'T':
+ INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
continue;
- case 'd':
case 'G':
+ if (mips_opts.micromips)
+ INSERT_OPERAND (1, RS, insn, va_arg (args, int));
+ else
+ INSERT_OPERAND (0, RD, insn, va_arg (args, int));
+ continue;
+
case 'K':
- INSERT_OPERAND (RD, insn, va_arg (args, int));
+ gas_assert (!mips_opts.micromips);
+ case 'd':
+ INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
continue;
case 'U':
+ gas_assert (!mips_opts.micromips);
{
int tmp = va_arg (args, int);
- INSERT_OPERAND (RT, insn, tmp);
- INSERT_OPERAND (RD, insn, tmp);
- continue;
+ INSERT_OPERAND (0, RT, insn, tmp);
+ INSERT_OPERAND (0, RD, insn, tmp);
}
+ continue;
case 'V':
case 'S':
- INSERT_OPERAND (FS, insn, va_arg (args, int));
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, FS, insn, va_arg (args, int));
continue;
case 'z':
continue;
case '<':
- INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
+ INSERT_OPERAND (mips_opts.micromips,
+ SHAMT, insn, va_arg (args, int));
continue;
case 'D':
- INSERT_OPERAND (FD, insn, va_arg (args, int));
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, FD, insn, va_arg (args, int));
continue;
case 'B':
- INSERT_OPERAND (CODE20, insn, va_arg (args, int));
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
continue;
case 'J':
- INSERT_OPERAND (CODE19, insn, va_arg (args, int));
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
continue;
case 'q':
- INSERT_OPERAND (CODE2, insn, va_arg (args, int));
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
continue;
case 'b':
case 's':
case 'r':
case 'v':
- INSERT_OPERAND (RS, insn, va_arg (args, int));
+ INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
continue;
case 'i':
*/
if (ep->X_op == O_constant)
{
+ /* For microMIPS we always use relocations for branches.
+ So we should not resolve immediate values. */
+ gas_assert (!mips_opts.micromips);
+
if ((ep->X_add_number & 3) != 0)
as_bad (_("branch to misaligned address (0x%lx)"),
(unsigned long) ep->X_add_number);
continue;
case 'C':
- INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
continue;
case 'k':
- INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
+ INSERT_OPERAND (mips_opts.micromips,
+ CACHE, insn, va_arg (args, unsigned long));
+ continue;
+
+ case '|':
+ gas_assert (mips_opts.micromips);
+ INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
+ continue;
+
+ case '.':
+ gas_assert (mips_opts.micromips);
+ INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
+ continue;
+
+ case '~':
+ gas_assert (mips_opts.micromips);
+ INSERT_OPERAND (1, OFFSET12, insn, va_arg (args, unsigned long));
+ continue;
+
+ case 'N':
+ gas_assert (mips_opts.micromips);
+ INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
+ continue;
+
+ case 'm': /* Opcode extension character. */
+ gas_assert (mips_opts.micromips);
+ switch (*fmt++)
+ {
+ case 'j':
+ INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
+ break;
+
+ case 'p':
+ INSERT_OPERAND (1, MP, insn, va_arg (args, int));
+ break;
+
+ case 'F':
+ INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
+ break;
+
+ default:
+ internalError ();
+ }
continue;
default:
va_end (args);
gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
- append_insn (&insn, ep, r);
+ append_insn (&insn, ep, r, TRUE);
}
static void
gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
- append_insn (&insn, ep, r);
+ append_insn (&insn, ep, r, TRUE);
}
/*
* function. This occurs in NewABI PIC code.
*/
static void
-macro_build_jalr (expressionS *ep)
+macro_build_jalr (expressionS *ep, int cprestore)
{
+ static const bfd_reloc_code_real_type jalr_relocs[2]
+ = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
+ bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
+ const char *jalr;
char *f = NULL;
if (MIPS_JALR_HINT_P (ep))
frag_grow (8);
f = frag_more (0);
}
- macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
+ if (!mips_opts.micromips)
+ macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
+ else
+ {
+ jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
+ if (MIPS_JALR_HINT_P (ep))
+ macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
+ else
+ macro_build (NULL, jalr, "mj", PIC_CALL_REG);
+ }
if (MIPS_JALR_HINT_P (ep))
- fix_new_exp (frag_now, f - frag_now->fr_literal,
- 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
+ fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
}
/*
static void
macro_build_lui (expressionS *ep, int regnum)
{
- expressionS high_expr;
- const struct mips_opcode *mo;
- struct mips_cl_insn insn;
- bfd_reloc_code_real_type r[3]
- = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
- const char *name = "lui";
- const char *fmt = "t,u";
-
gas_assert (! mips_opts.mips16);
- high_expr = *ep;
-
- if (high_expr.X_op == O_constant)
- {
- /* We can compute the instruction now without a relocation entry. */
- high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
- >> 16) & 0xffff;
- *r = BFD_RELOC_UNUSED;
- }
- else
+ if (ep->X_op != O_constant)
{
gas_assert (ep->X_op == O_symbol);
/* _gp_disp is a special case, used from s_cpload.
|| (! mips_in_shared
&& strcmp (S_GET_NAME (ep->X_add_symbol),
"__gnu_local_gp") == 0));
- *r = BFD_RELOC_HI16_S;
}
- mo = hash_find (op_hash, name);
- gas_assert (strcmp (name, mo->name) == 0);
- gas_assert (strcmp (fmt, mo->args) == 0);
- create_insn (&insn, mo);
-
- insn.insn_opcode = insn.insn_mo->match;
- INSERT_OPERAND (RT, insn, regnum);
- if (*r == BFD_RELOC_UNUSED)
- {
- insn.insn_opcode |= high_expr.X_add_number;
- append_insn (&insn, NULL, r);
- }
- else
- append_insn (&insn, &high_expr, r);
+ macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
}
/* Generate a sequence of instructions to do a load or store from a constant
else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
{
/* 32 bit values require an lui. */
- macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
+ macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
if ((ep->X_add_number & 0xffff) != 0)
macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
return;
}
if (lo32.X_add_number & 0x80000000)
{
- macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
+ macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
if (lo32.X_add_number & 0xffff)
macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
return;
else
tmp.X_add_number = hi32.X_add_number >> (shift - 32);
macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
- macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
+ macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
reg, reg, (shift >= 32) ? shift - 32 : shift);
return;
}
if (bit != 0)
{
bit += shift;
- macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
+ macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
reg, reg, (bit >= 32) ? bit - 32 : bit);
}
- macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
+ macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
reg, reg, (shift >= 32) ? shift - 32 : shift);
return;
}
{
if (freg != 0)
{
- macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
+ macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
freg = reg;
}
}
if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
{
- macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
- macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
+ macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
+ macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
return;
}
if (freg != 0)
{
- macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
+ macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
freg = reg;
}
mid16 = lo32;
mid16.X_add_number >>= 16;
macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
- macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
+ macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
freg = reg;
}
if ((lo32.X_add_number & 0xffff) != 0)
if (*used_at == 0 && mips_opts.at)
{
- macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
- macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
+ macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
+ macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
macro_build (ep, "daddiu", "t,r,j", reg, reg,
BFD_RELOC_MIPS_HIGHER);
macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
- macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
+ macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
*used_at = 1;
}
else
{
- macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
+ macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
macro_build (ep, "daddiu", "t,r,j", reg, reg,
BFD_RELOC_MIPS_HIGHER);
- macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
+ macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
- macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
+ macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
}
ex.X_add_number = ep->X_add_number;
ep->X_add_number = 0;
relax_start (ep->X_add_symbol);
- macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
+ macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
reg, reg, mips_gp_register);
macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
ex.X_add_number = ep->X_add_number;
ep->X_add_number = 0;
relax_start (ep->X_add_symbol);
- macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
+ macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
reg, reg, mips_gp_register);
macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
static void
move_register (int dest, int source)
{
- macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
- dest, source, 0);
+ /* Prefer to use a 16-bit microMIPS instruction unless the previous
+ instruction specifically requires a 32-bit one. */
+ if (mips_opts.micromips
+ && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
+ macro_build (NULL, "move", "mp,mj", dest, source );
+ else
+ macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
+ dest, source, 0);
}
/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
}
+/* Emit a sequence of instructions to emulate a branch likely operation.
+ BR is an ordinary branch corresponding to one to be emulated. BRNEG
+ is its complementing branch with the original condition negated.
+ CALL is set if the original branch specified the link operation.
+ EP, FMT, SREG and TREG specify the usual macro_build() parameters.
+
+ Code like this is produced in the noreorder mode:
+
+ BRNEG <args>, 1f
+ nop
+ b <sym>
+ delay slot (executed only if branch taken)
+ 1:
+
+ or, if CALL is set:
+
+ BRNEG <args>, 1f
+ nop
+ bal <sym>
+ delay slot (executed only if branch taken)
+ 1:
+
+ In the reorder mode the delay slot would be filled with a nop anyway,
+ so code produced is simply:
+
+ BR <args>, <sym>
+ nop
+
+ This function is used when producing code for the microMIPS ASE that
+ does not implement branch likely instructions in hardware. */
+
+static void
+macro_build_branch_likely (const char *br, const char *brneg,
+ int call, expressionS *ep, const char *fmt,
+ unsigned int sreg, unsigned int treg)
+{
+ int noreorder = mips_opts.noreorder;
+ expressionS expr1;
+
+ gas_assert (mips_opts.micromips);
+ start_noreorder ();
+ if (noreorder)
+ {
+ micromips_label_expr (&expr1);
+ macro_build (&expr1, brneg, fmt, sreg, treg);
+ macro_build (NULL, "nop", "");
+ macro_build (ep, call ? "bal" : "b", "p");
+
+ /* Set to true so that append_insn adds a label. */
+ emit_branch_likely_macro = TRUE;
+ }
+ else
+ {
+ macro_build (ep, br, fmt, sreg, treg);
+ macro_build (NULL, "nop", "");
+ }
+ end_noreorder ();
+}
+
+/* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
+ the condition code tested. EP specifies the branch target. */
+
+static void
+macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
+{
+ const int call = 0;
+ const char *brneg;
+ const char *br;
+
+ switch (type)
+ {
+ case M_BC1FL:
+ br = "bc1f";
+ brneg = "bc1t";
+ break;
+ case M_BC1TL:
+ br = "bc1t";
+ brneg = "bc1f";
+ break;
+ case M_BC2FL:
+ br = "bc2f";
+ brneg = "bc2t";
+ break;
+ case M_BC2TL:
+ br = "bc2t";
+ brneg = "bc2f";
+ break;
+ default:
+ abort ();
+ }
+ macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
+}
+
+/* Emit a two-argument branch macro specified by TYPE, using SREG as
+ the register tested. EP specifies the branch target. */
+
+static void
+macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
+{
+ const char *brneg = NULL;
+ const char *br;
+ int call = 0;
+
+ switch (type)
+ {
+ case M_BGEZ:
+ br = "bgez";
+ break;
+ case M_BGEZL:
+ br = mips_opts.micromips ? "bgez" : "bgezl";
+ brneg = "bltz";
+ break;
+ case M_BGEZALL:
+ gas_assert (mips_opts.micromips);
+ br = "bgezals";
+ brneg = "bltz";
+ call = 1;
+ break;
+ case M_BGTZ:
+ br = "bgtz";
+ break;
+ case M_BGTZL:
+ br = mips_opts.micromips ? "bgtz" : "bgtzl";
+ brneg = "blez";
+ break;
+ case M_BLEZ:
+ br = "blez";
+ break;
+ case M_BLEZL:
+ br = mips_opts.micromips ? "blez" : "blezl";
+ brneg = "bgtz";
+ break;
+ case M_BLTZ:
+ br = "bltz";
+ break;
+ case M_BLTZL:
+ br = mips_opts.micromips ? "bltz" : "bltzl";
+ brneg = "bgez";
+ break;
+ case M_BLTZALL:
+ gas_assert (mips_opts.micromips);
+ br = "bltzals";
+ brneg = "bgez";
+ call = 1;
+ break;
+ default:
+ abort ();
+ }
+ if (mips_opts.micromips && brneg)
+ macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
+ else
+ macro_build (ep, br, "s,p", sreg);
+}
+
+/* Emit a three-argument branch macro specified by TYPE, using SREG and
+ TREG as the registers tested. EP specifies the branch target. */
+
+static void
+macro_build_branch_rsrt (int type, expressionS *ep,
+ unsigned int sreg, unsigned int treg)
+{
+ const char *brneg = NULL;
+ const int call = 0;
+ const char *br;
+
+ switch (type)
+ {
+ case M_BEQ:
+ case M_BEQ_I:
+ br = "beq";
+ break;
+ case M_BEQL:
+ case M_BEQL_I:
+ br = mips_opts.micromips ? "beq" : "beql";
+ brneg = "bne";
+ break;
+ case M_BNE:
+ case M_BNE_I:
+ br = "bne";
+ break;
+ case M_BNEL:
+ case M_BNEL_I:
+ br = mips_opts.micromips ? "bne" : "bnel";
+ brneg = "beq";
+ break;
+ default:
+ abort ();
+ }
+ if (mips_opts.micromips && brneg)
+ macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
+ else
+ macro_build (ep, br, "s,t,p", sreg, treg);
+}
+
/*
* Build macros
* This routine implements the seemingly endless macro or synthesized
unsigned int tempreg;
int mask;
int used_at = 0;
+ expressionS label_expr;
expressionS expr1;
+ expressionS *ep;
const char *s;
const char *s2;
const char *fmt;
int likely = 0;
- int dbl = 0;
int coproc = 0;
- int lr = 0;
- int imm = 0;
+ int off12 = 0;
int call = 0;
+ int jals = 0;
+ int dbl = 0;
+ int imm = 0;
+ int ust = 0;
+ int lp = 0;
+ int ab = 0;
int off;
offsetT maxnum;
bfd_reloc_code_real_type r;
gas_assert (! mips_opts.mips16);
- treg = EXTRACT_OPERAND (RT, *ip);
- dreg = EXTRACT_OPERAND (RD, *ip);
- sreg = breg = EXTRACT_OPERAND (RS, *ip);
+ treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
+ dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
+ sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
mask = ip->insn_mo->mask;
+ label_expr.X_op = O_constant;
+ label_expr.X_op_symbol = NULL;
+ label_expr.X_add_symbol = NULL;
+ label_expr.X_add_number = 0;
+
expr1.X_op = O_constant;
expr1.X_op_symbol = NULL;
expr1.X_add_symbol = NULL;
case M_DABS:
dbl = 1;
case M_ABS:
- /* bgez $a0,.+12
- move v0,$a0
- sub v0,$zero,$a0
- */
+ /* bgez $a0,1f
+ move v0,$a0
+ sub v0,$zero,$a0
+ 1:
+ */
start_noreorder ();
- expr1.X_add_number = 8;
- macro_build (&expr1, "bgez", "s,p", sreg);
+ if (mips_opts.micromips)
+ micromips_label_expr (&label_expr);
+ else
+ label_expr.X_add_number = 8;
+ macro_build (&label_expr, "bgez", "s,p", sreg);
if (dreg == sreg)
macro_build (NULL, "nop", "");
else
move_register (dreg, sreg);
macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
+ if (mips_opts.micromips)
+ micromips_add_label ();
end_noreorder ();
break;
dbl = 1;
s = "daddi";
s2 = "dadd";
- goto do_addi;
+ if (!mips_opts.micromips)
+ goto do_addi;
+ if (imm_expr.X_op == O_constant
+ && imm_expr.X_add_number >= -0x200
+ && imm_expr.X_add_number < 0x200)
+ {
+ macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
+ break;
+ }
+ goto do_addi_i;
case M_DADDU_I:
dbl = 1;
s = "daddiu";
macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
break;
}
+ do_addi_i:
used_at = 1;
load_register (AT, &imm_expr, dbl);
macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
}
break;
+ case M_BC1FL:
+ case M_BC1TL:
+ case M_BC2FL:
+ case M_BC2TL:
+ gas_assert (mips_opts.micromips);
+ macro_build_branch_ccl (mask, &offset_expr,
+ EXTRACT_OPERAND (1, BCC, *ip));
+ break;
+
case M_BEQ_I:
- s = "beq";
- goto beq_i;
case M_BEQL_I:
- s = "beql";
- likely = 1;
- goto beq_i;
case M_BNE_I:
- s = "bne";
- goto beq_i;
case M_BNEL_I:
- s = "bnel";
- likely = 1;
- beq_i:
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
+ treg = 0;
+ else
{
- macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
- break;
+ treg = AT;
+ used_at = 1;
+ load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
}
- used_at = 1;
- load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (&offset_expr, s, "s,t,p", sreg, AT);
+ /* Fall through. */
+ case M_BEQL:
+ case M_BNEL:
+ macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
break;
case M_BGEL:
likely = 1;
case M_BGE:
if (treg == 0)
+ macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
+ else if (sreg == 0)
+ macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
+ else
{
- macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
- break;
- }
- if (sreg == 0)
- {
- macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
- break;
+ used_at = 1;
+ macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
+ macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
+ &offset_expr, AT, ZERO);
}
- used_at = 1;
- macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
- macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
+ break;
+
+ case M_BGEZL:
+ case M_BGEZALL:
+ case M_BGTZL:
+ case M_BLEZL:
+ case M_BLTZL:
+ case M_BLTZALL:
+ macro_build_branch_rs (mask, &offset_expr, sreg);
break;
case M_BGTL_I:
if (! likely)
macro_build (NULL, "nop", "");
else
- macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
+ macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
break;
}
if (imm_expr.X_op != O_constant)
likely = 1;
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
- macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
+ macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
+ &offset_expr, sreg);
break;
}
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
{
- macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
+ macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
+ &offset_expr, sreg);
break;
}
maxnum = 0x7fffffff;
}
used_at = 1;
set_at (sreg, 0);
- macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
+ macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
+ &offset_expr, AT, ZERO);
break;
case M_BGEUL:
case M_BGEU:
if (treg == 0)
goto do_true;
- if (sreg == 0)
+ else if (sreg == 0)
+ macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
+ &offset_expr, ZERO, treg);
+ else
{
- macro_build (&offset_expr, likely ? "beql" : "beq",
- "s,t,p", ZERO, treg);
- break;
+ used_at = 1;
+ macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
+ macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
+ &offset_expr, AT, ZERO);
}
- used_at = 1;
- macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
- macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
break;
case M_BGTUL_I:
likely = 1;
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
goto do_true;
- if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
+ else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
+ macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
+ &offset_expr, sreg, ZERO);
+ else
{
- macro_build (&offset_expr, likely ? "bnel" : "bne",
- "s,t,p", sreg, ZERO);
- break;
+ used_at = 1;
+ set_at (sreg, 1);
+ macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
+ &offset_expr, AT, ZERO);
}
- used_at = 1;
- set_at (sreg, 1);
- macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
break;
case M_BGTL:
likely = 1;
case M_BGT:
if (treg == 0)
+ macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
+ else if (sreg == 0)
+ macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
+ else
{
- macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
- break;
+ used_at = 1;
+ macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
+ macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
+ &offset_expr, AT, ZERO);
}
- if (sreg == 0)
- {
- macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
- break;
- }
- used_at = 1;
- macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
- macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
break;
case M_BGTUL:
likely = 1;
case M_BGTU:
if (treg == 0)
+ macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
+ &offset_expr, sreg, ZERO);
+ else if (sreg == 0)
+ goto do_false;
+ else
{
- macro_build (&offset_expr, likely ? "bnel" : "bne",
- "s,t,p", sreg, ZERO);
- break;
+ used_at = 1;
+ macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
+ macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
+ &offset_expr, AT, ZERO);
}
- if (sreg == 0)
- goto do_false;
- used_at = 1;
- macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
- macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
break;
case M_BLEL:
likely = 1;
case M_BLE:
if (treg == 0)
+ macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
+ else if (sreg == 0)
+ macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
+ else
{
- macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
- break;
- }
- if (sreg == 0)
- {
- macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
- break;
+ used_at = 1;
+ macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
+ macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
+ &offset_expr, AT, ZERO);
}
- used_at = 1;
- macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
- macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
break;
case M_BLEL_I:
if (mask == M_BLTL_I)
likely = 1;
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
+ macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
+ else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
+ macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
+ else
{
- macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
- break;
- }
- if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
- {
- macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
- break;
+ used_at = 1;
+ set_at (sreg, 0);
+ macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
+ &offset_expr, AT, ZERO);
}
- used_at = 1;
- set_at (sreg, 0);
- macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
break;
case M_BLEUL:
likely = 1;
case M_BLEU:
if (treg == 0)
+ macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
+ &offset_expr, sreg, ZERO);
+ else if (sreg == 0)
+ goto do_true;
+ else
{
- macro_build (&offset_expr, likely ? "beql" : "beq",
- "s,t,p", sreg, ZERO);
- break;
+ used_at = 1;
+ macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
+ macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
+ &offset_expr, AT, ZERO);
}
- if (sreg == 0)
- goto do_true;
- used_at = 1;
- macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
- macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
break;
case M_BLEUL_I:
likely = 1;
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
goto do_false;
- if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
+ else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
+ macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
+ &offset_expr, sreg, ZERO);
+ else
{
- macro_build (&offset_expr, likely ? "beql" : "beq",
- "s,t,p", sreg, ZERO);
- break;
+ used_at = 1;
+ set_at (sreg, 1);
+ macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
+ &offset_expr, AT, ZERO);
}
- used_at = 1;
- set_at (sreg, 1);
- macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
break;
case M_BLTL:
likely = 1;
case M_BLT:
if (treg == 0)
+ macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
+ else if (sreg == 0)
+ macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
+ else
{
- macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
- break;
- }
- if (sreg == 0)
- {
- macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
- break;
+ used_at = 1;
+ macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
+ macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
+ &offset_expr, AT, ZERO);
}
- used_at = 1;
- macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
- macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
break;
case M_BLTUL:
case M_BLTU:
if (treg == 0)
goto do_false;
- if (sreg == 0)
+ else if (sreg == 0)
+ macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
+ &offset_expr, ZERO, treg);
+ else
{
- macro_build (&offset_expr, likely ? "bnel" : "bne",
- "s,t,p", ZERO, treg);
- break;
+ used_at = 1;
+ macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
+ macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
+ &offset_expr, AT, ZERO);
}
- used_at = 1;
- macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
- macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
break;
case M_DEXT:
{
as_warn (_("Divide by zero."));
if (mips_trap)
- macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
+ macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
else
- macro_build (NULL, "break", "c", 7);
+ macro_build (NULL, "break", BRK_FMT, 7);
break;
}
start_noreorder ();
if (mips_trap)
{
- macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
+ macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
}
else
{
- expr1.X_add_number = 8;
- macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
+ if (mips_opts.micromips)
+ micromips_label_expr (&label_expr);
+ else
+ label_expr.X_add_number = 8;
+ macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
- macro_build (NULL, "break", "c", 7);
+ macro_build (NULL, "break", BRK_FMT, 7);
+ if (mips_opts.micromips)
+ micromips_add_label ();
}
expr1.X_add_number = -1;
used_at = 1;
load_register (AT, &expr1, dbl);
- expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
- macro_build (&expr1, "bne", "s,t,p", treg, AT);
+ if (mips_opts.micromips)
+ micromips_label_expr (&label_expr);
+ else
+ label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
+ macro_build (&label_expr, "bne", "s,t,p", treg, AT);
if (dbl)
{
expr1.X_add_number = 1;
load_register (AT, &expr1, dbl);
- macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
+ macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
}
else
{
expr1.X_add_number = 0x80000000;
- macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
+ macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
}
if (mips_trap)
{
- macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
+ macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
/* We want to close the noreorder block as soon as possible, so
that later insns are available for delay slot filling. */
end_noreorder ();
}
else
{
- expr1.X_add_number = 8;
- macro_build (&expr1, "bne", "s,t,p", sreg, AT);
+ if (mips_opts.micromips)
+ micromips_label_expr (&label_expr);
+ else
+ label_expr.X_add_number = 8;
+ macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
macro_build (NULL, "nop", "");
/* We want to close the noreorder block as soon as possible, so
that later insns are available for delay slot filling. */
end_noreorder ();
- macro_build (NULL, "break", "c", 6);
+ macro_build (NULL, "break", BRK_FMT, 6);
}
- macro_build (NULL, s, "d", dreg);
+ if (mips_opts.micromips)
+ micromips_add_label ();
+ macro_build (NULL, s, MFHL_FMT, dreg);
break;
case M_DIV_3I:
{
as_warn (_("Divide by zero."));
if (mips_trap)
- macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
+ macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
else
- macro_build (NULL, "break", "c", 7);
+ macro_build (NULL, "break", BRK_FMT, 7);
break;
}
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
used_at = 1;
load_register (AT, &imm_expr, dbl);
macro_build (NULL, s, "z,s,t", sreg, AT);
- macro_build (NULL, s2, "d", dreg);
+ macro_build (NULL, s2, MFHL_FMT, dreg);
break;
case M_DIVU_3:
start_noreorder ();
if (mips_trap)
{
- macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
+ macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
macro_build (NULL, s, "z,s,t", sreg, treg);
/* We want to close the noreorder block as soon as possible, so
that later insns are available for delay slot filling. */
}
else
{
- expr1.X_add_number = 8;
- macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
+ if (mips_opts.micromips)
+ micromips_label_expr (&label_expr);
+ else
+ label_expr.X_add_number = 8;
+ macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
macro_build (NULL, s, "z,s,t", sreg, treg);
/* We want to close the noreorder block as soon as possible, so
that later insns are available for delay slot filling. */
end_noreorder ();
- macro_build (NULL, "break", "c", 7);
+ macro_build (NULL, "break", BRK_FMT, 7);
+ if (mips_opts.micromips)
+ micromips_add_label ();
}
- macro_build (NULL, s2, "d", dreg);
+ macro_build (NULL, s2, MFHL_FMT, dreg);
break;
case M_DLCA_AB:
if (used_at == 0 && mips_opts.at)
{
- macro_build (&offset_expr, "lui", "t,u",
+ macro_build (&offset_expr, "lui", LUI_FMT,
tempreg, BFD_RELOC_MIPS_HIGHEST);
- macro_build (&offset_expr, "lui", "t,u",
+ macro_build (&offset_expr, "lui", LUI_FMT,
AT, BFD_RELOC_HI16_S);
macro_build (&offset_expr, "daddiu", "t,r,j",
tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
macro_build (&offset_expr, "daddiu", "t,r,j",
AT, AT, BFD_RELOC_LO16);
- macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
+ macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
used_at = 1;
}
else
{
- macro_build (&offset_expr, "lui", "t,u",
+ macro_build (&offset_expr, "lui", LUI_FMT,
tempreg, BFD_RELOC_MIPS_HIGHEST);
macro_build (&offset_expr, "daddiu", "t,r,j",
tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
- macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
+ macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
macro_build (&offset_expr, "daddiu", "t,r,j",
tempreg, tempreg, BFD_RELOC_HI16_S);
- macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
+ macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
macro_build (&offset_expr, "daddiu", "t,r,j",
tempreg, tempreg, BFD_RELOC_LO16);
}
lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
}
- macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
+ macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, mips_gp_register);
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
}
- macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
+ macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, mips_gp_register);
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
break;
case M_MSGSND:
+ gas_assert (!mips_opts.micromips);
{
unsigned long temp = (treg << 16) | (0x01);
macro_build (NULL, "c2", "C", temp);
break;
case M_MSGLD:
+ gas_assert (!mips_opts.micromips);
{
unsigned long temp = (0x02);
macro_build (NULL, "c2", "C", temp);
break;
case M_MSGLD_T:
+ gas_assert (!mips_opts.micromips);
{
unsigned long temp = (treg << 16) | (0x02);
macro_build (NULL, "c2", "C", temp);
break;
case M_MSGWAIT:
+ gas_assert (!mips_opts.micromips);
macro_build (NULL, "c2", "C", 3);
break;
case M_MSGWAIT_T:
+ gas_assert (!mips_opts.micromips);
{
unsigned long temp = (treg << 16) | 0x03;
macro_build (NULL, "c2", "C", temp);
/* The jal instructions must be handled as macros because when
generating PIC code they expand to multi-instruction
sequences. Normally they are simple instructions. */
+ case M_JALS_1:
+ dreg = RA;
+ /* Fall through. */
+ case M_JALS_2:
+ gas_assert (mips_opts.micromips);
+ jals = 1;
+ goto jal;
case M_JAL_1:
dreg = RA;
/* Fall through. */
case M_JAL_2:
+ jal:
if (mips_pic == NO_PIC)
- macro_build (NULL, "jalr", "d,s", dreg, sreg);
+ {
+ s = jals ? "jalrs" : "jalr";
+ if (mips_opts.micromips && dreg == RA)
+ macro_build (NULL, s, "mj", sreg);
+ else
+ macro_build (NULL, s, JALR_FMT, dreg, sreg);
+ }
else
{
+ int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
+ && mips_cprestore_offset >= 0);
+
if (sreg != PIC_CALL_REG)
as_warn (_("MIPS PIC call to register other than $25"));
- macro_build (NULL, "jalr", "d,s", dreg, sreg);
+ s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
+ ? "jalrs" : "jalr");
+ if (mips_opts.micromips && dreg == RA)
+ macro_build (NULL, s, "mj", sreg);
+ else
+ macro_build (NULL, s, JALR_FMT, dreg, sreg);
if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
{
if (mips_cprestore_offset < 0)
break;
+ case M_JALS_A:
+ gas_assert (mips_opts.micromips);
+ jals = 1;
+ /* Fall through. */
case M_JAL_A:
if (mips_pic == NO_PIC)
- macro_build (&offset_expr, "jal", "a");
+ macro_build (&offset_expr, jals ? "jals" : "jal", "a");
else if (mips_pic == SVR4_PIC)
{
/* If this is a reference to an external symbol, and we are
else
{
relax_start (offset_expr.X_add_symbol);
- macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
+ macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
BFD_RELOC_MIPS_CALL_HI16);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
PIC_CALL_REG, mips_gp_register);
relax_end ();
}
- macro_build_jalr (&offset_expr);
+ macro_build_jalr (&offset_expr, 0);
}
else
{
int gpdelay;
gpdelay = reg_needs_delay (mips_gp_register);
- macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
+ macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
BFD_RELOC_MIPS_CALL_HI16);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
PIC_CALL_REG, mips_gp_register);
macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
relax_end ();
- macro_build_jalr (&offset_expr);
+ macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
if (mips_cprestore_offset < 0)
as_warn (_("No .cprestore pseudo-op used in PIC code"));
break;
case M_LB_AB:
+ ab = 1;
s = "lb";
+ fmt = "t,o(b)";
goto ld;
case M_LBU_AB:
+ ab = 1;
s = "lbu";
+ fmt = "t,o(b)";
goto ld;
case M_LH_AB:
+ ab = 1;
s = "lh";
+ fmt = "t,o(b)";
goto ld;
case M_LHU_AB:
+ ab = 1;
s = "lhu";
+ fmt = "t,o(b)";
goto ld;
case M_LW_AB:
+ ab = 1;
s = "lw";
+ fmt = "t,o(b)";
goto ld;
case M_LWC0_AB:
+ ab = 1;
+ gas_assert (!mips_opts.micromips);
s = "lwc0";
+ fmt = "E,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
- goto ld;
+ goto ld_st;
case M_LWC1_AB:
+ ab = 1;
s = "lwc1";
+ fmt = "T,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
- goto ld;
+ goto ld_st;
case M_LWC2_AB:
+ ab = 1;
+ case M_LWC2_OB:
s = "lwc2";
+ fmt = COP12_FMT;
+ off12 = mips_opts.micromips;
/* Itbl support may require additional care here. */
coproc = 1;
- goto ld;
+ goto ld_st;
case M_LWC3_AB:
+ ab = 1;
+ gas_assert (!mips_opts.micromips);
s = "lwc3";
+ fmt = "E,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
- goto ld;
+ goto ld_st;
case M_LWL_AB:
+ ab = 1;
+ case M_LWL_OB:
s = "lwl";
- lr = 1;
- goto ld;
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_LWR_AB:
+ ab = 1;
+ case M_LWR_OB:
s = "lwr";
- lr = 1;
- goto ld;
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_LDC1_AB:
+ ab = 1;
s = "ldc1";
+ fmt = "T,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
- goto ld;
+ goto ld_st;
case M_LDC2_AB:
+ ab = 1;
+ case M_LDC2_OB:
s = "ldc2";
+ fmt = COP12_FMT;
+ off12 = mips_opts.micromips;
/* Itbl support may require additional care here. */
coproc = 1;
- goto ld;
+ goto ld_st;
case M_LDC3_AB:
+ ab = 1;
s = "ldc3";
+ fmt = "E,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
- goto ld;
+ goto ld_st;
case M_LDL_AB:
+ ab = 1;
+ case M_LDL_OB:
s = "ldl";
- lr = 1;
- goto ld;
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_LDR_AB:
+ ab = 1;
+ case M_LDR_OB:
s = "ldr";
- lr = 1;
- goto ld;
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_LL_AB:
+ ab = 1;
+ case M_LL_OB:
s = "ll";
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
goto ld;
case M_LLD_AB:
+ ab = 1;
+ case M_LLD_OB:
s = "lld";
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
goto ld;
case M_LWU_AB:
+ ab = 1;
+ case M_LWU_OB:
s = "lwu";
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld;
+ case M_LWP_AB:
+ ab = 1;
+ case M_LWP_OB:
+ gas_assert (mips_opts.micromips);
+ s = "lwp";
+ fmt = "t,~(b)";
+ off12 = 1;
+ lp = 1;
+ goto ld;
+ case M_LDP_AB:
+ ab = 1;
+ case M_LDP_OB:
+ gas_assert (mips_opts.micromips);
+ s = "ldp";
+ fmt = "t,~(b)";
+ off12 = 1;
+ lp = 1;
+ goto ld;
+ case M_LWM_AB:
+ ab = 1;
+ case M_LWM_OB:
+ gas_assert (mips_opts.micromips);
+ s = "lwm";
+ fmt = "n,~(b)";
+ off12 = 1;
+ goto ld_st;
+ case M_LDM_AB:
+ ab = 1;
+ case M_LDM_OB:
+ gas_assert (mips_opts.micromips);
+ s = "ldm";
+ fmt = "n,~(b)";
+ off12 = 1;
+ goto ld_st;
+
ld:
- if (breg == treg || coproc || lr)
- {
- tempreg = AT;
- used_at = 1;
- }
+ if (breg == treg + lp)
+ goto ld_st;
else
- {
- tempreg = treg;
- }
- goto ld_st;
+ tempreg = treg + lp;
+ goto ld_noat;
+
case M_SB_AB:
+ ab = 1;
s = "sb";
- goto st;
+ fmt = "t,o(b)";
+ goto ld_st;
case M_SH_AB:
+ ab = 1;
s = "sh";
- goto st;
+ fmt = "t,o(b)";
+ goto ld_st;
case M_SW_AB:
+ ab = 1;
s = "sw";
- goto st;
+ fmt = "t,o(b)";
+ goto ld_st;
case M_SWC0_AB:
+ ab = 1;
+ gas_assert (!mips_opts.micromips);
s = "swc0";
+ fmt = "E,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
- goto st;
+ goto ld_st;
case M_SWC1_AB:
+ ab = 1;
s = "swc1";
+ fmt = "T,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
- goto st;
+ goto ld_st;
case M_SWC2_AB:
+ ab = 1;
+ case M_SWC2_OB:
s = "swc2";
+ fmt = COP12_FMT;
+ off12 = mips_opts.micromips;
/* Itbl support may require additional care here. */
coproc = 1;
- goto st;
+ goto ld_st;
case M_SWC3_AB:
+ ab = 1;
+ gas_assert (!mips_opts.micromips);
s = "swc3";
+ fmt = "E,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
- goto st;
+ goto ld_st;
case M_SWL_AB:
+ ab = 1;
+ case M_SWL_OB:
s = "swl";
- goto st;
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_SWR_AB:
+ ab = 1;
+ case M_SWR_OB:
s = "swr";
- goto st;
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_SC_AB:
+ ab = 1;
+ case M_SC_OB:
s = "sc";
- goto st;
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_SCD_AB:
+ ab = 1;
+ case M_SCD_OB:
s = "scd";
- goto st;
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_CACHE_AB:
+ ab = 1;
+ case M_CACHE_OB:
s = "cache";
- goto st;
+ fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_PREF_AB:
+ ab = 1;
+ case M_PREF_OB:
s = "pref";
- goto st;
+ fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_SDC1_AB:
+ ab = 1;
s = "sdc1";
+ fmt = "T,o(b)";
coproc = 1;
/* Itbl support may require additional care here. */
- goto st;
+ goto ld_st;
case M_SDC2_AB:
+ ab = 1;
+ case M_SDC2_OB:
s = "sdc2";
+ fmt = COP12_FMT;
+ off12 = mips_opts.micromips;
/* Itbl support may require additional care here. */
coproc = 1;
- goto st;
+ goto ld_st;
case M_SDC3_AB:
+ ab = 1;
+ gas_assert (!mips_opts.micromips);
s = "sdc3";
+ fmt = "E,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
- goto st;
+ goto ld_st;
case M_SDL_AB:
+ ab = 1;
+ case M_SDL_OB:
s = "sdl";
- goto st;
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld_st;
case M_SDR_AB:
+ ab = 1;
+ case M_SDR_OB:
s = "sdr";
- st:
+ fmt = MEM12_FMT;
+ off12 = mips_opts.micromips;
+ goto ld_st;
+ case M_SWP_AB:
+ ab = 1;
+ case M_SWP_OB:
+ gas_assert (mips_opts.micromips);
+ s = "swp";
+ fmt = "t,~(b)";
+ off12 = 1;
+ goto ld_st;
+ case M_SDP_AB:
+ ab = 1;
+ case M_SDP_OB:
+ gas_assert (mips_opts.micromips);
+ s = "sdp";
+ fmt = "t,~(b)";
+ off12 = 1;
+ goto ld_st;
+ case M_SWM_AB:
+ ab = 1;
+ case M_SWM_OB:
+ gas_assert (mips_opts.micromips);
+ s = "swm";
+ fmt = "n,~(b)";
+ off12 = 1;
+ goto ld_st;
+ case M_SDM_AB:
+ ab = 1;
+ case M_SDM_OB:
+ gas_assert (mips_opts.micromips);
+ s = "sdm";
+ fmt = "n,~(b)";
+ off12 = 1;
+
+ ld_st:
tempreg = AT;
used_at = 1;
- ld_st:
+ ld_noat:
if (coproc
&& NO_ISA_COP (mips_opts.arch)
&& (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
break;
}
- /* Itbl support may require additional care here. */
- if (mask == M_LWC1_AB
- || mask == M_SWC1_AB
- || mask == M_LDC1_AB
- || mask == M_SDC1_AB
- || mask == M_L_DAB
- || mask == M_S_DAB)
- fmt = "T,o(b)";
- else if (mask == M_CACHE_AB || mask == M_PREF_AB)
- fmt = "k,o(b)";
- else if (coproc)
- fmt = "E,o(b)";
- else
- fmt = "t,o(b)";
-
if (offset_expr.X_op != O_constant
&& offset_expr.X_op != O_symbol)
{
is in non PIC code. */
if (offset_expr.X_op == O_constant)
{
+ int hipart = 0;
+
expr1.X_add_number = offset_expr.X_add_number;
normalize_address_expr (&expr1);
- if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
+ if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
{
expr1.X_add_number = ((expr1.X_add_number + 0x8000)
& ~(bfd_vma) 0xffff);
+ hipart = 1;
+ }
+ else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
+ {
+ expr1.X_add_number = ((expr1.X_add_number + 0x800)
+ & ~(bfd_vma) 0xfff);
+ hipart = 1;
+ }
+ if (hipart)
+ {
load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
if (breg != 0)
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, breg);
breg = tempreg;
}
- macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
+ if (!off12)
+ macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
+ else
+ macro_build (NULL, s, fmt,
+ treg, (unsigned long) offset_expr.X_add_number, breg);
+ }
+ else if (off12)
+ {
+ /* A 12-bit offset field is too narrow to be used for a low-part
+ relocation, so load the whole address into the auxillary
+ register. In the case of "A(b)" addresses, we first load
+ absolute address "A" into the register and then add base
+ register "b". In the case of "o(b)" addresses, we simply
+ need to add 16-bit offset "o" to base register "b", and
+ offset_reloc already contains the relocations associated
+ with "o". */
+ if (ab)
+ {
+ load_address (tempreg, &offset_expr, &used_at);
+ if (breg != 0)
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
+ tempreg, tempreg, breg);
+ }
+ else
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+ tempreg, breg, -1,
+ offset_reloc[0], offset_reloc[1], offset_reloc[2]);
+ expr1.X_add_number = 0;
+ macro_build (NULL, s, fmt,
+ treg, (unsigned long) expr1.X_add_number, tempreg);
}
else if (mips_pic == NO_PIC)
{
if (used_at == 0 && mips_opts.at)
{
- macro_build (&offset_expr, "lui", "t,u", tempreg,
+ macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
BFD_RELOC_MIPS_HIGHEST);
- macro_build (&offset_expr, "lui", "t,u", AT,
+ macro_build (&offset_expr, "lui", LUI_FMT, AT,
BFD_RELOC_HI16_S);
macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
tempreg, BFD_RELOC_MIPS_HIGHER);
if (breg != 0)
macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
- macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
+ macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
tempreg);
}
else
{
- macro_build (&offset_expr, "lui", "t,u", tempreg,
+ macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
BFD_RELOC_MIPS_HIGHEST);
macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
tempreg, BFD_RELOC_MIPS_HIGHER);
- macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
+ macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
tempreg, BFD_RELOC_HI16_S);
- macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
+ macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
if (breg != 0)
macro_build (NULL, "daddu", "d,v,t",
tempreg, tempreg, breg);
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
gpdelay = reg_needs_delay (mips_gp_register);
relax_start (offset_expr.X_add_symbol);
- macro_build (&offset_expr, "lui", "t,u", tempreg,
+ macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
BFD_RELOC_MIPS_GOT_HI16);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
mips_gp_register);
|| expr1.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
relax_start (offset_expr.X_add_symbol);
- macro_build (&offset_expr, "lui", "t,u", tempreg,
+ macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
BFD_RELOC_MIPS_GOT_HI16);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
mips_gp_register);
s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
if (strcmp (s, ".lit8") == 0)
{
- if (mips_opts.isa != ISA_MIPS1)
+ if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
{
macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
BFD_RELOC_MIPS_LITERAL, mips_gp_register);
macro_build_lui (&offset_expr, AT);
}
- if (mips_opts.isa != ISA_MIPS1)
+ if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
{
macro_build (&offset_expr, "ldc1", "T,o(b)",
treg, BFD_RELOC_LO16, AT);
to adjust when loading from memory. */
r = BFD_RELOC_LO16;
dob:
+ gas_assert (!mips_opts.micromips);
gas_assert (mips_opts.isa == ISA_MIPS1);
macro_build (&offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg + 1 : treg, r, breg);
break;
case M_S_DOB:
+ gas_assert (!mips_opts.micromips);
gas_assert (mips_opts.isa == ISA_MIPS1);
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when storing to memory. */
break;
case M_L_DAB:
+ gas_assert (!mips_opts.micromips);
/*
* The MIPS assembler seems to check for X_add_number not
* being double aligned and generating:
*/
/* Itbl support may require additional care here. */
coproc = 1;
+ fmt = "T,o(b)";
if (mips_opts.isa != ISA_MIPS1)
{
s = "ldc1";
- goto ld;
+ goto ld_st;
}
-
s = "lwc1";
- fmt = "T,o(b)";
goto ldd_std;
case M_S_DAB:
+ gas_assert (!mips_opts.micromips);
+ /* Itbl support may require additional care here. */
+ coproc = 1;
+ fmt = "T,o(b)";
if (mips_opts.isa != ISA_MIPS1)
{
s = "sdc1";
- goto st;
+ goto ld_st;
}
-
s = "swc1";
- fmt = "T,o(b)";
- /* Itbl support may require additional care here. */
- coproc = 1;
goto ldd_std;
case M_LD_AB:
+ fmt = "t,o(b)";
if (HAVE_64BIT_GPRS)
{
s = "ld";
goto ld;
}
-
s = "lw";
- fmt = "t,o(b)";
goto ldd_std;
case M_SD_AB:
+ fmt = "t,o(b)";
if (HAVE_64BIT_GPRS)
{
s = "sd";
- goto st;
+ goto ld_st;
}
-
s = "sw";
- fmt = "t,o(b)";
ldd_std:
if (offset_expr.X_op != O_symbol
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
gpdelay = reg_needs_delay (mips_gp_register);
relax_start (offset_expr.X_add_symbol);
- macro_build (&offset_expr, "lui", "t,u",
+ macro_build (&offset_expr, "lui", LUI_FMT,
AT, BFD_RELOC_MIPS_GOT_HI16);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
AT, AT, mips_gp_register);
case M_COP3:
s = "c3";
copz:
+ gas_assert (!mips_opts.micromips);
if (NO_ISA_COP (mips_opts.arch)
&& (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
{
dbl = 1;
case M_MUL:
macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
- macro_build (NULL, "mflo", "d", dreg);
+ macro_build (NULL, "mflo", MFHL_FMT, dreg);
break;
case M_DMUL_I:
used_at = 1;
load_register (AT, &imm_expr, dbl);
macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
- macro_build (NULL, "mflo", "d", dreg);
+ macro_build (NULL, "mflo", MFHL_FMT, dreg);
break;
case M_DMULO_I:
if (imm)
load_register (AT, &imm_expr, dbl);
macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
- macro_build (NULL, "mflo", "d", dreg);
- macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
- macro_build (NULL, "mfhi", "d", AT);
+ macro_build (NULL, "mflo", MFHL_FMT, dreg);
+ macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
+ macro_build (NULL, "mfhi", MFHL_FMT, AT);
if (mips_trap)
- macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
+ macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
else
{
- expr1.X_add_number = 8;
- macro_build (&expr1, "beq", "s,t,p", dreg, AT);
+ if (mips_opts.micromips)
+ micromips_label_expr (&label_expr);
+ else
+ label_expr.X_add_number = 8;
+ macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
macro_build (NULL, "nop", "");
- macro_build (NULL, "break", "c", 6);
+ macro_build (NULL, "break", BRK_FMT, 6);
+ if (mips_opts.micromips)
+ micromips_add_label ();
}
end_noreorder ();
- macro_build (NULL, "mflo", "d", dreg);
+ macro_build (NULL, "mflo", MFHL_FMT, dreg);
break;
case M_DMULOU_I:
load_register (AT, &imm_expr, dbl);
macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
sreg, imm ? AT : treg);
- macro_build (NULL, "mfhi", "d", AT);
- macro_build (NULL, "mflo", "d", dreg);
+ macro_build (NULL, "mfhi", MFHL_FMT, AT);
+ macro_build (NULL, "mflo", MFHL_FMT, dreg);
if (mips_trap)
- macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
+ macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
else
{
- expr1.X_add_number = 8;
- macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
+ if (mips_opts.micromips)
+ micromips_label_expr (&label_expr);
+ else
+ label_expr.X_add_number = 8;
+ macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
macro_build (NULL, "nop", "");
- macro_build (NULL, "break", "c", 6);
+ macro_build (NULL, "break", BRK_FMT, 6);
+ if (mips_opts.micromips)
+ micromips_add_label ();
}
end_noreorder ();
break;
{
rot = (64 - rot) & 0x3f;
if (rot >= 32)
- macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
+ macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
else
- macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
+ macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
break;
}
if (rot == 0)
{
- macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
+ macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
break;
}
l = (rot < 0x20) ? "dsll" : "dsll32";
rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
rot &= 0x1f;
used_at = 1;
- macro_build (NULL, l, "d,w,<", AT, sreg, rot);
- macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
+ macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
}
break;
rot = imm_expr.X_add_number & 0x1f;
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
{
- macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
+ macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
break;
}
if (rot == 0)
{
- macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
+ macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
break;
}
used_at = 1;
- macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
- macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
+ macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
}
break;
if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
{
if (rot >= 32)
- macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
+ macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
else
- macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
+ macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
break;
}
if (rot == 0)
{
- macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
+ macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
break;
}
rr = (rot < 0x20) ? "dsrl" : "dsrl32";
l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
rot &= 0x1f;
used_at = 1;
- macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
- macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
+ macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
}
break;
rot = imm_expr.X_add_number & 0x1f;
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
{
- macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
+ macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
break;
}
if (rot == 0)
{
- macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
+ macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
break;
}
used_at = 1;
- macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
- macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
+ macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
}
break;
macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
break;
+ case M_SUB_I:
+ s = "addi";
+ s2 = "sub";
+ goto do_subi;
+ case M_SUBU_I:
+ s = "addiu";
+ s2 = "subu";
+ goto do_subi;
case M_DSUB_I:
dbl = 1;
- case M_SUB_I:
+ s = "daddi";
+ s2 = "dsub";
+ if (!mips_opts.micromips)
+ goto do_subi;
if (imm_expr.X_op == O_constant
- && imm_expr.X_add_number > -0x8000
- && imm_expr.X_add_number <= 0x8000)
+ && imm_expr.X_add_number > -0x200
+ && imm_expr.X_add_number <= 0x200)
{
- imm_expr.X_add_number = -imm_expr.X_add_number;
- macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
- dreg, sreg, BFD_RELOC_LO16);
+ macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
break;
}
- used_at = 1;
- load_register (AT, &imm_expr, dbl);
- macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
- break;
-
+ goto do_subi_i;
case M_DSUBU_I:
dbl = 1;
- case M_SUBU_I:
+ s = "daddiu";
+ s2 = "dsubu";
+ do_subi:
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number > -0x8000
&& imm_expr.X_add_number <= 0x8000)
{
imm_expr.X_add_number = -imm_expr.X_add_number;
- macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
- dreg, sreg, BFD_RELOC_LO16);
+ macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
break;
}
+ do_subi_i:
used_at = 1;
load_register (AT, &imm_expr, dbl);
- macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
+ macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
break;
case M_TEQ_I:
case M_TRUNCWS:
case M_TRUNCWD:
+ gas_assert (!mips_opts.micromips);
gas_assert (mips_opts.isa == ISA_MIPS1);
used_at = 1;
sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
end_noreorder ();
break;
+ case M_ULH_A:
+ ab = 1;
case M_ULH:
s = "lb";
- goto ulh;
+ s2 = "lbu";
+ off = 1;
+ goto uld_st;
+ case M_ULHU_A:
+ ab = 1;
case M_ULHU:
s = "lbu";
- ulh:
- used_at = 1;
- if (offset_expr.X_add_number >= 0x7fff)
- as_bad (_("Operand overflow"));
- if (!target_big_endian)
- ++offset_expr.X_add_number;
- macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
- if (!target_big_endian)
- --offset_expr.X_add_number;
- else
- ++offset_expr.X_add_number;
- macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
- macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
- macro_build (NULL, "or", "d,v,t", treg, treg, AT);
- break;
-
+ s2 = "lbu";
+ off = 1;
+ goto uld_st;
+ case M_ULW_A:
+ ab = 1;
+ case M_ULW:
+ s = "lwl";
+ s2 = "lwr";
+ off12 = mips_opts.micromips;
+ off = 3;
+ goto uld_st;
+ case M_ULD_A:
+ ab = 1;
case M_ULD:
s = "ldl";
s2 = "ldr";
+ off12 = mips_opts.micromips;
off = 7;
- goto ulw;
- case M_ULW:
- s = "lwl";
- s2 = "lwr";
+ goto uld_st;
+ case M_USH_A:
+ ab = 1;
+ case M_USH:
+ s = "sb";
+ s2 = "sb";
+ off = 1;
+ ust = 1;
+ goto uld_st;
+ case M_USW_A:
+ ab = 1;
+ case M_USW:
+ s = "swl";
+ s2 = "swr";
+ off12 = mips_opts.micromips;
off = 3;
- ulw:
- if (offset_expr.X_add_number >= 0x8000 - off)
+ ust = 1;
+ goto uld_st;
+ case M_USD_A:
+ ab = 1;
+ case M_USD:
+ s = "sdl";
+ s2 = "sdr";
+ off12 = mips_opts.micromips;
+ off = 7;
+ ust = 1;
+
+ uld_st:
+ if (!ab && offset_expr.X_add_number >= 0x8000 - off)
as_bad (_("Operand overflow"));
- if (treg != breg)
- tempreg = treg;
- else
+
+ ep = &offset_expr;
+ expr1.X_add_number = 0;
+ if (ab)
+ {
+ used_at = 1;
+ tempreg = AT;
+ load_address (tempreg, ep, &used_at);
+ if (breg != 0)
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
+ tempreg, tempreg, breg);
+ breg = tempreg;
+ tempreg = treg;
+ ep = &expr1;
+ }
+ else if (off12
+ && (offset_expr.X_op != O_constant
+ || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
+ || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
+ {
+ used_at = 1;
+ tempreg = AT;
+ macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
+ -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
+ breg = tempreg;
+ tempreg = treg;
+ ep = &expr1;
+ }
+ else if (!ust && treg == breg)
{
used_at = 1;
tempreg = AT;
}
- if (!target_big_endian)
- offset_expr.X_add_number += off;
- macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
- if (!target_big_endian)
- offset_expr.X_add_number -= off;
else
- offset_expr.X_add_number += off;
- macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
+ tempreg = treg;
- /* If necessary, move the result in tempreg to the final destination. */
- if (treg == tempreg)
- break;
- /* Protect second load's delay slot. */
- load_delay_nop ();
- move_register (treg, tempreg);
- break;
+ if (off == 1)
+ goto ulh_sh;
- case M_ULD_A:
- s = "ldl";
- s2 = "ldr";
- off = 7;
- goto ulwa;
- case M_ULW_A:
- s = "lwl";
- s2 = "lwr";
- off = 3;
- ulwa:
- used_at = 1;
- load_address (AT, &offset_expr, &used_at);
- if (breg != 0)
- macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
if (!target_big_endian)
- expr1.X_add_number = off;
+ ep->X_add_number += off;
+ if (!off12)
+ macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
else
- expr1.X_add_number = 0;
- macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
+ macro_build (NULL, s, "t,~(b)",
+ tempreg, (unsigned long) ep->X_add_number, breg);
+
if (!target_big_endian)
- expr1.X_add_number = 0;
+ ep->X_add_number -= off;
else
- expr1.X_add_number = off;
- macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
- break;
+ ep->X_add_number += off;
+ if (!off12)
+ macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
+ else
+ macro_build (NULL, s2, "t,~(b)",
+ tempreg, (unsigned long) ep->X_add_number, breg);
- case M_ULH_A:
- case M_ULHU_A:
- used_at = 1;
- load_address (AT, &offset_expr, &used_at);
- if (breg != 0)
- macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
- if (target_big_endian)
- expr1.X_add_number = 0;
- macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
- treg, BFD_RELOC_LO16, AT);
- if (target_big_endian)
- expr1.X_add_number = 1;
- else
- expr1.X_add_number = 0;
- macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
- macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
- macro_build (NULL, "or", "d,v,t", treg, treg, AT);
- break;
-
- case M_USH:
- used_at = 1;
- if (offset_expr.X_add_number >= 0x7fff)
- as_bad (_("Operand overflow"));
- if (target_big_endian)
- ++offset_expr.X_add_number;
- macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
- macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
- if (target_big_endian)
- --offset_expr.X_add_number;
- else
- ++offset_expr.X_add_number;
- macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
- break;
-
- case M_USD:
- s = "sdl";
- s2 = "sdr";
- off = 7;
- goto usw;
- case M_USW:
- s = "swl";
- s2 = "swr";
- off = 3;
- usw:
- if (offset_expr.X_add_number >= 0x8000 - off)
- as_bad (_("Operand overflow"));
- if (!target_big_endian)
- offset_expr.X_add_number += off;
- macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
- if (!target_big_endian)
- offset_expr.X_add_number -= off;
- else
- offset_expr.X_add_number += off;
- macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
+ /* If necessary, move the result in tempreg to the final destination. */
+ if (!ust && treg != tempreg)
+ {
+ /* Protect second load's delay slot. */
+ load_delay_nop ();
+ move_register (treg, tempreg);
+ }
break;
- case M_USD_A:
- s = "sdl";
- s2 = "sdr";
- off = 7;
- goto uswa;
- case M_USW_A:
- s = "swl";
- s2 = "swr";
- off = 3;
- uswa:
+ ulh_sh:
used_at = 1;
- load_address (AT, &offset_expr, &used_at);
- if (breg != 0)
- macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
- if (!target_big_endian)
- expr1.X_add_number = off;
- else
- expr1.X_add_number = 0;
- macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
- if (!target_big_endian)
- expr1.X_add_number = 0;
+ if (target_big_endian == ust)
+ ep->X_add_number += off;
+ tempreg = ust || ab ? treg : AT;
+ macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
+
+ /* For halfword transfers we need a temporary register to shuffle
+ bytes. Unfortunately for M_USH_A we have none available before
+ the next store as AT holds the base address. We deal with this
+ case by clobbering TREG and then restoring it as with ULH. */
+ tempreg = ust == ab ? treg : AT;
+ if (ust)
+ macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
+
+ if (target_big_endian == ust)
+ ep->X_add_number -= off;
else
- expr1.X_add_number = off;
- macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
- break;
+ ep->X_add_number += off;
+ macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
- case M_USH_A:
- used_at = 1;
- load_address (AT, &offset_expr, &used_at);
- if (breg != 0)
- macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
- if (!target_big_endian)
- expr1.X_add_number = 0;
- macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
- macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
- if (!target_big_endian)
- expr1.X_add_number = 1;
- else
- expr1.X_add_number = 0;
- macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
- if (!target_big_endian)
- expr1.X_add_number = 0;
- else
- expr1.X_add_number = 1;
- macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
- macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
- macro_build (NULL, "or", "d,v,t", treg, treg, AT);
+ /* For M_USH_A re-retrieve the LSB. */
+ if (ust && ab)
+ {
+ if (target_big_endian)
+ ep->X_add_number += off;
+ else
+ ep->X_add_number -= off;
+ macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
+ }
+ /* For ULH and M_USH_A OR the LSB in. */
+ if (!ust || ab)
+ {
+ tempreg = !ab ? AT : treg;
+ macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
+ macro_build (NULL, "or", "d,v,t", treg, treg, AT);
+ }
break;
default:
return 1;
}
+/* For consistency checking, verify that the length implied matches the
+ major opcode and that all bits are specified either by the match/mask
+ part of the instruction definition, or by the operand list. */
+
+static int
+validate_micromips_insn (const struct mips_opcode *opc)
+{
+ unsigned long match = opc->match;
+ unsigned long mask = opc->mask;
+ const char *p = opc->args;
+ unsigned long insn_bits;
+ unsigned long used_bits;
+ unsigned long major;
+ unsigned int length;
+ char e;
+ char c;
+
+ if ((mask & match) != match)
+ {
+ as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
+ opc->name, opc->args);
+ return 0;
+ }
+ length = micromips_insn_length (opc);
+ if (length != 2 && length != 4)
+ {
+ as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
+ "%s %s"), length, opc->name, opc->args);
+ return 0;
+ }
+ major = match >> (10 + 8 * (length - 2));
+ if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
+ || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
+ {
+ as_bad (_("Internal error: bad microMIPS opcode "
+ "(opcode/length mismatch): %s %s"), opc->name, opc->args);
+ return 0;
+ }
+
+ /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
+ insn_bits = 1 << 4 * length;
+ insn_bits <<= 4 * length;
+ insn_bits -= 1;
+ used_bits = mask;
+#define USE_BITS(field) \
+ (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
+ while (*p)
+ switch (c = *p++)
+ {
+ case ',': break;
+ case '(': break;
+ case ')': break;
+ case '+':
+ e = c;
+ switch (c = *p++)
+ {
+ case 'A': USE_BITS (EXTLSB); break;
+ case 'B': USE_BITS (INSMSB); break;
+ case 'C': USE_BITS (EXTMSBD); break;
+ case 'D': USE_BITS (RS); USE_BITS (SEL); break;
+ case 'E': USE_BITS (EXTLSB); break;
+ case 'F': USE_BITS (INSMSB); break;
+ case 'G': USE_BITS (EXTMSBD); break;
+ case 'H': USE_BITS (EXTMSBD); break;
+ default:
+ as_bad (_("Internal error: bad mips opcode "
+ "(unknown extension operand type `%c%c'): %s %s"),
+ e, c, opc->name, opc->args);
+ return 0;
+ }
+ break;
+ case 'm':
+ e = c;
+ switch (c = *p++)
+ {
+ case 'A': USE_BITS (IMMA); break;
+ case 'B': USE_BITS (IMMB); break;
+ case 'C': USE_BITS (IMMC); break;
+ case 'D': USE_BITS (IMMD); break;
+ case 'E': USE_BITS (IMME); break;
+ case 'F': USE_BITS (IMMF); break;
+ case 'G': USE_BITS (IMMG); break;
+ case 'H': USE_BITS (IMMH); break;
+ case 'I': USE_BITS (IMMI); break;
+ case 'J': USE_BITS (IMMJ); break;
+ case 'L': USE_BITS (IMML); break;
+ case 'M': USE_BITS (IMMM); break;
+ case 'N': USE_BITS (IMMN); break;
+ case 'O': USE_BITS (IMMO); break;
+ case 'P': USE_BITS (IMMP); break;
+ case 'Q': USE_BITS (IMMQ); break;
+ case 'U': USE_BITS (IMMU); break;
+ case 'W': USE_BITS (IMMW); break;
+ case 'X': USE_BITS (IMMX); break;
+ case 'Y': USE_BITS (IMMY); break;
+ case 'Z': break;
+ case 'a': break;
+ case 'b': USE_BITS (MB); break;
+ case 'c': USE_BITS (MC); break;
+ case 'd': USE_BITS (MD); break;
+ case 'e': USE_BITS (ME); break;
+ case 'f': USE_BITS (MF); break;
+ case 'g': USE_BITS (MG); break;
+ case 'h': USE_BITS (MH); break;
+ case 'i': USE_BITS (MI); break;
+ case 'j': USE_BITS (MJ); break;
+ case 'l': USE_BITS (ML); break;
+ case 'm': USE_BITS (MM); break;
+ case 'n': USE_BITS (MN); break;
+ case 'p': USE_BITS (MP); break;
+ case 'q': USE_BITS (MQ); break;
+ case 'r': break;
+ case 's': break;
+ case 't': break;
+ case 'x': break;
+ case 'y': break;
+ case 'z': break;
+ default:
+ as_bad (_("Internal error: bad mips opcode "
+ "(unknown extension operand type `%c%c'): %s %s"),
+ e, c, opc->name, opc->args);
+ return 0;
+ }
+ break;
+ case '.': USE_BITS (OFFSET10); break;
+ case '1': USE_BITS (STYPE); break;
+ case '<': USE_BITS (SHAMT); break;
+ case '>': USE_BITS (SHAMT); break;
+ case 'B': USE_BITS (CODE10); break;
+ case 'C': USE_BITS (COPZ); break;
+ case 'D': USE_BITS (FD); break;
+ case 'E': USE_BITS (RT); break;
+ case 'G': USE_BITS (RS); break;
+ case 'H': USE_BITS (SEL); break;
+ case 'K': USE_BITS (RS); break;
+ case 'M': USE_BITS (CCC); break;
+ case 'N': USE_BITS (BCC); break;
+ case 'R': USE_BITS (FR); break;
+ case 'S': USE_BITS (FS); break;
+ case 'T': USE_BITS (FT); break;
+ case 'V': USE_BITS (FS); break;
+ case 'a': USE_BITS (TARGET); break;
+ case 'b': USE_BITS (RS); break;
+ case 'c': USE_BITS (CODE); break;
+ case 'd': USE_BITS (RD); break;
+ case 'h': USE_BITS (PREFX); break;
+ case 'i': USE_BITS (IMMEDIATE); break;
+ case 'j': USE_BITS (DELTA); break;
+ case 'k': USE_BITS (CACHE); break;
+ case 'n': USE_BITS (RT); break;
+ case 'o': USE_BITS (DELTA); break;
+ case 'p': USE_BITS (DELTA); break;
+ case 'q': USE_BITS (CODE2); break;
+ case 'r': USE_BITS (RS); break;
+ case 's': USE_BITS (RS); break;
+ case 't': USE_BITS (RT); break;
+ case 'u': USE_BITS (IMMEDIATE); break;
+ case 'v': USE_BITS (RS); break;
+ case 'w': USE_BITS (RT); break;
+ case 'y': USE_BITS (RS3); break;
+ case 'z': break;
+ case '|': USE_BITS (TRAP); break;
+ case '~': USE_BITS (OFFSET12); break;
+ default:
+ as_bad (_("Internal error: bad microMIPS opcode "
+ "(unknown operand type `%c'): %s %s"),
+ c, opc->name, opc->args);
+ return 0;
+ }
+#undef USE_BITS
+ if (used_bits != insn_bits)
+ {
+ if (~used_bits & insn_bits)
+ as_bad (_("Internal error: bad microMIPS opcode "
+ "(bits 0x%lx undefined): %s %s"),
+ ~used_bits & insn_bits, opc->name, opc->args);
+ if (used_bits & ~insn_bits)
+ as_bad (_("Internal error: bad microMIPS opcode "
+ "(bits 0x%lx defined): %s %s"),
+ used_bits & ~insn_bits, opc->name, opc->args);
+ return 0;
+ }
+ return 1;
+}
+
/* UDI immediates. */
struct mips_immed {
char type;
return 0;
}
+/* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
+ taking bits from BIT up. */
+static int
+expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
+{
+ return (ep->X_op == O_constant
+ && (ep->X_add_number & ((1 << bit) - 1)) == 0
+ && ep->X_add_number >= min << bit
+ && ep->X_add_number < max << bit);
+}
+
/* This routine assembles an instruction into its binary format. As a
side effect, it sets one of the global variables imm_reloc or
offset_reloc to the type of relocation to do if one of the operands
static void
mips_ip (char *str, struct mips_cl_insn *ip)
{
+ bfd_boolean wrong_delay_slot_insns = FALSE;
+ bfd_boolean need_delay_slot_ok = TRUE;
+ struct mips_opcode *firstinsn = NULL;
+ const struct mips_opcode *past;
+ struct hash_control *hash;
char *s;
const char *args;
char c = 0;
char *argsStart;
unsigned int regno;
unsigned int lastregno;
+ unsigned int destregno = 0;
unsigned int lastpos = 0;
unsigned int limlo, limhi;
char *s_reset;
offsetT min_range, max_range;
+ long opend;
char *name;
int argnum;
unsigned int rtype;
+ char *dot;
long end;
insn_error = NULL;
+ if (mips_opts.micromips)
+ {
+ hash = micromips_op_hash;
+ past = µmips_opcodes[bfd_micromips_num_opcodes];
+ }
+ else
+ {
+ hash = op_hash;
+ past = &mips_opcodes[NUMOPCODES];
+ }
+ forced_insn_length = 0;
insn = NULL;
- /* Try to match an instruction up to a space or to the end. */
+ /* We first try to match an instruction up to a space or to the end. */
for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
continue;
memcpy (name, str, end);
name[end] = '\0';
- insn = (struct mips_opcode *) hash_find (op_hash, name);
+ for (;;)
+ {
+ insn = (struct mips_opcode *) hash_find (hash, name);
+
+ if (insn != NULL || !mips_opts.micromips)
+ break;
+ if (forced_insn_length)
+ break;
+
+ /* See if there's an instruction size override suffix,
+ either `16' or `32', at the end of the mnemonic proper,
+ that defines the operation, i.e. before the first `.'
+ character if any. Strip it and retry. */
+ dot = strchr (name, '.');
+ opend = dot != NULL ? dot - name : end;
+ if (opend < 3)
+ break;
+ if (name[opend - 2] == '1' && name[opend - 1] == '6')
+ forced_insn_length = 2;
+ else if (name[opend - 2] == '3' && name[opend - 1] == '2')
+ forced_insn_length = 4;
+ else
+ break;
+ memcpy (name + opend - 2, name + opend, end - opend + 1);
+ }
if (insn == NULL)
{
insn_error = _("Unrecognized opcode");
return;
}
+ /* For microMIPS instructions placed in a fixed-length branch delay slot
+ we make up to two passes over the relevant fragment of the opcode
+ table. First we try instructions that meet the delay slot's length
+ requirement. If none matched, then we retry with the remaining ones
+ and if one matches, then we use it and then issue an appropriate
+ warning later on. */
argsStart = s = str + end;
for (;;)
{
+ bfd_boolean delay_slot_ok;
+ bfd_boolean size_ok;
bfd_boolean ok;
gas_assert (strcmp (insn->name, name) == 0);
ok = is_opcode_valid (insn);
- if (! ok)
+ size_ok = is_size_valid (insn);
+ delay_slot_ok = is_delay_slot_valid (insn);
+ if (!delay_slot_ok && !wrong_delay_slot_insns)
{
- if (insn + 1 < &mips_opcodes[NUMOPCODES]
- && strcmp (insn->name, insn[1].name) == 0)
+ firstinsn = insn;
+ wrong_delay_slot_insns = TRUE;
+ }
+ if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
+ {
+ static char buf[256];
+
+ if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
{
++insn;
continue;
}
- else
+ if (wrong_delay_slot_insns && need_delay_slot_ok)
{
- if (!insn_error)
- {
- static char buf[100];
- sprintf (buf,
- _("opcode not supported on this processor: %s (%s)"),
- mips_cpu_info_from_arch (mips_opts.arch)->name,
- mips_cpu_info_from_isa (mips_opts.isa)->name);
- insn_error = buf;
- }
- return;
+ gas_assert (firstinsn);
+ need_delay_slot_ok = FALSE;
+ past = insn + 1;
+ insn = firstinsn;
+ continue;
}
+
+ if (insn_error)
+ return;
+
+ if (!ok)
+ sprintf (buf, _("opcode not supported on this processor: %s (%s)"),
+ mips_cpu_info_from_arch (mips_opts.arch)->name,
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+ else
+ sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
+ 8 * forced_insn_length);
+ insn_error = buf;
+
+ return;
}
create_insn (ip, insn);
break;
case '2': /* DSP 2-bit unsigned immediate in bit 11. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number != 1
as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
(unsigned long) imm_expr.X_add_number);
}
- INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '3': /* DSP 3-bit unsigned immediate in bit 21. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_SA3)
as_bad (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
}
- INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '4': /* DSP 4-bit unsigned immediate in bit 21. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_SA4)
as_bad (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
}
- INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '5': /* DSP 8-bit unsigned immediate in bit 16. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_IMM8)
as_bad (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
}
- INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '6': /* DSP 5-bit unsigned immediate in bit 21. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_RS)
as_bad (_("DSP immediate not in range 0..%d (%lu)"),
OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
}
- INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '7': /* Four DSP accumulators in bits 11,12. */
+ gas_assert (!mips_opts.micromips);
if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
s[3] >= '0' && s[3] <= '3')
{
regno = s[3] - '0';
s += 4;
- INSERT_OPERAND (DSPACC, *ip, regno);
+ INSERT_OPERAND (0, DSPACC, *ip, regno);
continue;
}
else
break;
case '8': /* DSP 6-bit unsigned immediate in bit 11. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
OP_MASK_WRDSP,
(unsigned long) imm_expr.X_add_number);
}
- INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '9': /* Four DSP accumulators in bits 21,22. */
+ gas_assert (!mips_opts.micromips);
if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
s[3] >= '0' && s[3] <= '3')
{
regno = s[3] - '0';
s += 4;
- INSERT_OPERAND (DSPACC_S, *ip, regno);
+ INSERT_OPERAND (0, DSPACC_S, *ip, regno);
continue;
}
else
break;
case '0': /* DSP 6-bit signed immediate in bit 20. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
min_range = -((OP_MASK_DSPSFT + 1) >> 1);
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
}
- INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
OP_MASK_RDDSP,
(unsigned long) imm_expr.X_add_number);
}
- INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case ':': /* DSP 7-bit signed immediate in bit 19. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
}
- INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '@': /* DSP 10-bit signed immediate in bit 16. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
min_range = -((OP_MASK_IMM10 + 1) >> 1);
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
}
- INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '!': /* MT usermode flag bit. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_MT_U)
as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
(unsigned long) imm_expr.X_add_number);
- INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '$': /* MT load high flag bit. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_MT_H)
as_bad (_("MT load high bit not 0 or 1 (%lu)"),
(unsigned long) imm_expr.X_add_number);
- INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case '*': /* Four DSP accumulators in bits 18,19. */
+ gas_assert (!mips_opts.micromips);
if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
s[3] >= '0' && s[3] <= '3')
{
regno = s[3] - '0';
s += 4;
- INSERT_OPERAND (MTACC_T, *ip, regno);
+ INSERT_OPERAND (0, MTACC_T, *ip, regno);
continue;
}
else
break;
case '&': /* Four DSP accumulators in bits 13,14. */
+ gas_assert (!mips_opts.micromips);
if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
s[3] >= '0' && s[3] <= '3')
{
regno = s[3] - '0';
s += 4;
- INSERT_OPERAND (MTACC_D, *ip, regno);
+ INSERT_OPERAND (0, MTACC_D, *ip, regno);
continue;
}
else
{
case 'r':
case 'v':
- INSERT_OPERAND (RS, *ip, lastregno);
+ INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
continue;
case 'w':
- INSERT_OPERAND (RT, *ip, lastregno);
+ INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
continue;
case 'W':
- INSERT_OPERAND (FT, *ip, lastregno);
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, FT, *ip, lastregno);
continue;
case 'V':
- INSERT_OPERAND (FS, *ip, lastregno);
+ INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
continue;
}
break;
we must have a left paren. */
/* This is dependent on the next operand specifier
is a base register specification. */
- gas_assert (args[1] == 'b');
- if (*s == '\0')
+ gas_assert (args[1] == 'b'
+ || (mips_opts.micromips
+ && args[1] == 'm'
+ && (args[2] == 'l' || args[2] == 'n'
+ || args[2] == 's' || args[2] == 'a')));
+ if (*s == '\0' && args[1] == 'b')
return;
+ /* Fall through. */
case ')': /* These must match exactly. */
- case '[':
+ if (*s++ == *args)
+ continue;
+ break;
+
+ case '[': /* These must match exactly. */
case ']':
+ gas_assert (!mips_opts.micromips);
if (*s++ == *args)
continue;
break;
case '2':
case '3':
case '4':
+ gas_assert (!mips_opts.micromips);
{
const struct mips_immed *imm = mips_immed;
imm_expr.X_add_number = limlo;
}
lastpos = imm_expr.X_add_number;
- INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ EXTLSB, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
(unsigned long) lastpos);
imm_expr.X_add_number = limlo - lastpos;
}
- INSERT_OPERAND (INSMSB, *ip,
- lastpos + imm_expr.X_add_number - 1);
+ INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
+ lastpos + imm_expr.X_add_number - 1);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
(unsigned long) lastpos);
imm_expr.X_add_number = limlo - lastpos;
}
- INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
+ INSERT_OPERAND (mips_opts.micromips,
+ EXTMSBD, *ip, imm_expr.X_add_number - 1);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
continue;
case 'T': /* Coprocessor register. */
+ gas_assert (!mips_opts.micromips);
/* +T is for disassembly only; never match. */
break;
case 't': /* Coprocessor register number. */
+ gas_assert (!mips_opts.micromips);
if (s[0] == '$' && ISDIGIT (s[1]))
{
++s;
as_bad (_("Invalid register number (%d)"), regno);
else
{
- INSERT_OPERAND (RT, *ip, regno);
+ INSERT_OPERAND (0, RT, *ip, regno);
continue;
}
}
case 'x':
/* bbit[01] and bbit[01]32 bit index. Give error if index
is not in the valid range. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned) imm_expr.X_add_number > 31)
(unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number = 0;
}
- INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
/* bbit[01] bit index when bbit is used but we generate
bbit[01]32 because the index is over 32. Move to the
next candidate if index is not in the valid range. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned) imm_expr.X_add_number < 32
|| (unsigned) imm_expr.X_add_number > 63)
break;
- INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
+ INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'p':
/* cins, cins32, exts and exts32 position field. Give error
if it's not in the valid range. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned) imm_expr.X_add_number > 31)
}
/* Make the pos explicit to simplify +S. */
lastpos = imm_expr.X_add_number + 32;
- INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'P':
/* cins, cins32, exts and exts32 position field. Move to
the next candidate if it's not in the valid range. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned) imm_expr.X_add_number < 32
|| (unsigned) imm_expr.X_add_number > 63)
break;
lastpos = imm_expr.X_add_number;
- INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
+ INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 's':
/* cins and exts length-minus-one field. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > 31)
(unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number = 0;
}
- INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'S':
/* cins32/exts32 and cins/exts aliasing cint32/exts32
length-minus-one field. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((long) imm_expr.X_add_number < 0
(unsigned long) imm_expr.X_add_number);
imm_expr.X_add_number = 0;
}
- INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'Q':
/* seqi/snei immediate field. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((long) imm_expr.X_add_number < -512
(long) imm_expr.X_add_number);
imm_expr.X_add_number = 0;
}
- INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'a': /* 8-bit signed offset in bit 6 */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
}
- INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'b': /* 8-bit signed offset in bit 3 */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
}
- INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'c': /* 9-bit signed offset in bit 6 */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
(long) imm_expr.X_add_number);
}
/* Right shift 4 bits to adjust the offset operand. */
- INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
+ INSERT_OPERAND (0, OFFSET_C, *ip,
+ imm_expr.X_add_number >> 4);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'z':
+ gas_assert (!mips_opts.micromips);
if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
break;
if (regno == AT && mips_opts.at)
as_warn (_("used $%u with \".set at=$%u\""),
regno, mips_opts.at);
}
- INSERT_OPERAND (RZ, *ip, regno);
+ INSERT_OPERAND (0, RZ, *ip, regno);
continue;
case 'Z':
+ gas_assert (!mips_opts.micromips);
if (!reg_lookup (&s, RTYPE_FPU, ®no))
break;
- INSERT_OPERAND (FZ, *ip, regno);
+ INSERT_OPERAND (0, FZ, *ip, regno);
continue;
default:
- as_bad (_("Internal error: bad mips opcode "
+ as_bad (_("Internal error: bad %s opcode "
"(unknown extension operand type `+%c'): %s %s"),
+ mips_opts.micromips ? "microMIPS" : "MIPS",
*args, insn->name, insn->args);
/* Further processing is fruitless. */
return;
}
break;
+ case '.': /* 10-bit offset. */
+ case '~': /* 12-bit offset. */
+ gas_assert (mips_opts.micromips);
+ {
+ int shift = *args == '.' ? 9 : 11;
+ size_t i;
+
+ /* Check whether there is only a single bracketed expression
+ left. If so, it must be the base register and the
+ constant must be zero. */
+ if (*s == '(' && strchr (s + 1, '(') == 0)
+ continue;
+
+ /* If this value won't fit into the offset, then go find
+ a macro that will generate a 16- or 32-bit offset code
+ pattern. */
+ i = my_getSmallExpression (&imm_expr, imm_reloc, s);
+ if ((i == 0 && (imm_expr.X_op != O_constant
+ || imm_expr.X_add_number >= 1 << shift
+ || imm_expr.X_add_number < -1 << shift))
+ || i > 0)
+ {
+ imm_expr.X_op = O_absent;
+ break;
+ }
+ if (shift == 9)
+ INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
+ else
+ INSERT_OPERAND (1, OFFSET12, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
+ continue;
+
case '<': /* must be at least one digit */
/*
* According to the manual, if the shift amount is greater
if ((unsigned long) imm_expr.X_add_number > 31)
as_warn (_("Improper shift amount (%lu)"),
(unsigned long) imm_expr.X_add_number);
- INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ SHAMT, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
if ((unsigned long) imm_expr.X_add_number < 32
|| (unsigned long) imm_expr.X_add_number > 63)
break;
- INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
+ INSERT_OPERAND (mips_opts.micromips,
+ SHAMT, *ip, imm_expr.X_add_number - 32);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
as_warn (_("Invalid value for `%s' (%lu)"),
ip->insn_mo->name,
(unsigned long) imm_expr.X_add_number);
- if (*args == 'k')
+ switch (*args)
{
- if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
+ case 'k':
+ if (mips_fix_cn63xxp1
+ && !mips_opts.micromips
+ && strcmp ("pref", insn->name) == 0)
switch (imm_expr.X_add_number)
{
case 5:
imm_expr.X_add_number = 28;
break;
}
- INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ CACHE, *ip, imm_expr.X_add_number);
+ break;
+ case 'h':
+ INSERT_OPERAND (mips_opts.micromips,
+ PREFX, *ip, imm_expr.X_add_number);
+ break;
+ case '1':
+ INSERT_OPERAND (mips_opts.micromips,
+ STYPE, *ip, imm_expr.X_add_number);
+ break;
}
- else if (*args == 'h')
- INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
- else
- INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'c': /* BREAK code. */
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
- as_warn (_("Code for %s not in range 0..1023 (%lu)"),
- ip->insn_mo->name,
- (unsigned long) imm_expr.X_add_number);
- INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ {
+ unsigned long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_CODE
+ : OP_MASK_CODE);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned long) imm_expr.X_add_number > mask)
+ as_warn (_("Code for %s not in range 0..%lu (%lu)"),
+ ip->insn_mo->name,
+ mask, (unsigned long) imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ CODE, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
continue;
case 'q': /* Lower BREAK code. */
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
- as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
- ip->insn_mo->name,
- (unsigned long) imm_expr.X_add_number);
- INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ {
+ unsigned long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_CODE2
+ : OP_MASK_CODE2);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned long) imm_expr.X_add_number > mask)
+ as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
+ ip->insn_mo->name,
+ mask, (unsigned long) imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ CODE2, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
continue;
- case 'B': /* 20-bit SYSCALL/BREAK code. */
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
- as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
- ip->insn_mo->name,
- (unsigned long) imm_expr.X_add_number);
- INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ case 'B': /* 20- or 10-bit syscall/break/wait code. */
+ {
+ unsigned long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_CODE10
+ : OP_MASK_CODE20);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned long) imm_expr.X_add_number > mask)
+ as_warn (_("Code for %s not in range 0..%lu (%lu)"),
+ ip->insn_mo->name,
+ mask, (unsigned long) imm_expr.X_add_number);
+ if (mips_opts.micromips)
+ INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
+ else
+ INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
continue;
- case 'C': /* Coprocessor code. */
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
- {
- as_warn (_("Coproccesor code > 25 bits (%lu)"),
+ case 'C': /* 25- or 23-bit coprocessor code. */
+ {
+ unsigned long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_COPZ
+ : OP_MASK_COPZ);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned long) imm_expr.X_add_number > mask)
+ as_warn (_("Coproccesor code > %u bits (%lu)"),
+ mips_opts.micromips ? 23U : 25U,
(unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= OP_MASK_COPZ;
- }
- INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ INSERT_OPERAND (mips_opts.micromips,
+ COPZ, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
continue;
- case 'J': /* 19-bit WAIT code. */
+ case 'J': /* 19-bit WAIT code. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
- {
- as_warn (_("Illegal 19-bit code (%lu)"),
+ {
+ as_warn (_("Illegal 19-bit code (%lu)"),
(unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= OP_MASK_CODE19;
- }
- INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
+ imm_expr.X_add_number &= OP_MASK_CODE19;
+ }
+ INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'P': /* Performance register. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
as_warn (_("Invalid performance register (%lu)"),
(unsigned long) imm_expr.X_add_number);
- INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
case 'G': /* Coprocessor destination register. */
- if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
- ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
- else
- ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
- INSERT_OPERAND (RD, *ip, regno);
- if (ok)
- {
- lastregno = regno;
- continue;
- }
- else
- break;
+ {
+ unsigned long opcode = ip->insn_opcode;
+ unsigned long mask;
+ unsigned int types;
+ int cop0;
+
+ if (mips_opts.micromips)
+ {
+ mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
+ | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
+ | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
+ opcode &= mask;
+ switch (opcode)
+ {
+ case 0x000000fc: /* mfc0 */
+ case 0x000002fc: /* mtc0 */
+ case 0x580000fc: /* dmfc0 */
+ case 0x580002fc: /* dmtc0 */
+ cop0 = 1;
+ break;
+ default:
+ cop0 = 0;
+ break;
+ }
+ }
+ else
+ {
+ opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
+ cop0 = opcode == OP_OP_COP0;
+ }
+ types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
+ ok = reg_lookup (&s, types, ®no);
+ if (mips_opts.micromips)
+ INSERT_OPERAND (1, RS, *ip, regno);
+ else
+ INSERT_OPERAND (0, RD, *ip, regno);
+ if (ok)
+ {
+ lastregno = regno;
+ continue;
+ }
+ }
+ break;
+ case 'y': /* ALNV.PS source register. */
+ gas_assert (mips_opts.micromips);
+ goto do_reg;
+ case 'x': /* Ignore register name. */
+ case 'U': /* Destination register (CLO/CLZ). */
+ case 'g': /* Coprocessor destination register. */
+ gas_assert (!mips_opts.micromips);
case 'b': /* Base register. */
case 'd': /* Destination register. */
case 's': /* Source register. */
case 'w': /* Both dest and target. */
case 'E': /* Coprocessor target register. */
case 'K': /* RDHWR destination register. */
- case 'x': /* Ignore register name. */
case 'z': /* Must be zero register. */
- case 'U': /* Destination register (CLO/CLZ). */
- case 'g': /* Coprocessor destination register. */
+ do_reg:
s_reset = s;
if (*args == 'E' || *args == 'K')
ok = reg_lookup (&s, RTYPE_NUM, ®no);
case 's':
case 'v':
case 'b':
- INSERT_OPERAND (RS, *ip, regno);
+ INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
break;
- case 'd':
+
case 'K':
+ if (mips_opts.micromips)
+ INSERT_OPERAND (1, RS, *ip, regno);
+ else
+ INSERT_OPERAND (0, RD, *ip, regno);
+ break;
+
+ case 'd':
case 'g':
- INSERT_OPERAND (RD, *ip, regno);
+ INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
break;
+
case 'U':
- INSERT_OPERAND (RD, *ip, regno);
- INSERT_OPERAND (RT, *ip, regno);
+ gas_assert (!mips_opts.micromips);
+ INSERT_OPERAND (0, RD, *ip, regno);
+ INSERT_OPERAND (0, RT, *ip, regno);
break;
+
case 'w':
case 't':
case 'E':
- INSERT_OPERAND (RT, *ip, regno);
+ INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
+ break;
+
+ case 'y':
+ gas_assert (mips_opts.micromips);
+ INSERT_OPERAND (1, RS3, *ip, regno);
break;
+
case 'x':
/* This case exists because on the r3000 trunc
expands into a macro which requires a gp
is MIPS_ISA2 and uses 'x', and the macro
version is MIPS_ISA1 and uses 't'. */
break;
+
case 'z':
/* This case is for the div instruction, which
acts differently if the destination argument
{
case 'r':
case 'v':
- INSERT_OPERAND (RS, *ip, lastregno);
+ INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
continue;
+
case 'w':
- INSERT_OPERAND (RT, *ip, lastregno);
+ INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
continue;
}
break;
case 'O': /* MDMX alignment immediate constant. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
as_warn (_("Improper align amount (%ld), using low bits"),
(long) imm_expr.X_add_number);
- INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
if (s[0] != '$')
{
/* MDMX Immediate. */
+ gas_assert (!mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
as_warn (_("Invalid MDMX Immediate (%ld)"),
(long) imm_expr.X_add_number);
- INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
else
case 'Y': /* MDMX source register. */
case 'Z': /* MDMX target register. */
is_mdmx = 1;
+ case 'W':
+ gas_assert (!mips_opts.micromips);
case 'D': /* Floating point destination register. */
case 'S': /* Floating point source register. */
case 'T': /* Floating point target register. */
case 'R': /* Floating point source register. */
case 'V':
- case 'W':
rtype = RTYPE_FPU;
if (is_mdmx
|| (mips_opts.ase_mdmx
{
case 'D':
case 'X':
- INSERT_OPERAND (FD, *ip, regno);
+ INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
break;
+
case 'V':
case 'S':
case 'Y':
- INSERT_OPERAND (FS, *ip, regno);
+ INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
break;
+
case 'Q':
/* This is like 'Z', but also needs to fix the MDMX
vector/scalar select bits. Note that the
case 'W':
case 'T':
case 'Z':
- INSERT_OPERAND (FT, *ip, regno);
+ INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
break;
+
case 'R':
- INSERT_OPERAND (FR, *ip, regno);
+ INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
break;
}
lastregno = regno;
switch (*args++)
{
case 'V':
- INSERT_OPERAND (FS, *ip, lastregno);
+ INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
continue;
+
case 'W':
- INSERT_OPERAND (FT, *ip, lastregno);
+ INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
continue;
}
break;
if (seg == now_seg)
as_bad (_("Can't use floating point insn in this section"));
- /* Set the argument to the current address in the
- section. */
- offset_expr.X_op = O_symbol;
- offset_expr.X_add_symbol = symbol_temp_new_now ();
- offset_expr.X_add_number = 0;
+ /* Set the argument to the current address in the
+ section. */
+ offset_expr.X_op = O_symbol;
+ offset_expr.X_add_symbol = symbol_temp_new_now ();
+ offset_expr.X_add_number = 0;
+
+ /* Put the floating point number into the section. */
+ p = frag_more ((int) length);
+ memcpy (p, temp, length);
+
+ /* Switch back to the original section. */
+ subseg_set (seg, subseg);
+ }
+ }
+ continue;
+
+ case 'i': /* 16-bit unsigned immediate. */
+ case 'j': /* 16-bit signed immediate. */
+ *imm_reloc = BFD_RELOC_LO16;
+ if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
+ {
+ int more;
+ offsetT minval, maxval;
+
+ more = (insn + 1 < past
+ && strcmp (insn->name, insn[1].name) == 0);
+
+ /* If the expression was written as an unsigned number,
+ only treat it as signed if there are no more
+ alternatives. */
+ if (more
+ && *args == 'j'
+ && sizeof (imm_expr.X_add_number) <= 4
+ && imm_expr.X_op == O_constant
+ && imm_expr.X_add_number < 0
+ && imm_expr.X_unsigned
+ && HAVE_64BIT_GPRS)
+ break;
+
+ /* For compatibility with older assemblers, we accept
+ 0x8000-0xffff as signed 16-bit numbers when only
+ signed numbers are allowed. */
+ if (*args == 'i')
+ minval = 0, maxval = 0xffff;
+ else if (more)
+ minval = -0x8000, maxval = 0x7fff;
+ else
+ minval = -0x8000, maxval = 0xffff;
+
+ if (imm_expr.X_op != O_constant
+ || imm_expr.X_add_number < minval
+ || imm_expr.X_add_number > maxval)
+ {
+ if (more)
+ break;
+ if (imm_expr.X_op == O_constant
+ || imm_expr.X_op == O_big)
+ as_bad (_("Expression out of range"));
+ }
+ }
+ s = expr_end;
+ continue;
+
+ case 'o': /* 16-bit offset. */
+ offset_reloc[0] = BFD_RELOC_LO16;
+ offset_reloc[1] = BFD_RELOC_UNUSED;
+ offset_reloc[2] = BFD_RELOC_UNUSED;
+
+ /* Check whether there is only a single bracketed expression
+ left. If so, it must be the base register and the
+ constant must be zero. */
+ if (*s == '(' && strchr (s + 1, '(') == 0)
+ {
+ offset_expr.X_op = O_constant;
+ offset_expr.X_add_number = 0;
+ continue;
+ }
+
+ /* If this value won't fit into a 16 bit offset, then go
+ find a macro that will generate the 32 bit offset
+ code pattern. */
+ if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
+ && (offset_expr.X_op != O_constant
+ || offset_expr.X_add_number >= 0x8000
+ || offset_expr.X_add_number < -0x8000))
+ break;
+
+ s = expr_end;
+ continue;
+
+ case 'p': /* PC-relative offset. */
+ *offset_reloc = BFD_RELOC_16_PCREL_S2;
+ my_getExpression (&offset_expr, s);
+ s = expr_end;
+ continue;
+
+ case 'u': /* Upper 16 bits. */
+ if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
+ && imm_expr.X_op == O_constant
+ && (imm_expr.X_add_number < 0
+ || imm_expr.X_add_number >= 0x10000))
+ as_bad (_("lui expression (%lu) not in range 0..65535"),
+ (unsigned long) imm_expr.X_add_number);
+ s = expr_end;
+ continue;
+
+ case 'a': /* 26-bit address. */
+ *offset_reloc = BFD_RELOC_MIPS_JMP;
+ my_getExpression (&offset_expr, s);
+ s = expr_end;
+ continue;
+
+ case 'N': /* 3-bit branch condition code. */
+ case 'M': /* 3-bit compare condition code. */
+ rtype = RTYPE_CCC;
+ if (ip->insn_mo->pinfo & (FP_D | FP_S))
+ rtype |= RTYPE_FCC;
+ if (!reg_lookup (&s, rtype, ®no))
+ break;
+ if ((strcmp (str + strlen (str) - 3, ".ps") == 0
+ || strcmp (str + strlen (str) - 5, "any2f") == 0
+ || strcmp (str + strlen (str) - 5, "any2t") == 0)
+ && (regno & 1) != 0)
+ as_warn (_("Condition code register should be even for %s, "
+ "was %d"),
+ str, regno);
+ if ((strcmp (str + strlen (str) - 5, "any4f") == 0
+ || strcmp (str + strlen (str) - 5, "any4t") == 0)
+ && (regno & 3) != 0)
+ as_warn (_("Condition code register should be 0 or 4 for %s, "
+ "was %d"),
+ str, regno);
+ if (*args == 'N')
+ INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
+ else
+ INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
+ continue;
+
+ case 'H':
+ if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
+ s += 2;
+ if (ISDIGIT (*s))
+ {
+ c = 0;
+ do
+ {
+ c *= 10;
+ c += *s - '0';
+ ++s;
+ }
+ while (ISDIGIT (*s));
+ }
+ else
+ c = 8; /* Invalid sel value. */
+
+ if (c > 7)
+ as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
+ INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
+ continue;
+
+ case 'e':
+ gas_assert (!mips_opts.micromips);
+ /* Must be at least one digit. */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+
+ if ((unsigned long) imm_expr.X_add_number
+ > (unsigned long) OP_MASK_VECBYTE)
+ {
+ as_bad (_("bad byte vector index (%ld)"),
+ (long) imm_expr.X_add_number);
+ imm_expr.X_add_number = 0;
+ }
+
+ INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
+ case '%':
+ gas_assert (!mips_opts.micromips);
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+
+ if ((unsigned long) imm_expr.X_add_number
+ > (unsigned long) OP_MASK_VECALIGN)
+ {
+ as_bad (_("bad byte vector index (%ld)"),
+ (long) imm_expr.X_add_number);
+ imm_expr.X_add_number = 0;
+ }
+
+ INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
+ case 'm': /* Opcode extension character. */
+ gas_assert (mips_opts.micromips);
+ c = *++args;
+ switch (c)
+ {
+ case 'r':
+ if (strncmp (s, "$pc", 3) == 0)
+ {
+ s += 3;
+ continue;
+ }
+ break;
+
+ case 'a':
+ case 'b':
+ case 'c':
+ case 'd':
+ case 'e':
+ case 'f':
+ case 'g':
+ case 'h':
+ case 'i':
+ case 'j':
+ case 'l':
+ case 'm':
+ case 'n':
+ case 'p':
+ case 'q':
+ case 's':
+ case 't':
+ case 'x':
+ case 'y':
+ case 'z':
+ s_reset = s;
+ ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
+ if (regno == AT && mips_opts.at)
+ {
+ if (mips_opts.at == ATREG)
+ as_warn (_("Used $at without \".set noat\""));
+ else
+ as_warn (_("Used $%u with \".set at=$%u\""),
+ regno, mips_opts.at);
+ }
+ if (!ok)
+ {
+ if (c == 'c')
+ {
+ gas_assert (args[1] == ',');
+ regno = lastregno;
+ ++args;
+ }
+ else if (c == 't')
+ {
+ gas_assert (args[1] == ',');
+ ++args;
+ continue; /* Nothing to do. */
+ }
+ else
+ break;
+ }
+
+ if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
+ {
+ if (regno == lastregno)
+ {
+ insn_error
+ = _("Source and destination must be different");
+ continue;
+ }
+ if (regno == 31 && lastregno == 0xffffffff)
+ {
+ insn_error
+ = _("A destination register must be supplied");
+ continue;
+ }
+ }
+
+ if (*s == ' ')
+ ++s;
+ if (args[1] != *s)
+ {
+ if (c == 'e')
+ {
+ gas_assert (args[1] == ',');
+ regno = lastregno;
+ s = s_reset;
+ ++args;
+ }
+ else if (c == 't')
+ {
+ gas_assert (args[1] == ',');
+ s = s_reset;
+ ++args;
+ continue; /* Nothing to do. */
+ }
+ }
+
+ /* Make sure regno is the same as lastregno. */
+ if (c == 't' && regno != lastregno)
+ break;
+
+ /* Make sure regno is the same as destregno. */
+ if (c == 'x' && regno != destregno)
+ break;
+
+ /* We need to save regno, before regno maps to the
+ microMIPS register encoding. */
+ lastregno = regno;
+
+ if (c == 'f')
+ destregno = regno;
+
+ switch (c)
+ {
+ case 'a':
+ if (regno != GP)
+ regno = ILLEGAL_REG;
+ break;
+
+ case 'b':
+ regno = mips32_to_micromips_reg_b_map[regno];
+ break;
+
+ case 'c':
+ regno = mips32_to_micromips_reg_c_map[regno];
+ break;
+
+ case 'd':
+ regno = mips32_to_micromips_reg_d_map[regno];
+ break;
+
+ case 'e':
+ regno = mips32_to_micromips_reg_e_map[regno];
+ break;
+
+ case 'f':
+ regno = mips32_to_micromips_reg_f_map[regno];
+ break;
+
+ case 'g':
+ regno = mips32_to_micromips_reg_g_map[regno];
+ break;
+
+ case 'h':
+ regno = mips32_to_micromips_reg_h_map[regno];
+ break;
+
+ case 'i':
+ switch (EXTRACT_OPERAND (1, MI, *ip))
+ {
+ case 4:
+ if (regno == 21)
+ regno = 3;
+ else if (regno == 22)
+ regno = 4;
+ else if (regno == 5)
+ regno = 5;
+ else if (regno == 6)
+ regno = 6;
+ else if (regno == 7)
+ regno = 7;
+ else
+ regno = ILLEGAL_REG;
+ break;
+
+ case 5:
+ if (regno == 6)
+ regno = 0;
+ else if (regno == 7)
+ regno = 1;
+ else
+ regno = ILLEGAL_REG;
+ break;
+
+ case 6:
+ if (regno == 7)
+ regno = 2;
+ else
+ regno = ILLEGAL_REG;
+ break;
+
+ default:
+ regno = ILLEGAL_REG;
+ break;
+ }
+ break;
+
+ case 'l':
+ regno = mips32_to_micromips_reg_l_map[regno];
+ break;
+
+ case 'm':
+ regno = mips32_to_micromips_reg_m_map[regno];
+ break;
+
+ case 'n':
+ regno = mips32_to_micromips_reg_n_map[regno];
+ break;
+
+ case 'q':
+ regno = mips32_to_micromips_reg_q_map[regno];
+ break;
+
+ case 's':
+ if (regno != SP)
+ regno = ILLEGAL_REG;
+ break;
+
+ case 'y':
+ if (regno != 31)
+ regno = ILLEGAL_REG;
+ break;
+
+ case 'z':
+ if (regno != ZERO)
+ regno = ILLEGAL_REG;
+ break;
+
+ case 'j': /* Do nothing. */
+ case 'p':
+ case 't':
+ case 'x':
+ break;
+
+ default:
+ internalError ();
+ }
+
+ if (regno == ILLEGAL_REG)
+ break;
+
+ switch (c)
+ {
+ case 'b':
+ INSERT_OPERAND (1, MB, *ip, regno);
+ break;
+
+ case 'c':
+ INSERT_OPERAND (1, MC, *ip, regno);
+ break;
+
+ case 'd':
+ INSERT_OPERAND (1, MD, *ip, regno);
+ break;
+
+ case 'e':
+ INSERT_OPERAND (1, ME, *ip, regno);
+ break;
+
+ case 'f':
+ INSERT_OPERAND (1, MF, *ip, regno);
+ break;
+
+ case 'g':
+ INSERT_OPERAND (1, MG, *ip, regno);
+ break;
+
+ case 'h':
+ INSERT_OPERAND (1, MH, *ip, regno);
+ break;
+
+ case 'i':
+ INSERT_OPERAND (1, MI, *ip, regno);
+ break;
+
+ case 'j':
+ INSERT_OPERAND (1, MJ, *ip, regno);
+ break;
+
+ case 'l':
+ INSERT_OPERAND (1, ML, *ip, regno);
+ break;
+
+ case 'm':
+ INSERT_OPERAND (1, MM, *ip, regno);
+ break;
+
+ case 'n':
+ INSERT_OPERAND (1, MN, *ip, regno);
+ break;
+
+ case 'p':
+ INSERT_OPERAND (1, MP, *ip, regno);
+ break;
+
+ case 'q':
+ INSERT_OPERAND (1, MQ, *ip, regno);
+ break;
+
+ case 'a': /* Do nothing. */
+ case 's': /* Do nothing. */
+ case 't': /* Do nothing. */
+ case 'x': /* Do nothing. */
+ case 'y': /* Do nothing. */
+ case 'z': /* Do nothing. */
+ break;
+
+ default:
+ internalError ();
+ }
+ continue;
+
+ case 'A':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ /* Check whether there is only a single bracketed
+ expression left. If so, it must be the base register
+ and the constant must be zero. */
+ if (*s == '(' && strchr (s + 1, '(') == 0)
+ {
+ INSERT_OPERAND (1, IMMA, *ip, 0);
+ continue;
+ }
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, -64, 64, 2))
+ break;
+
+ imm = ep.X_add_number >> 2;
+ INSERT_OPERAND (1, IMMA, *ip, imm);
+ }
+ s = expr_end;
+ continue;
+
+ case 'B':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || ep.X_op != O_constant)
+ break;
+
+ for (imm = 0; imm < 8; imm++)
+ if (micromips_imm_b_map[imm] == ep.X_add_number)
+ break;
+ if (imm >= 8)
+ break;
+
+ INSERT_OPERAND (1, IMMB, *ip, imm);
+ }
+ s = expr_end;
+ continue;
+
+ case 'C':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || ep.X_op != O_constant)
+ break;
+
+ for (imm = 0; imm < 16; imm++)
+ if (micromips_imm_c_map[imm] == ep.X_add_number)
+ break;
+ if (imm >= 16)
+ break;
+
+ INSERT_OPERAND (1, IMMC, *ip, imm);
+ }
+ s = expr_end;
+ continue;
+
+ case 'D': /* pc relative offset */
+ case 'E': /* pc relative offset */
+ my_getExpression (&offset_expr, s);
+ if (offset_expr.X_op == O_register)
+ break;
+
+ *offset_reloc = (int) BFD_RELOC_UNUSED + c;
+ s = expr_end;
+ continue;
+
+ case 'F':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, 0, 16, 0))
+ break;
+
+ imm = ep.X_add_number;
+ INSERT_OPERAND (1, IMMF, *ip, imm);
+ }
+ s = expr_end;
+ continue;
+
+ case 'G':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ /* Check whether there is only a single bracketed
+ expression left. If so, it must be the base register
+ and the constant must be zero. */
+ if (*s == '(' && strchr (s + 1, '(') == 0)
+ {
+ INSERT_OPERAND (1, IMMG, *ip, 0);
+ continue;
+ }
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, -1, 15, 0))
+ break;
+
+ imm = ep.X_add_number & 15;
+ INSERT_OPERAND (1, IMMG, *ip, imm);
+ }
+ s = expr_end;
+ continue;
+
+ case 'H':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ /* Check whether there is only a single bracketed
+ expression left. If so, it must be the base register
+ and the constant must be zero. */
+ if (*s == '(' && strchr (s + 1, '(') == 0)
+ {
+ INSERT_OPERAND (1, IMMH, *ip, 0);
+ continue;
+ }
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, 0, 16, 1))
+ break;
+
+ imm = ep.X_add_number >> 1;
+ INSERT_OPERAND (1, IMMH, *ip, imm);
+ }
+ s = expr_end;
+ continue;
+
+ case 'I':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, -1, 127, 0))
+ break;
+
+ imm = ep.X_add_number & 127;
+ INSERT_OPERAND (1, IMMI, *ip, imm);
+ }
+ s = expr_end;
+ continue;
+
+ case 'J':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ /* Check whether there is only a single bracketed
+ expression left. If so, it must be the base register
+ and the constant must be zero. */
+ if (*s == '(' && strchr (s + 1, '(') == 0)
+ {
+ INSERT_OPERAND (1, IMMJ, *ip, 0);
+ continue;
+ }
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, 0, 16, 2))
+ break;
+
+ imm = ep.X_add_number >> 2;
+ INSERT_OPERAND (1, IMMJ, *ip, imm);
+ }
+ s = expr_end;
+ continue;
+
+ case 'L':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ /* Check whether there is only a single bracketed
+ expression left. If so, it must be the base register
+ and the constant must be zero. */
+ if (*s == '(' && strchr (s + 1, '(') == 0)
+ {
+ INSERT_OPERAND (1, IMML, *ip, 0);
+ continue;
+ }
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, 0, 16, 0))
+ break;
+
+ imm = ep.X_add_number;
+ INSERT_OPERAND (1, IMML, *ip, imm);
+ }
+ s = expr_end;
+ continue;
+
+ case 'M':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, 1, 9, 0))
+ break;
+
+ imm = ep.X_add_number & 7;
+ INSERT_OPERAND (1, IMMM, *ip, imm);
+ }
+ s = expr_end;
+ continue;
+
+ case 'N': /* Register list for lwm and swm. */
+ {
+ /* A comma-separated list of registers and/or
+ dash-separated contiguous ranges including
+ both ra and a set of one or more registers
+ starting at s0 up to s3 which have to be
+ consecutive, e.g.:
+
+ s0, ra
+ s0, s1, ra, s2, s3
+ s0-s2, ra
+
+ and any permutations of these. */
+ unsigned int reglist;
+ int imm;
+
+ if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
+ break;
+
+ if ((reglist & 0xfff1ffff) != 0x80010000)
+ break;
+
+ reglist = (reglist >> 17) & 7;
+ reglist += 1;
+ if ((reglist & -reglist) != reglist)
+ break;
- /* Put the floating point number into the section. */
- p = frag_more ((int) length);
- memcpy (p, temp, length);
+ imm = ffs (reglist) - 1;
+ INSERT_OPERAND (1, IMMN, *ip, imm);
+ }
+ continue;
- /* Switch back to the original section. */
- subseg_set (seg, subseg);
+ case 'O': /* sdbbp 4-bit code. */
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, 0, 16, 0))
+ break;
+
+ imm = ep.X_add_number;
+ INSERT_OPERAND (1, IMMO, *ip, imm);
}
- }
- continue;
+ s = expr_end;
+ continue;
- case 'i': /* 16-bit unsigned immediate. */
- case 'j': /* 16-bit signed immediate. */
- *imm_reloc = BFD_RELOC_LO16;
- if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
- {
- int more;
- offsetT minval, maxval;
+ case 'P':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
- more = (insn + 1 < &mips_opcodes[NUMOPCODES]
- && strcmp (insn->name, insn[1].name) == 0);
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, 0, 32, 2))
+ break;
- /* If the expression was written as an unsigned number,
- only treat it as signed if there are no more
- alternatives. */
- if (more
- && *args == 'j'
- && sizeof (imm_expr.X_add_number) <= 4
- && imm_expr.X_op == O_constant
- && imm_expr.X_add_number < 0
- && imm_expr.X_unsigned
- && HAVE_64BIT_GPRS)
- break;
+ imm = ep.X_add_number >> 2;
+ INSERT_OPERAND (1, IMMP, *ip, imm);
+ }
+ s = expr_end;
+ continue;
- /* For compatibility with older assemblers, we accept
- 0x8000-0xffff as signed 16-bit numbers when only
- signed numbers are allowed. */
- if (*args == 'i')
- minval = 0, maxval = 0xffff;
- else if (more)
- minval = -0x8000, maxval = 0x7fff;
- else
- minval = -0x8000, maxval = 0xffff;
+ case 'Q':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
- if (imm_expr.X_op != O_constant
- || imm_expr.X_add_number < minval
- || imm_expr.X_add_number > maxval)
- {
- if (more)
- break;
- if (imm_expr.X_op == O_constant
- || imm_expr.X_op == O_big)
- as_bad (_("Expression out of range"));
- }
- }
- s = expr_end;
- continue;
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
+ break;
- case 'o': /* 16-bit offset. */
- offset_reloc[0] = BFD_RELOC_LO16;
- offset_reloc[1] = BFD_RELOC_UNUSED;
- offset_reloc[2] = BFD_RELOC_UNUSED;
+ imm = ep.X_add_number >> 2;
+ INSERT_OPERAND (1, IMMQ, *ip, imm);
+ }
+ s = expr_end;
+ continue;
- /* Check whether there is only a single bracketed expression
- left. If so, it must be the base register and the
- constant must be zero. */
- if (*s == '(' && strchr (s + 1, '(') == 0)
- {
- offset_expr.X_op = O_constant;
- offset_expr.X_add_number = 0;
+ case 'U':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
+
+ /* Check whether there is only a single bracketed
+ expression left. If so, it must be the base register
+ and the constant must be zero. */
+ if (*s == '(' && strchr (s + 1, '(') == 0)
+ {
+ INSERT_OPERAND (1, IMMU, *ip, 0);
+ continue;
+ }
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, 0, 32, 2))
+ break;
+
+ imm = ep.X_add_number >> 2;
+ INSERT_OPERAND (1, IMMU, *ip, imm);
+ }
+ s = expr_end;
continue;
- }
- /* If this value won't fit into a 16 bit offset, then go
- find a macro that will generate the 32 bit offset
- code pattern. */
- if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
- && (offset_expr.X_op != O_constant
- || offset_expr.X_add_number >= 0x8000
- || offset_expr.X_add_number < -0x8000))
- break;
+ case 'W':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
- s = expr_end;
- continue;
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, 0, 64, 2))
+ break;
- case 'p': /* PC-relative offset. */
- *offset_reloc = BFD_RELOC_16_PCREL_S2;
- my_getExpression (&offset_expr, s);
- s = expr_end;
- continue;
+ imm = ep.X_add_number >> 2;
+ INSERT_OPERAND (1, IMMW, *ip, imm);
+ }
+ s = expr_end;
+ continue;
- case 'u': /* Upper 16 bits. */
- if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
- && imm_expr.X_op == O_constant
- && (imm_expr.X_add_number < 0
- || imm_expr.X_add_number >= 0x10000))
- as_bad (_("lui expression (%lu) not in range 0..65535"),
- (unsigned long) imm_expr.X_add_number);
- s = expr_end;
- continue;
+ case 'X':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
- case 'a': /* 26-bit address. */
- my_getExpression (&offset_expr, s);
- s = expr_end;
- *offset_reloc = BFD_RELOC_MIPS_JMP;
- continue;
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, -8, 8, 0))
+ break;
- case 'N': /* 3-bit branch condition code. */
- case 'M': /* 3-bit compare condition code. */
- rtype = RTYPE_CCC;
- if (ip->insn_mo->pinfo & (FP_D | FP_S))
- rtype |= RTYPE_FCC;
- if (!reg_lookup (&s, rtype, ®no))
- break;
- if ((strcmp (str + strlen (str) - 3, ".ps") == 0
- || strcmp (str + strlen (str) - 5, "any2f") == 0
- || strcmp (str + strlen (str) - 5, "any2t") == 0)
- && (regno & 1) != 0)
- as_warn (_("Condition code register should be even for %s, "
- "was %d"),
- str, regno);
- if ((strcmp (str + strlen (str) - 5, "any4f") == 0
- || strcmp (str + strlen (str) - 5, "any4t") == 0)
- && (regno & 3) != 0)
- as_warn (_("Condition code register should be 0 or 4 for %s, "
- "was %d"),
- str, regno);
- if (*args == 'N')
- INSERT_OPERAND (BCC, *ip, regno);
- else
- INSERT_OPERAND (CCC, *ip, regno);
- continue;
+ imm = ep.X_add_number;
+ INSERT_OPERAND (1, IMMX, *ip, imm);
+ }
+ s = expr_end;
+ continue;
- case 'H':
- if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
- s += 2;
- if (ISDIGIT (*s))
- {
- c = 0;
- do
- {
- c *= 10;
- c += *s - '0';
- ++s;
- }
- while (ISDIGIT (*s));
- }
- else
- c = 8; /* Invalid sel value. */
+ case 'Y':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+ int imm;
- if (c > 7)
- as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
- ip->insn_opcode |= c;
- continue;
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || expr_const_in_range (&ep, -2, 2, 2)
+ || !expr_const_in_range (&ep, -258, 258, 2))
+ break;
- case 'e':
- /* Must be at least one digit. */
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
+ imm = ep.X_add_number >> 2;
+ imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
+ INSERT_OPERAND (1, IMMY, *ip, imm);
+ }
+ s = expr_end;
+ continue;
- if ((unsigned long) imm_expr.X_add_number
- > (unsigned long) OP_MASK_VECBYTE)
- {
- as_bad (_("bad byte vector index (%ld)"),
- (long) imm_expr.X_add_number);
- imm_expr.X_add_number = 0;
+ case 'Z':
+ {
+ bfd_reloc_code_real_type r[3];
+ expressionS ep;
+
+ if (my_getSmallExpression (&ep, r, s) > 0
+ || !expr_const_in_range (&ep, 0, 1, 0))
+ break;
+ }
+ s = expr_end;
+ continue;
+
+ default:
+ as_bad (_("Internal error: bad microMIPS opcode "
+ "(unknown extension operand type `m%c'): %s %s"),
+ *args, insn->name, insn->args);
+ /* Further processing is fruitless. */
+ return;
}
+ break;
- INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ case 'n': /* Register list for 32-bit lwm and swm. */
+ gas_assert (mips_opts.micromips);
+ {
+ /* A comma-separated list of registers and/or
+ dash-separated contiguous ranges including
+ at least one of ra and a set of one or more
+ registers starting at s0 up to s7 and then
+ s8 which have to be consecutive, e.g.:
+
+ ra
+ s0
+ ra, s0, s1, s2
+ s0-s8
+ s0-s5, ra
+
+ and any permutations of these. */
+ unsigned int reglist;
+ int imm;
+ int ra;
+
+ if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
+ break;
+
+ if ((reglist & 0x3f00ffff) != 0)
+ break;
+
+ ra = (reglist >> 27) & 0x10;
+ reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
+ reglist += 1;
+ if ((reglist & -reglist) != reglist)
+ break;
+
+ imm = (ffs (reglist) - 1) | ra;
+ INSERT_OPERAND (1, RT, *ip, imm);
+ imm_expr.X_op = O_absent;
+ }
continue;
- case '%':
+ case '|': /* 4-bit trap code. */
+ gas_assert (mips_opts.micromips);
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
-
if ((unsigned long) imm_expr.X_add_number
- > (unsigned long) OP_MASK_VECALIGN)
- {
- as_bad (_("bad byte vector index (%ld)"),
- (long) imm_expr.X_add_number);
- imm_expr.X_add_number = 0;
- }
-
- INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
+ > MICROMIPSOP_MASK_TRAP)
+ as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
+ (unsigned long) imm_expr.X_add_number,
+ ip->insn_mo->name);
+ INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
break;
}
/* Args don't match. */
- if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
- !strcmp (insn->name, insn[1].name))
+ s = argsStart;
+ insn_error = _("Illegal operands");
+ if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
{
++insn;
- s = argsStart;
- insn_error = _("Illegal operands");
continue;
}
- insn_error = _("Illegal operands");
+ else if (wrong_delay_slot_insns && need_delay_slot_ok)
+ {
+ gas_assert (firstinsn);
+ need_delay_slot_ok = FALSE;
+ past = insn + 1;
+ insn = firstinsn;
+ continue;
+ }
return;
}
}
/* This routine assembles an instruction into its binary format when
assembling for the mips16. As a side effect, it sets one of the
- global variables imm_reloc or offset_reloc to the type of
- relocation to do if one of the operands is an address expression.
- It also sets mips16_small and mips16_ext if the user explicitly
- requested a small or extended instruction. */
+ global variables imm_reloc or offset_reloc to the type of relocation
+ to do if one of the operands is an address expression. It also sets
+ forced_insn_length to the resulting instruction size in bytes if the
+ user explicitly requested a small or extended instruction. */
static void
mips16_ip (char *str, struct mips_cl_insn *ip)
insn_error = NULL;
- mips16_small = FALSE;
- mips16_ext = FALSE;
+ forced_insn_length = 0;
for (s = str; ISLOWER (*s); ++s)
;
if (s[1] == 't' && s[2] == ' ')
{
*s = '\0';
- mips16_small = TRUE;
+ forced_insn_length = 2;
s += 3;
break;
}
else if (s[1] == 'e' && s[2] == ' ')
{
*s = '\0';
- mips16_ext = TRUE;
+ forced_insn_length = 4;
s += 3;
break;
}
return;
}
- if (mips_opts.noautoextend && ! mips16_ext)
- mips16_small = TRUE;
+ if (mips_opts.noautoextend && !forced_insn_length)
+ forced_insn_length = 2;
if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
{
*offset_reloc = BFD_RELOC_UNUSED;
mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
- tmp, TRUE, mips16_small,
- mips16_ext, &ip->insn_opcode,
+ tmp, TRUE, forced_insn_length == 2,
+ forced_insn_length == 4, &ip->insn_opcode,
&ip->use_extend, &ip->extend);
imm_expr.X_op = O_absent;
*imm_reloc = BFD_RELOC_UNUSED;
{
if (imm_expr.X_op != O_constant)
{
- mips16_ext = TRUE;
+ forced_insn_length = 4;
ip->use_extend = TRUE;
ip->extend = 0;
}
OPTION_NO_SMARTMIPS,
OPTION_DSPR2,
OPTION_NO_DSPR2,
+ OPTION_MICROMIPS,
+ OPTION_NO_MICROMIPS,
OPTION_COMPAT_ARCH_BASE,
OPTION_M4650,
OPTION_NO_M4650,
{"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
{"mdspr2", no_argument, NULL, OPTION_DSPR2},
{"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
+ {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
+ {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
/* Old-style architecture options. Don't add more of these. */
{"m4650", no_argument, NULL, OPTION_M4650},
mips_opts.ase_mt = 0;
break;
+ case OPTION_MICROMIPS:
+ if (mips_opts.mips16 == 1)
+ {
+ as_bad (_("-mmicromips cannot be used with -mips16"));
+ return 0;
+ }
+ mips_opts.micromips = 1;
+ mips_no_prev_insn ();
+ break;
+
+ case OPTION_NO_MICROMIPS:
+ mips_opts.micromips = 0;
+ mips_no_prev_insn ();
+ break;
+
case OPTION_MIPS16:
+ if (mips_opts.micromips == 1)
+ {
+ as_bad (_("-mips16 cannot be used with -micromips"));
+ return 0;
+ }
mips_opts.mips16 = 1;
mips_no_prev_insn ();
break;
generation of code for them. */
if (mips_opts.mips16 == -1)
mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
+ if (mips_opts.micromips == -1)
+ mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
if (mips_opts.ase_mips3d == -1)
mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
&& file_mips_fp32 == 0) ? 1 : 0;
valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
switch (fixP->fx_r_type)
{
+ case BFD_RELOC_MICROMIPS_7_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_10_PCREL_S1:
+ /* Return the address of the delay slot. */
+ return addr + 2;
+
+ case BFD_RELOC_MICROMIPS_16_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_JMP:
case BFD_RELOC_16_PCREL_S2:
case BFD_RELOC_MIPS_JMP:
/* Return the address of the delay slot. */
return addr + 4;
+
default:
/* We have no relocation type for PC relative MIPS16 instructions. */
if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
if (generic_force_reloc (fixp))
return 1;
+ /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
+ so that the linker relaxation can update targets. */
+ if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
+ return 1;
+
if (HAVE_NEWABI
&& S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
&& (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
if (! howto)
return;
- gas_assert (fixP->fx_size == 4
+ gas_assert (fixP->fx_size == 2
+ || fixP->fx_size == 4
|| fixP->fx_r_type == BFD_RELOC_16
|| fixP->fx_r_type == BFD_RELOC_64
|| fixP->fx_r_type == BFD_RELOC_CTOR
|| fixP->fx_r_type == BFD_RELOC_MIPS_SUB
+ || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
|| fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
- gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
+ gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
+ || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
+ || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
+ || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
/* Don't treat parts of a composite relocation as done. There are two
reasons for this:
case BFD_RELOC_MIPS_TLS_GOTTPREL:
case BFD_RELOC_MIPS_TLS_TPREL_HI16:
case BFD_RELOC_MIPS_TLS_TPREL_LO16:
+ case BFD_RELOC_MICROMIPS_TLS_GD:
+ case BFD_RELOC_MICROMIPS_TLS_LDM:
+ case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
+ case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
+ case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
+ case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
+ case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
S_SET_THREAD_LOCAL (fixP->fx_addsy);
/* fall through */
case BFD_RELOC_MIPS16_HI16:
case BFD_RELOC_MIPS16_HI16_S:
case BFD_RELOC_MIPS16_JMP:
+ case BFD_RELOC_MICROMIPS_JMP:
+ case BFD_RELOC_MICROMIPS_GOT_DISP:
+ case BFD_RELOC_MICROMIPS_GOT_PAGE:
+ case BFD_RELOC_MICROMIPS_GOT_OFST:
+ case BFD_RELOC_MICROMIPS_SUB:
+ case BFD_RELOC_MICROMIPS_HIGHEST:
+ case BFD_RELOC_MICROMIPS_HIGHER:
+ case BFD_RELOC_MICROMIPS_SCN_DISP:
+ case BFD_RELOC_MICROMIPS_JALR:
+ case BFD_RELOC_MICROMIPS_HI16:
+ case BFD_RELOC_MICROMIPS_HI16_S:
+ case BFD_RELOC_MICROMIPS_GPREL16:
+ case BFD_RELOC_MICROMIPS_LITERAL:
+ case BFD_RELOC_MICROMIPS_CALL16:
+ case BFD_RELOC_MICROMIPS_GOT16:
+ case BFD_RELOC_MICROMIPS_GOT_HI16:
+ case BFD_RELOC_MICROMIPS_GOT_LO16:
+ case BFD_RELOC_MICROMIPS_CALL_HI16:
+ case BFD_RELOC_MICROMIPS_CALL_LO16:
/* Nothing needed to do. The value comes from the reloc entry. */
break;
case BFD_RELOC_LO16:
case BFD_RELOC_MIPS16_LO16:
+ case BFD_RELOC_MICROMIPS_LO16:
/* FIXME: Now that embedded-PIC is gone, some of this code/comment
may be safe to remove, but if so it's not obvious. */
/* When handling an embedded PIC switch statement, we can wind
if (*valP + 0x8000 > 0xffff)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("relocation overflow"));
- if (target_big_endian)
+ /* 32-bit microMIPS instructions are divided into two halfwords.
+ Relocations always refer to the second halfword, regardless
+ of endianness. */
+ if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16)
buf += 2;
md_number_to_chars ((char *) buf, *valP, 2);
}
}
break;
+ case BFD_RELOC_MICROMIPS_7_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_10_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_16_PCREL_S1:
+ /* We adjust the offset back to even. */
+ if ((*valP & 0x1) != 0)
+ --(*valP);
+
+ if (! fixP->fx_done)
+ break;
+
+ /* Should never visit here, because we keep the relocation. */
+ abort ();
+ break;
+
case BFD_RELOC_VTABLE_INHERIT:
fixP->fx_done = 0;
if (fixP->fx_addsy
mips_align (int to, int *fill, symbolS *label)
{
mips_emit_delays ();
- mips_record_mips16_mode ();
+ mips_record_compressed_mode ();
if (fill == NULL && subseg_text_p (now_seg))
frag_align_code (to, 0);
else
mips_opts.single_float = 0;
else if (strcmp (name, "mips16") == 0
|| strcmp (name, "MIPS-16") == 0)
- mips_opts.mips16 = 1;
+ {
+ if (mips_opts.micromips == 1)
+ as_fatal (_("`mips16' cannot be used with `micromips'"));
+ mips_opts.mips16 = 1;
+ }
else if (strcmp (name, "nomips16") == 0
|| strcmp (name, "noMIPS-16") == 0)
mips_opts.mips16 = 0;
+ else if (strcmp (name, "micromips") == 0)
+ {
+ if (mips_opts.mips16 == 1)
+ as_fatal (_("`micromips' cannot be used with `mips16'"));
+ mips_opts.micromips = 1;
+ }
+ else if (strcmp (name, "nomicromips") == 0)
+ mips_opts.micromips = 0;
else if (strcmp (name, "smartmips") == 0)
{
if (!ISA_SUPPORTS_SMARTMIPS)
if (mips_in_shared || HAVE_64BIT_SYMBOLS)
{
- macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
+ macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
-1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
BFD_RELOC_HI16_S);
}
/* Handle the .insn pseudo-op. This marks instruction labels in
- mips16 mode. This permits the linker to handle them specially,
+ mips16/micromips mode. This permits the linker to handle them specially,
such as generating jalx instructions when needed. We also make
them odd for the duration of the assembly, in order to generate the
right sort of code. We will make them even in the adjust_symtab
static void
s_insn (int ignore ATTRIBUTE_UNUSED)
{
- mips16_mark_labels ();
+ mips_mark_labels ();
demand_empty_rest_of_line ();
}
s_mips_stab (int type)
{
if (type == 'n')
- mips16_mark_labels ();
+ mips_mark_labels ();
s_stab (type);
}
return length;
}
+/* Compute the length of a branch sequence, and adjust the
+ RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
+ worst-case length is computed, with UPDATE being used to indicate
+ whether an unconditional (-1), or regular (0) branch is to be
+ computed. */
+
+static int
+relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
+{
+ bfd_boolean toofar;
+ int length;
+
+ if (fragp
+ && S_IS_DEFINED (fragp->fr_symbol)
+ && sec == S_GET_SEGMENT (fragp->fr_symbol))
+ {
+ addressT addr;
+ offsetT val;
+
+ val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
+ /* Ignore the low bit in the target, since it will be set
+ for a text label. */
+ if ((val & 1) != 0)
+ --val;
+
+ addr = fragp->fr_address + fragp->fr_fix + 4;
+
+ val -= addr;
+
+ toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
+ }
+ else if (fragp)
+ /* If the symbol is not defined or it's in a different segment,
+ assume the user knows what's going on and emit a short
+ branch. */
+ toofar = FALSE;
+ else
+ toofar = TRUE;
+
+ if (fragp && update
+ && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
+ fragp->fr_subtype = (toofar
+ ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
+ : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
+
+ length = 4;
+ if (toofar)
+ {
+ bfd_boolean compact_known = fragp != NULL;
+ bfd_boolean compact = FALSE;
+ bfd_boolean uncond;
+
+ if (compact_known)
+ compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
+ if (fragp)
+ uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
+ else
+ uncond = update < 0;
+
+ /* If label is out of range, we turn branch <br>:
+
+ <br> label # 4 bytes
+ 0:
+
+ into:
+
+ j label # 4 bytes
+ nop # 2 bytes if compact && !PIC
+ 0:
+ */
+ if (mips_pic == NO_PIC && (!compact_known || compact))
+ length += 2;
+
+ /* If assembling PIC code, we further turn:
+
+ j label # 4 bytes
+
+ into:
+
+ lw/ld at, %got(label)(gp) # 4 bytes
+ d/addiu at, %lo(label) # 4 bytes
+ jr/c at # 2 bytes
+ */
+ if (mips_pic != NO_PIC)
+ length += 6;
+
+ /* If branch <br> is conditional, we prepend negated branch <brneg>:
+
+ <brneg> 0f # 4 bytes
+ nop # 2 bytes if !compact
+ */
+ if (!uncond)
+ length += (compact_known && compact) ? 4 : 6;
+ }
+
+ return length;
+}
+
+/* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
+ bit accordingly. */
+
+static int
+relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
+{
+ bfd_boolean toofar;
+
+ if (RELAX_MICROMIPS_U16BIT (fragp->fr_subtype))
+ return 2;
+
+ if (fragp
+ && S_IS_DEFINED (fragp->fr_symbol)
+ && sec == S_GET_SEGMENT (fragp->fr_symbol))
+ {
+ addressT addr;
+ offsetT val;
+ int type;
+
+ val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
+ /* Ignore the low bit in the target, since it will be set
+ for a text label. */
+ if ((val & 1) != 0)
+ --val;
+
+ /* Assume this is a 2-byte branch. */
+ addr = fragp->fr_address + fragp->fr_fix + 2;
+
+ /* We try to avoid the infinite loop by not adding 2 more bytes for
+ long branches. */
+
+ val -= addr;
+
+ type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
+ if (type == 'D')
+ toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
+ else if (type == 'E')
+ toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
+ else
+ abort ();
+ }
+ else
+ /* If the symbol is not defined or it's in a different segment,
+ we emit a normal 32-bit branch. */
+ toofar = TRUE;
+
+ if (fragp && update
+ && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
+ fragp->fr_subtype
+ = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
+ : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
+
+ if (toofar)
+ return 4;
+
+ return 2;
+}
+
/* Estimate the size of a frag before relaxing. Unless this is the
mips16, we are not really relaxing here, and the final size is
encoded in the subtype information. For the mips16, we have to
into infinite loops. We change it only in mips_relax_frag(). */
return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
+ if (RELAX_MICROMIPS_P (fragp->fr_subtype))
+ {
+ int length = 4;
+
+ if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
+ length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
+ if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
+ length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
+ fragp->fr_var = length;
+
+ return length;
+ }
+
if (mips_pic == NO_PIC)
change = nopic_need_relax (fragp->fr_symbol, 0);
else if (mips_pic == SVR4_PIC)
the in-place relocatable field if recalculated against the start
address of the symbol's containing section. */
if (HAVE_IN_PLACE_ADDENDS
- && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
+ && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
return 0;
#ifdef OBJ_ELF
There is a further restriction:
- 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
- on targets with in-place addends; the relocation field cannot
+ 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
+ R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
+ targets with in-place addends; the relocation field cannot
encode the low bit.
- For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
- against a MIPS16 symbol.
+ For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
+ against a MIPS16 symbol. We deal with (5) by by not reducing any
+ such relocations on REL targets.
We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
relocation against some symbol R, no relocation against R may be
if (IS_ELF
&& fixp->fx_subsy == NULL
&& (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
- || *symbol_get_tc (fixp->fx_addsy)))
+ || *symbol_get_tc (fixp->fx_addsy)
+ || (HAVE_IN_PLACE_ADDENDS
+ && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
+ && jmp_reloc_p (fixp->fx_r_type))))
return 0;
#endif
if (fixp->fx_pcrel)
{
- gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
+ gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
/* At this point, fx_addnumber is "symbol offset - pcrel address".
Relocations want only the symbol offset. */
return fragp->fr_var - old_var;
}
+ if (RELAX_MICROMIPS_P (fragp->fr_subtype))
+ {
+ offsetT old_var = fragp->fr_var;
+ offsetT new_var = 4;
+
+ if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
+ new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
+ if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
+ new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
+ fragp->fr_var = new_var;
+
+ return new_var - old_var;
+ }
+
if (! RELAX_MIPS16_P (fragp->fr_subtype))
return 0;
return;
}
+ /* Relax microMIPS branches. */
+ if (RELAX_MICROMIPS_P (fragp->fr_subtype))
+ {
+ bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
+ bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
+ bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
+ int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
+ unsigned long jal, jalr, jr;
+
+ unsigned long insn;
+ expressionS exp;
+ fixS *fixp;
+
+ exp.X_op = O_symbol;
+ exp.X_add_symbol = fragp->fr_symbol;
+ exp.X_add_number = fragp->fr_offset;
+
+ fragp->fr_fix += fragp->fr_var;
+
+ /* Handle 16-bit branches that fit or are forced to fit. */
+ if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
+ {
+ /* We generate a fixup instead of applying it right now,
+ because if there is linker relaxation, we're going to
+ need the relocations. */
+ if (type == 'D')
+ fixp = fix_new_exp (fragp,
+ buf - (bfd_byte *) fragp->fr_literal,
+ 2, &exp, TRUE,
+ BFD_RELOC_MICROMIPS_10_PCREL_S1);
+ else if (type == 'E')
+ fixp = fix_new_exp (fragp,
+ buf - (bfd_byte *) fragp->fr_literal,
+ 2, &exp, TRUE,
+ BFD_RELOC_MICROMIPS_7_PCREL_S1);
+ else
+ abort ();
+
+ fixp->fx_file = fragp->fr_file;
+ fixp->fx_line = fragp->fr_line;
+
+ /* These relocations can have an addend that won't fit in
+ 2 octets. */
+ fixp->fx_no_overflow = 1;
+
+ return;
+ }
+
+ /* Handle 32-bit branches that fit or forced to fit. */
+ if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
+ || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
+ {
+ /* We generate a fixup instead of applying it right now,
+ because if there is linker relaxation, we're going to
+ need the relocations. */
+ fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
+ 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
+ fixp->fx_file = fragp->fr_file;
+ fixp->fx_line = fragp->fr_line;
+
+ if (type == 0)
+ return;
+ }
+
+ /* Relax 16-bit branches to 32-bit branches. */
+ if (type != 0)
+ {
+ if (target_big_endian)
+ insn = bfd_getb16 (buf);
+ else
+ insn = bfd_getl16 (buf);
+
+ if ((insn & 0xfc00) == 0xcc00) /* b16 */
+ insn = 0x94000000; /* beq */
+ else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
+ {
+ unsigned long regno;
+
+ regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
+ regno = micromips_to_32_reg_d_map [regno];
+ insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
+ insn |= regno << MICROMIPSOP_SH_RS;
+ }
+ else
+ abort ();
+
+ /* Nothing else to do, just write it out. */
+ if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
+ || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
+ {
+ md_number_to_chars ((char *) buf, insn >> 16, 2);
+ buf += 2;
+ md_number_to_chars ((char *) buf, insn & 0xffff, 2);
+ buf += 2;
+
+ gas_assert (buf == ((bfd_byte *) fragp->fr_literal
+ + fragp->fr_fix));
+ return;
+ }
+ }
+ else
+ {
+ unsigned long next;
+
+ if (target_big_endian)
+ {
+ insn = bfd_getb16 (buf);
+ next = bfd_getb16 (buf + 2);
+ }
+ else
+ {
+ insn = bfd_getl16 (buf);
+ next = bfd_getl16 (buf + 2);
+ }
+ insn = (insn << 16) | next;
+ }
+
+ /* Relax 32-bit branches to a sequence of instructions. */
+ as_warn_where (fragp->fr_file, fragp->fr_line,
+ _("Relaxed out-of-range branch into a jump"));
+
+ /* Check the short-delay-slot bit. */
+ if (al && (insn & 0x02000000) != 0)
+ {
+ jal = 0x74000000; /* jals */
+ jalr = 0x45e0; /* jalrs */
+ }
+ else
+ {
+ jal = 0xf4000000; /* jal */
+ jalr = 0x45c0; /* jalr */
+ }
+ jr = compact ? 0x45a0 : 0x4580; /* jr/c */
+
+ if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
+ {
+ symbolS *l;
+
+ /* Reverse the branch. */
+ if ((insn & 0xfc000000) == 0x94000000 /* beq */
+ || (insn & 0xfc000000) == 0xb4000000) /* bne */
+ insn ^= 0x20000000;
+ else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
+ || (insn & 0xffe00000) == 0x40400000 /* bgez */
+ || (insn & 0xffe00000) == 0x40800000 /* blez */
+ || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
+ || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
+ || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
+ || (insn & 0xffe00000) == 0x40200000 /* bltzal */
+ || (insn & 0xffe00000) == 0x40600000 /* bgezal */
+ || (insn & 0xffe00000) == 0x42200000 /* bltzals */
+ || (insn & 0xffe00000) == 0x42600000) /* bgezals */
+ insn ^= 0x00400000;
+ else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
+ || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
+ || (insn & 0xffe30000) == 0x42800000 /* bc2f */
+ || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
+ insn ^= 0x00200000;
+ else
+ abort ();
+
+ if (al)
+ {
+ /* Clear the and-link and short-delay-slot bits. */
+ gas_assert ((insn & 0xfda00000) == 0x40200000);
+
+ /* bltzal 0x40200000 bgezal 0x40600000 */
+ /* bltzals 0x42200000 bgezals 0x42600000 */
+ insn &= ~0x02200000;
+ }
+
+ /* Make a label at the end for use with the branch. */
+ l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
+ micromips_label_inc ();
+#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
+ if (IS_ELF)
+ S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
+#endif
+
+ /* Refer to it. */
+ fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal,
+ 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
+ fixp->fx_file = fragp->fr_file;
+ fixp->fx_line = fragp->fr_line;
+
+ /* Branch over the jump. */
+ md_number_to_chars ((char *) buf, insn >> 16, 2);
+ buf += 2;
+ md_number_to_chars ((char *) buf, insn & 0xffff, 2);
+ buf += 2;
+
+ if (!compact)
+ {
+ /* nop */
+ insn = 0x0c00;
+ md_number_to_chars ((char *) buf, insn, 2);
+ buf += 2;
+ }
+ }
+
+ if (mips_pic == NO_PIC)
+ {
+ /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
+ insn = al ? jal : 0xd4000000;
+
+ fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
+ 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP);
+ fixp->fx_file = fragp->fr_file;
+ fixp->fx_line = fragp->fr_line;
+
+ md_number_to_chars ((char *) buf, insn >> 16, 2);
+ buf += 2;
+ md_number_to_chars ((char *) buf, insn & 0xffff, 2);
+ buf += 2;
+
+ if (compact)
+ {
+ /* nop */
+ insn = 0x0c00;
+ md_number_to_chars ((char *) buf, insn, 2);
+ buf += 2;
+ }
+ }
+ else
+ {
+ unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
+
+ /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
+ insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
+ insn |= at << MICROMIPSOP_SH_RT;
+
+ if (exp.X_add_number)
+ {
+ exp.X_add_symbol = make_expr_symbol (&exp);
+ exp.X_add_number = 0;
+ }
+
+ fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
+ 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16);
+ fixp->fx_file = fragp->fr_file;
+ fixp->fx_line = fragp->fr_line;
+
+ md_number_to_chars ((char *) buf, insn >> 16, 2);
+ buf += 2;
+ md_number_to_chars ((char *) buf, insn & 0xffff, 2);
+ buf += 2;
+
+ /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
+ insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
+ insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
+
+ fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
+ 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16);
+ fixp->fx_file = fragp->fr_file;
+ fixp->fx_line = fragp->fr_line;
+
+ md_number_to_chars ((char *) buf, insn >> 16, 2);
+ buf += 2;
+ md_number_to_chars ((char *) buf, insn & 0xffff, 2);
+ buf += 2;
+
+ /* jr/jrc/jalr/jalrs $at */
+ insn = al ? jalr : jr;
+ insn |= at << MICROMIPSOP_SH_MJ;
+
+ md_number_to_chars ((char *) buf, insn & 0xffff, 2);
+ buf += 2;
+ }
+
+ gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix);
+ return;
+ }
+
if (RELAX_MIPS16_P (fragp->fr_subtype))
{
int type;
}
else
{
+ relax_substateT subtype = fragp->fr_subtype;
+ bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
+ bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
int first, second;
fixS *fixp;
- first = RELAX_FIRST (fragp->fr_subtype);
- second = RELAX_SECOND (fragp->fr_subtype);
+ first = RELAX_FIRST (subtype);
+ second = RELAX_SECOND (subtype);
fixp = (fixS *) fragp->fr_opcode;
+ /* If the delay slot chosen does not match the size of the instruction,
+ then emit a warning. */
+ if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
+ || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
+ {
+ relax_substateT s;
+ const char *msg;
+
+ s = subtype & (RELAX_DELAY_SLOT_16BIT
+ | RELAX_DELAY_SLOT_SIZE_FIRST
+ | RELAX_DELAY_SLOT_SIZE_SECOND);
+ msg = macro_warning (s);
+ if (msg != NULL)
+ as_warn_where (fragp->fr_file, fragp->fr_line, msg);
+ subtype &= ~s;
+ }
+
/* Possibly emit a warning if we've chosen the longer option. */
- if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
- == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
+ if (use_second == second_longer)
{
- const char *msg = macro_warning (fragp->fr_subtype);
- if (msg != 0)
- as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
+ relax_substateT s;
+ const char *msg;
+
+ s = (subtype
+ & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
+ msg = macro_warning (s);
+ if (msg != NULL)
+ as_warn_where (fragp->fr_file, fragp->fr_line, msg);
+ subtype &= ~s;
}
/* Go through all the fixups for the first sequence. Disable them
&& fixp->fx_frag == fragp
&& fixp->fx_where < fragp->fr_fix - second)
{
- if (fragp->fr_subtype & RELAX_USE_SECOND)
+ if (subtype & RELAX_USE_SECOND)
fixp->fx_done = 1;
fixp = fixp->fx_next;
}
addresses to account for the relaxation. */
while (fixp && fixp->fx_frag == fragp)
{
- if (fragp->fr_subtype & RELAX_USE_SECOND)
+ if (subtype & RELAX_USE_SECOND)
fixp->fx_where -= first;
else
fixp->fx_done = 1;
}
/* Now modify the frag contents. */
- if (fragp->fr_subtype & RELAX_USE_SECOND)
+ if (subtype & RELAX_USE_SECOND)
{
char *start;
syms = bfd_get_outsymbols (stdoutput);
count = bfd_get_symcount (stdoutput);
for (i = 0; i < count; i++, syms++)
- {
- if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
- && ((*syms)->value & 1) != 0)
- {
- (*syms)->value &= ~1;
- /* If the symbol has an odd size, it was probably computed
- incorrectly, so adjust that as well. */
- if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
- ++elf_symbol (*syms)->internal_elf_sym.st_size;
- }
- }
+ if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
+ && ((*syms)->value & 1) != 0)
+ {
+ (*syms)->value &= ~1;
+ /* If the symbol has an odd size, it was probably computed
+ incorrectly, so adjust that as well. */
+ if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
+ ++elf_symbol (*syms)->internal_elf_sym.st_size;
+ }
}
#endif
file_ase_mt is true. */
if (file_ase_mips16)
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
+ if (file_ase_micromips)
+ elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
#if 0 /* XXX FIXME */
if (file_ase_mips3d)
elf_elfheader (stdoutput)->e_flags |= ???;
static procS *cur_proc_ptr;
static int numprocs;
-/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
- nop as "0". */
+/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
+ as "2", and a normal nop as "0". */
+
+#define NOP_OPCODE_MIPS 0
+#define NOP_OPCODE_MIPS16 1
+#define NOP_OPCODE_MICROMIPS 2
char
mips_nop_opcode (void)
{
- return seg_info (now_seg)->tc_segment_info_data.mips16;
+ if (seg_info (now_seg)->tc_segment_info_data.micromips)
+ return NOP_OPCODE_MICROMIPS;
+ else if (seg_info (now_seg)->tc_segment_info_data.mips16)
+ return NOP_OPCODE_MIPS16;
+ else
+ return NOP_OPCODE_MIPS;
}
-/* Fill in an rs_align_code fragment. This only needs to do something
- for MIPS16 code, where 0 is not a nop. */
+/* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
+ 32-bit microMIPS NOPs here (if applicable). */
void
mips_handle_align (fragS *fragp)
{
+ char nop_opcode;
char *p;
int bytes, size, excess;
valueT opcode;
return;
p = fragp->fr_literal + fragp->fr_fix;
- if (*p)
+ nop_opcode = *p;
+ switch (nop_opcode)
{
+ case NOP_OPCODE_MICROMIPS:
+ opcode = micromips_nop32_insn.insn_opcode;
+ size = 4;
+ break;
+ case NOP_OPCODE_MIPS16:
opcode = mips16_nop_insn.insn_opcode;
size = 2;
- }
- else
- {
+ break;
+ case NOP_OPCODE_MIPS:
+ default:
opcode = nop_insn.insn_opcode;
size = 4;
+ break;
}
bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
excess = bytes % size;
- if (excess != 0)
+
+ /* Handle the leading part if we're not inserting a whole number of
+ instructions, and make it the end of the fixed part of the frag.
+ Try to fit in a short microMIPS NOP if applicable and possible,
+ and use zeroes otherwise. */
+ gas_assert (excess < 4);
+ fragp->fr_fix += excess;
+ switch (excess)
{
- /* If we're not inserting a whole number of instructions,
- pad the end of the fixed part of the frag with zeros. */
- memset (p, 0, excess);
- p += excess;
- fragp->fr_fix += excess;
+ case 3:
+ *p++ = '\0';
+ /* Fall through. */
+ case 2:
+ if (nop_opcode == NOP_OPCODE_MICROMIPS)
+ {
+ md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2);
+ p += 2;
+ break;
+ }
+ *p++ = '\0';
+ /* Fall through. */
+ case 1:
+ *p++ = '\0';
+ /* Fall through. */
+ case 0:
+ break;
}
md_number_to_chars (p, opcode, size);
-mips16 generate mips16 instructions\n\
-no-mips16 do not generate mips16 instructions\n"));
fprintf (stream, _("\
+-mmicromips generate microMIPS instructions\n\
+-mno-micromips do not generate microMIPS instructions\n"));
+ fprintf (stream, _("\
-msmartmips generate smartmips instructions\n\
-mno-smartmips do not generate smartmips instructions\n"));
fprintf (stream, _("\
struct mips_segment_info {
struct insn_label_list *labels;
unsigned int mips16 : 1;
+ unsigned int micromips : 1;
};
#define TC_SEGMENT_INFO_TYPE struct mips_segment_info
[@b{-construct-floats}] [@b{-no-construct-floats}]
[@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}]
[@b{-mips16}] [@b{-no-mips16}]
+ [@b{-mmicromips}] [@b{-mno-micromips}]
[@b{-msmartmips}] [@b{-mno-smartmips}]
[@b{-mips3d}] [@b{-no-mips3d}]
[@b{-mdmx}] [@b{-no-mdmx}]
@code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
turns off this option.
+@item -mmicromips
+@itemx -mno-micromips
+Generate code for the microMIPS processor. This is equivalent to putting
+@code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
+turns off this option. This is equivalent to putting @code{.set nomicromips}
+at the start of the assembly file.
+
@item -msmartmips
@itemx -mno-smartmips
Enables the SmartMIPS extension to the MIPS32 instruction set. This is
@code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
turns off this option.
+@item -mmicromips
+@itemx -mno-micromips
+Generate code for the microMIPS processor. This is equivalent to putting
+@code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
+turns off this option. This is equivalent to putting @code{.set nomicromips}
+at the start of the assembly file.
+
@item -msmartmips
@itemx -mno-smartmips
Enables the SmartMIPS extensions to the MIPS32 instruction set, which
Traditional @sc{mips} assemblers do not support this directive.
+The directive @code{.set micromips} puts the assembler into microMIPS mode,
+in which it will assemble instructions for the microMIPS processor. Use
+@code{.set nomicromips} to return to normal 32 bit mode.
+
+Traditional @sc{mips} assemblers do not support this directive.
+
@node MIPS autoextend
@section Directives for extending MIPS 16 bit instructions
@kindex @code{.insn}
The @code{.insn} directive tells @code{@value{AS}} that the following
-data is actually instructions. This makes a difference in MIPS 16 mode:
-when loading the address of a label which precedes instructions,
-@code{@value{AS}} automatically adds 1 to the value, so that jumping to
-the loaded address will do the right thing.
+data is actually instructions. This makes a difference in MIPS 16 and
+microMIPS modes: when loading the address of a label which precedes
+instructions, @code{@value{AS}} automatically adds 1 to the value, so
+that jumping to the loaded address will do the right thing.
@kindex @code{.global}
The @code{.global} and @code{.globl} directives supported by
#define DOLLAR_LABEL_CHAR '\001'
#define LOCAL_LABEL_CHAR '\002'
+#ifndef TC_LABEL_IS_LOCAL
+#define TC_LABEL_IS_LOCAL(name) 0
+#endif
+
struct obstack notes;
#ifdef TE_PE
/* The name of an external symbol which is
&& ! S_IS_DEBUG (s)
&& (strchr (name, DOLLAR_LABEL_CHAR)
|| strchr (name, LOCAL_LABEL_CHAR)
+ || TC_LABEL_IS_LOCAL (name)
|| (! flag_keep_locals
&& (bfd_is_local_label (stdoutput, s->bsym)
|| (flag_mri
+2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
+ Chao-ying Fu <fu@mips.com>
+ Richard Sandiford <rdsandiford@googlemail.com>
+
+ * gas/mips/micromips.d: New test.
+ * gas/mips/micromips-branch-delay.d: Likewise.
+ * gas/mips/micromips-branch-relax.d: Likewise.
+ * gas/mips/micromips-branch-relax-pic.d: Likewise.
+ * gas/mips/micromips-size-1.d: Likewise.
+ * gas/mips/micromips-trap.d: Likewise.
+ * gas/mips/micromips.l: New stderr output.
+ * gas/mips/micromips-branch-delay.l: Likewise.
+ * gas/mips/micromips-branch-relax.l: Likewise.
+ * gas/mips/micromips-branch-relax-pic.l: Likewise.
+ * gas/mips/micromips-size-0.l: New list test.
+ * gas/mips/micromips-size-1.l: New stderr output.
+ * gas/mips/micromips.s: New test source.
+ * gas/mips/micromips-branch-delay.s: Likewise.
+ * gas/mips/micromips-branch-relax.s: Likewise.
+ * gas/mips/micromips-size-0.s: Likewise.
+ * gas/mips/micromips-size-1.s: Likewise.
+ * gas/mips/mips.exp: Run the new tests.
+
+ * gas/mips/dli.s: Use .p2align.
+ * gas/mips/elf_ase_micromips.d: New test.
+ * gas/mips/elf_ase_micromips-2.d: Likewise.
+ * gas/mips/micromips@abs.d: Likewise.
+ * gas/mips/micromips@add.d: Likewise.
+ * gas/mips/micromips@alnv_ps-swap.d: Likewise.
+ * gas/mips/micromips@and.d: Likewise.
+ * gas/mips/micromips@beq.d: Likewise.
+ * gas/mips/micromips@bge.d: Likewise.
+ * gas/mips/micromips@bgeu.d: Likewise.
+ * gas/mips/micromips@blt.d: Likewise.
+ * gas/mips/micromips@bltu.d: Likewise.
+ * gas/mips/micromips@branch-likely.d: Likewise.
+ * gas/mips/micromips@branch-misc-1.d: Likewise.
+ * gas/mips/micromips@branch-misc-2-64.d: Likewise.
+ * gas/mips/micromips@branch-misc-2.d: Likewise.
+ * gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
+ * gas/mips/micromips@branch-misc-2pic.d: Likewise.
+ * gas/mips/micromips@branch-misc-4-64.d: Likewise.
+ * gas/mips/micromips@branch-misc-4.d: Likewise.
+ * gas/mips/micromips@branch-self.d: Likewise.
+ * gas/mips/micromips@cache.d: Likewise.
+ * gas/mips/micromips@daddi.d: Likewise.
+ * gas/mips/micromips@dli.d: Likewise.
+ * gas/mips/micromips@elf-jal.d: Likewise.
+ * gas/mips/micromips@elf-rel2.d: Likewise.
+ * gas/mips/micromips@elfel-rel2.d: Likewise.
+ * gas/mips/micromips@elf-rel4.d: Likewise.
+ * gas/mips/micromips@jal-svr4pic.d: Likewise.
+ * gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
+ * gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
+ * gas/mips/micromips@li.d: Likewise.
+ * gas/mips/micromips@loc-swap-dis.d: Likewise.
+ * gas/mips/micromips@loc-swap.d: Likewise.
+ * gas/mips/micromips@mips1-fp.d: Likewise.
+ * gas/mips/micromips@mips32-cp2.d: Likewise.
+ * gas/mips/micromips@mips32-imm.d: Likewise.
+ * gas/mips/micromips@mips32-sf32.d: Likewise.
+ * gas/mips/micromips@mips32.d: Likewise.
+ * gas/mips/micromips@mips32r2-cp2.d: Likewise.
+ * gas/mips/micromips@mips32r2-fp32.d: Likewise.
+ * gas/mips/micromips@mips32r2-sync.d: Likewise.
+ * gas/mips/micromips@mips32r2.d: Likewise.
+ * gas/mips/micromips@mips4-branch-likely.d: Likewise.
+ * gas/mips/micromips@mips4-fp.d: Likewise.
+ * gas/mips/micromips@mips4.d: Likewise.
+ * gas/mips/micromips@mips5.d: Likewise.
+ * gas/mips/micromips@mips64-cp2.d: Likewise.
+ * gas/mips/micromips@mips64.d: Likewise.
+ * gas/mips/micromips@mips64r2.d: Likewise.
+ * gas/mips/micromips@pref.d: Likewise.
+ * gas/mips/micromips@relax-at.d: Likewise.
+ * gas/mips/micromips@relax.d: Likewise.
+ * gas/mips/micromips@rol-hw.d: Likewise.
+ * gas/mips/micromips@uld2-eb.d: Likewise.
+ * gas/mips/micromips@uld2-el.d: Likewise.
+ * gas/mips/micromips@ulh2-eb.d: Likewise.
+ * gas/mips/micromips@ulh2-el.d: Likewise.
+ * gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
+ * gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
+ * gas/mips/cache.d: Likewise.
+ * gas/mips/daddi.d: Likewise.
+ * gas/mips/mips32-imm.d: Likewise.
+ * gas/mips/pref.d: Likewise.
+ * gas/mips/elf-rel27.d: Handle microMIPS ASE.
+ * gas/mips/l_d.d: Likewise.
+ * gas/mips/l_d-n32.d: Likewise.
+ * gas/mips/l_d-n64.d: Likewise.
+ * gas/mips/ld.d: Likewise.
+ * gas/mips/ld-n32.d: Likewise.
+ * gas/mips/ld-n64.d: Likewise.
+ * gas/mips/s_d.d: Likewise.
+ * gas/mips/s_d-n32.d: Likewise.
+ * gas/mips/s_d-n64.d: Likewise.
+ * gas/mips/sd.d: Likewise.
+ * gas/mips/sd-n32.d: Likewise.
+ * gas/mips/sd-n64.d: Likewise.
+ * gas/mips/mips32.d: Update immediates.
+ * gas/mips/micromips@mips32-cp2.s: New test source.
+ * gas/mips/micromips@mips32-imm.s: Likewise.
+ * gas/mips/micromips@mips32r2-cp2.s: Likewise.
+ * gas/mips/micromips@mips64-cp2.s: Likewise.
+ * gas/mips/cache.s: Likewise.
+ * gas/mips/daddi.s: Likewise.
+ * gas/mips/mips32-imm.s: Likewise.
+ * gas/mips/elf-rel4.s: Handle microMIPS ASE.
+ * gas/mips/lb-pic.s: Likewise.
+ * gas/mips/ld.s: Likewise.
+ * gas/mips/mips32.s: Likewise.
+ * gas/mips/mips.exp: Add the micromips arch. Exclude mips16e
+ from micromips. Run mips32-imm.
+
+ * gas/mips/jal-mask-11.d: New test.
+ * gas/mips/jal-mask-12.d: Likewise.
+ * gas/mips/micromips@jal-mask-11.d: Likewise.
+ * gas/mips/jal-mask-1.s: Source for the new tests.
+ * gas/mips/jal-mask-21.d: New test.
+ * gas/mips/jal-mask-22.d: Likewise.
+ * gas/mips/micromips@jal-mask-12.d: Likewise.
+ * gas/mips/jal-mask-2.s: Source for the new tests.
+ * gas/mips/mips.exp: Run the new tests.
+
+ * gas/mips/mips16-e.d: Add --special-syms to `objdump'.
+ * gas/mips/tmips16-e.d: Likewise.
+ * gas/mips/mipsel16-e.d: Likewise.
+ * gas/mips/tmipsel16-e.d: Likewise.
+
+ * gas/mips/and.s: Adjust padding.
+ * gas/mips/beq.s: Likewise.
+ * gas/mips/bge.s: Likewise.
+ * gas/mips/bgeu.s: Likewise.
+ * gas/mips/blt.s: Likewise.
+ * gas/mips/bltu.s: Likewise.
+ * gas/mips/branch-misc-2.s: Likewise.
+ * gas/mips/jal.s: Likewise.
+ * gas/mips/li.s: Likewise.
+ * gas/mips/mips4.s: Likewise.
+ * gas/mips/mips4-fp.s: Likewise.
+ * gas/mips/relax.s: Likewise.
+ * gas/mips/and.d: Update accordingly.
+ * gas/mips/elf-jal.d: Likewise.
+ * gas/mips/jal.d: Likewise.
+ * gas/mips/li.d: Likewise.
+ * gas/mips/relax-at.d: Likewise.
+ * gas/mips/relax.d: Likewise.
+
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/k1om.d: New.
0+0058 <[^>]*> nor a0,a1,at
0+005c <[^>]*> ori a0,a1,0x0
0+0060 <[^>]*> xori a0,a1,0x0
- ...
+ \.\.\.
xor $4,$5,0
- # Round to a 16 byte boundary, for ease in testing multiple targets.
- nop
- nop
- nop
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
# bal external_label
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
.space 8
bge $4,$5,external_label
bgt $4,$5,external_label
-# Round to a 16 byte boundary, for ease in testing multiple targets.
- nop
- nop
- nop
- nop
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
bgeu $4,$5,external_label
bgtu $4,$5,external_label
-# Round to a 16 byte boundary, for ease in testing multiple targets.
- nop
- nop
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
blt $4,$5,external_label
ble $4,$5,external_label
-# Round to a 16 byte boundary, for ease in testing multiple targets.
- nop
- nop
- nop
- nop
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
bltu $4,$5,external_label
bleu $4,$5,external_label
-# Round to a 16 byte boundary, for ease in testing multiple targets.
- nop
- nop
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
b .Ldata
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
.space 8
.data
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS CACHE instruction
+#as: -32
+
+# Check MIPS CACHE instruction assembly.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> bc4507ff cache 0x5,2047\(v0\)
+[0-9a-f]+ <[^>]*> bc65f800 cache 0x5,-2048\(v1\)
+[0-9a-f]+ <[^>]*> bc850800 cache 0x5,2048\(a0\)
+[0-9a-f]+ <[^>]*> bca5f7ff cache 0x5,-2049\(a1\)
+[0-9a-f]+ <[^>]*> bcc57fff cache 0x5,32767\(a2\)
+[0-9a-f]+ <[^>]*> bce58000 cache 0x5,-32768\(a3\)
+[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1
+[0-9a-f]+ <[^>]*> 00280821 addu at,at,t0
+[0-9a-f]+ <[^>]*> bc258000 cache 0x5,-32768\(at\)
+[0-9a-f]+ <[^>]*> 3c01ffff lui at,0xffff
+[0-9a-f]+ <[^>]*> 00290821 addu at,at,t1
+[0-9a-f]+ <[^>]*> bc257fff cache 0x5,32767\(at\)
+[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1
+[0-9a-f]+ <[^>]*> 002a0821 addu at,at,t2
+[0-9a-f]+ <[^>]*> bc259000 cache 0x5,-28672\(at\)
+[0-9a-f]+ <[^>]*> 3c01ffff lui at,0xffff
+[0-9a-f]+ <[^>]*> 002b0821 addu at,at,t3
+[0-9a-f]+ <[^>]*> bc256fff cache 0x5,28671\(at\)
+ \.\.\.
--- /dev/null
+# Source file to test offsets used with the CACHE and PREF instruction.
+
+# By default test CACHE.
+
+# If defined, test PREF.
+ .ifdef tpref
+ .macro cache ops:vararg
+ pref \ops
+ .endm
+ .endif
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+
+ cache 5, 2047($2)
+ cache 5, -2048($3)
+
+ # 12 bits accepted for microMIPS code.
+ .ifdef micromips
+ .set at
+ .endif
+ cache 5, 2048($4)
+ cache 5, -2049($5)
+ cache 5, 32767($6)
+ cache 5, -32768($7)
+
+ # 16 bits accepted for standard MIPS code.
+ .ifndef micromips
+ .set at
+ .endif
+ cache 5, 32768($8)
+ cache 5, -32769($9)
+ cache 5, 36864($10)
+ cache 5, -36865($11)
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DADDI instruction
+#as: -32
+
+# Check MIPS DADDI instruction assembly.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 604301ff daddi v1,v0,511
+[0-9a-f]+ <[^>]*> 6085fe00 daddi a1,a0,-512
+[0-9a-f]+ <[^>]*> 60c70200 daddi a3,a2,512
+[0-9a-f]+ <[^>]*> 6109fdff daddi t1,t0,-513
+[0-9a-f]+ <[^>]*> 614b7fff daddi t3,t2,32767
+[0-9a-f]+ <[^>]*> 618d8000 daddi t5,t4,-32768
+[0-9a-f]+ <[^>]*> 34018000 li at,0x8000
+[0-9a-f]+ <[^>]*> 01c1782c dadd t7,t6,at
+[0-9a-f]+ <[^>]*> 3c01ffff lui at,0xffff
+[0-9a-f]+ <[^>]*> 34217fff ori at,at,0x7fff
+[0-9a-f]+ <[^>]*> 0201882c dadd s1,s0,at
+[0-9a-f]+ <[^>]*> 34018200 li at,0x8200
+[0-9a-f]+ <[^>]*> 0241982c dadd s3,s2,at
+[0-9a-f]+ <[^>]*> 3c01ffff lui at,0xffff
+[0-9a-f]+ <[^>]*> 34217dff ori at,at,0x7dff
+[0-9a-f]+ <[^>]*> 0281a82c dadd s5,s4,at
+ \.\.\.
--- /dev/null
+# Source file to test immediates used with the DADDI instruction.
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+
+ daddi $3, $2, 511
+ daddi $5, $4, -512
+
+ # 10 bits accepted for microMIPS code.
+ .ifdef micromips
+ .set at
+ .endif
+ daddi $7, $6, 512
+ daddi $9, $8, -513
+ daddi $11, $10, 32767
+ daddi $13, $12, -32768
+
+ # 16 bits accepted for standard MIPS code.
+ .ifndef micromips
+ .set at
+ .endif
+ dadd $15, $14, 32768
+ dadd $17, $16, -32769
+ dadd $19, $18, 33280
+ dadd $21, $20, -33281
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
dli $4,0x003ffc03ffffc000
# Round to a 16 byte boundary, for ease in testing multiple targets.
- nop
- nop
- nop
+ .p2align 4
0+0028 <[^>]*> j 0+ <text_label>
[ ]*28: (MIPS_JMP|JMPADDR|R_MIPS_26) external_text_label
0+002c <[^>]*> nop
+ \.\.\.
Relocation section '\.rel\.text' at offset .* contains [34] entries:
*Offset * Info * Type * Sym\. Value * Symbol's Name
-[0-9a-f]+ * [0-9a-f]+ R_(MIPS|MIPS16)_HI16 * [0-9a-f]+ * (\.text|\.L0)
-[0-9a-f]+ * [0-9a-f]+ R_(MIPS|MIPS16)_HI16 * [0-9a-f]+ * (\.text|\.L0)
-[0-9a-f]+ * [0-9a-f]+ R_(MIPS|MIPS16)_LO16 * [0-9a-f]+ * (\.text|\.L0)
+[0-9a-f]+ * [0-9a-f]+ R_(MIPS|MIPS16|MICROMIPS)_HI16 * [0-9a-f]+ * (\.text|\.L0)
+[0-9a-f]+ * [0-9a-f]+ R_(MIPS|MIPS16|MICROMIPS)_HI16 * [0-9a-f]+ * (\.text|\.L0)
+[0-9a-f]+ * [0-9a-f]+ R_(MIPS|MIPS16|MICROMIPS)_LO16 * [0-9a-f]+ * (\.text|\.L0)
+# There's an extra R_MICROMIPS_PC10_S1 relocation here for microMIPS
+# assembly. We don't care about it and the entry count regexp above
+# catches other possible discrepancies, hence:
+#pass
a: .4byte 2
.section .text
- la $4,a
+b: la $4,a
la $4,a+4
la $4,a+8
la $4,a+12
--- /dev/null
+# name: ELF microMIPS ASE markings 2
+# source: nop.s
+# objdump: -p
+# as: -32 -mmicromips
+
+.*:.*file format.*mips.*
+private flags = [0-9a-f]*[2367abef]......: .*[[,]micromips[],].*
+
--- /dev/null
+# name: ELF microMIPS ASE markings
+# source: empty.s
+# objdump: -p
+# as: -32 -mmicromips
+
+.*:.*file format.*mips.*
+!private flags = .*micromips.*
+
--- /dev/null
+ .text
+foo:
+ j 0x0000000
+ j 0xaaaaaa4
+ j 0x5555558
+ j 0xffffffc
+ jal 0x0000000
+ jal 0xaaaaaa4
+ jal 0x5555558
+ jal 0xffffffc
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn --adjust-vma=0x55555550
+#name: MIPS jal mask 1.1
+#as: -32
+#source: jal-mask-1.s
+
+# Check address masks for JAL/J instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+55555550 <[^>]*> 08000000 j 50000000 <[^>]*>
+55555554 <[^>]*> 00000000 nop
+55555558 <[^>]*> 0aaaaaa9 j 5aaaaaa4 <[^>]*>
+5555555c <[^>]*> 00000000 nop
+55555560 <[^>]*> 09555556 j 55555558 <[^>]*>
+55555564 <[^>]*> 00000000 nop
+55555568 <[^>]*> 0bffffff j 5ffffffc <[^>]*>
+5555556c <[^>]*> 00000000 nop
+55555570 <[^>]*> 0c000000 jal 50000000 <[^>]*>
+55555574 <[^>]*> 00000000 nop
+55555578 <[^>]*> 0eaaaaa9 jal 5aaaaaa4 <[^>]*>
+5555557c <[^>]*> 00000000 nop
+55555580 <[^>]*> 0d555556 jal 55555558 <[^>]*>
+55555584 <[^>]*> 00000000 nop
+55555588 <[^>]*> 0fffffff jal 5ffffffc <[^>]*>
+5555558c <[^>]*> 00000000 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn --adjust-vma=0xaaaaaaa0
+#name: MIPS jal mask 1.2
+#as: -32
+#source: jal-mask-1.s
+
+# Check address masks for JAL/J instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+aaaaaaa0 <[^>]*> 08000000 j a0000000 <[^>]*>
+aaaaaaa4 <[^>]*> 00000000 nop
+aaaaaaa8 <[^>]*> 0aaaaaa9 j aaaaaaa4 <[^>]*>
+aaaaaaac <[^>]*> 00000000 nop
+aaaaaab0 <[^>]*> 09555556 j a5555558 <[^>]*>
+aaaaaab4 <[^>]*> 00000000 nop
+aaaaaab8 <[^>]*> 0bffffff j affffffc <[^>]*>
+aaaaaabc <[^>]*> 00000000 nop
+aaaaaac0 <[^>]*> 0c000000 jal a0000000 <[^>]*>
+aaaaaac4 <[^>]*> 00000000 nop
+aaaaaac8 <[^>]*> 0eaaaaa9 jal aaaaaaa4 <[^>]*>
+aaaaaacc <[^>]*> 00000000 nop
+aaaaaad0 <[^>]*> 0d555556 jal a5555558 <[^>]*>
+aaaaaad4 <[^>]*> 00000000 nop
+aaaaaad8 <[^>]*> 0fffffff jal affffffc <[^>]*>
+aaaaaadc <[^>]*> 00000000 nop
+ \.\.\.
--- /dev/null
+ .text
+foo:
+ j 0x0000000
+ j 0xaaaaaa2
+ j 0x5555554
+ j 0xffffff6
+ jal 0x0000008
+ jal 0xaaaaaaa
+ jal 0x555555c
+ jal 0xffffffe
+ jals 0x0000002
+ jals 0xaaaaaa6
+ jals 0x555555a
+ jals 0xffffffe
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn --adjust-vma=0x55555550
+#name: MIPS jal mask 2.1
+#as: -32
+#source: jal-mask-2.s
+
+# Check address masks for JAL/J instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+55555550 <[^>]*> d400 0000 j 50000000 <[^>]*>
+55555554 <[^>]*> 0c00 nop
+55555556 <[^>]*> d555 5551 j 52aaaaa2 <[^>]*>
+5555555a <[^>]*> 0c00 nop
+5555555c <[^>]*> d6aa aaaa j 55555554 <[^>]*>
+55555560 <[^>]*> 0c00 nop
+55555562 <[^>]*> d7ff fffb j 57fffff6 <[^>]*>
+55555566 <[^>]*> 0c00 nop
+55555568 <[^>]*> f400 0004 jal 50000008 <[^>]*>
+5555556c <[^>]*> 0000 0000 nop
+55555570 <[^>]*> f555 5555 jal 52aaaaaa <[^>]*>
+55555574 <[^>]*> 0000 0000 nop
+55555578 <[^>]*> f6aa aaae jal 5555555c <[^>]*>
+5555557c <[^>]*> 0000 0000 nop
+55555580 <[^>]*> f7ff ffff jal 57fffffe <[^>]*>
+55555584 <[^>]*> 0000 0000 nop
+55555588 <[^>]*> 7400 0001 jals 50000002 <[^>]*>
+5555558c <[^>]*> 0c00 nop
+5555558e <[^>]*> 7555 5553 jals 52aaaaa6 <[^>]*>
+55555592 <[^>]*> 0c00 nop
+55555594 <[^>]*> 76aa aaad jals 5555555a <[^>]*>
+55555598 <[^>]*> 0c00 nop
+5555559a <[^>]*> 77ff ffff jals 57fffffe <[^>]*>
+5555559e <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn --adjust-vma=0xaaaaaaa0
+#name: MIPS jal mask 2.2
+#as: -32
+#source: jal-mask-2.s
+
+# Check address masks for JAL/J instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+aaaaaaa0 <[^>]*> d400 0000 j a8000000 <[^>]*>
+aaaaaaa4 <[^>]*> 0c00 nop
+aaaaaaa6 <[^>]*> d555 5551 j aaaaaaa2 <[^>]*>
+aaaaaaaa <[^>]*> 0c00 nop
+aaaaaaac <[^>]*> d6aa aaaa j ad555554 <[^>]*>
+aaaaaab0 <[^>]*> 0c00 nop
+aaaaaab2 <[^>]*> d7ff fffb j affffff6 <[^>]*>
+aaaaaab6 <[^>]*> 0c00 nop
+aaaaaab8 <[^>]*> f400 0004 jal a8000008 <[^>]*>
+aaaaaabc <[^>]*> 0000 0000 nop
+aaaaaac0 <[^>]*> f555 5555 jal aaaaaaaa <[^>]*>
+aaaaaac4 <[^>]*> 0000 0000 nop
+aaaaaac8 <[^>]*> f6aa aaae jal ad55555c <[^>]*>
+aaaaaacc <[^>]*> 0000 0000 nop
+aaaaaad0 <[^>]*> f7ff ffff jal affffffe <[^>]*>
+aaaaaad4 <[^>]*> 0000 0000 nop
+aaaaaad8 <[^>]*> 7400 0001 jals a8000002 <[^>]*>
+aaaaaadc <[^>]*> 0c00 nop
+aaaaaade <[^>]*> 7555 5553 jals aaaaaaa6 <[^>]*>
+aaaaaae2 <[^>]*> 0c00 nop
+aaaaaae4 <[^>]*> 76aa aaad jals ad55555a <[^>]*>
+aaaaaae8 <[^>]*> 0c00 nop
+aaaaaaea <[^>]*> 77ff ffff jals affffffe <[^>]*>
+aaaaaaee <[^>]*> 0c00 nop
+ \.\.\.
0+0028 <[^>]*> j 0+ <text_label>
[ ]*28: (MIPS_JMP|JMPADDR|R_MIPS_26) external_text_label
0+002c <[^>]*> nop
+ \.\.\.
# Test j as well
j text_label
j external_text_label
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
\.\.\.
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
\.\.\.
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|-16384)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,(1|4097)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,1\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,1\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,(1|8193)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,(1|-16383)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(23131|14939)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|-16384)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,(1|4097)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,(1|8193)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> ldc1 \$f4,(1|-16383)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(23131|14939)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> ldc1 \$f4,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
\.\.\.
.lcomm small_local_common,1
.text
+text_label:
lb $4,0
lb $4,1
lb $4,0x8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,-23131\(a0\)
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[0-9a-f]+ <[^>]*> addu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[0-9a-f]+ <[^>]*> addu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[0-9a-f]+ <[^>]*> addu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> addu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> addu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[0-9a-f]+ <[^>]*> addu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> addu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
\.\.\.
[0-9a-f]+ <[^>]*> daddu a0,a0,a1
[0-9a-f]+ <[^>]*> ld a0,-23131\(a0\)
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> ld a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu a0,a1,gp
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui a0,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu a0,a0,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> dsll32 a0,a0,0x0
[0-9a-f]+ <[^>]*> daddu a0,a0,at
[0-9a-f]+ <[^>]*> ld a0,0\(a0\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
\.\.\.
[0-9a-f]+ <[^>]*> lw a0,-23131\(at\)
[0-9a-f]+ <[^>]*> lw a1,-23127\(at\)
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a0,0\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,4\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a0,0\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lw a1,4\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a0,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,(4|8196)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a0,(0|-16384)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lw a1,(4|-16380)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a0,(1|4097)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,(5|4101)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> lw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a0,1\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,5\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> lw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a0,1\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lw a1,5\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a0,(1|8193)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,(5|8197)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a0,(1|-16383)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lw a1,(5|-16379)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a0,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|24572)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a0,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|24572)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a0,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,(4|8196)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a0,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(23127|19031)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> lw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> lw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> lw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> lw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a0,-(23131|14939)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,-(23127|14935)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a0,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(23127|19031)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,(4|8196)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> lw a0,(0|-16384)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lw a1,(4|-16380)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,(1|4097)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,(5|4101)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> lw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> lw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,(1|8193)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,(5|8197)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> lw a0,(1|-16383)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lw a1,(5|-16379)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|24572)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|24572)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,(4|8196)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(23127|19031)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-(23131|14939)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lw a1,-(23127|14935)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> lw a0,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lw a1,-(23127|19031)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
\.\.\.
.text
.align 12
+text_label:
ld r4,0
ld r4,1
ld r4,0x8000
0+0010 <[^>]*> lui a0,0x1
0+0014 <[^>]*> lui a0,0x1
0+0018 <[^>]*> ori a0,a0,0xa5a5
-0+001c <[^>]*> nop
+ \.\.\.
li $4,0x10000
li $4,0x1a5a5
-# Round to a 16 byte boundary, for ease in testing multiple targets.
- nop
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:micromips
+#name: microMIPS branch delay
+#as: -32 -march=mips64 -mmicromips
+#source: micromips-branch-delay.s
+#stderr: micromips-branch-delay.l
+
+# Test microMIPS branch delay slots.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 3040 ffff li v0,-1
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 3040 7fff li v0,32767
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 5040 ffff li v0,0xffff
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 41a2 0001 lui v0,0x1
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> ed7f li v0,-1
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 3040 7fff li v0,32767
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 5040 ffff li v0,0xffff
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 41a2 0001 lui v0,0x1
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 3040 ffff li v0,-1
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 3040 7fff li v0,32767
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 5040 ffff li v0,0xffff
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 41a2 0001 lui v0,0x1
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d ffff addiu v0,sp,-1
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0008 addiu v0,sp,8
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0100 addiu v0,sp,256
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 7fff addiu v0,sp,32767
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d ffff addiu v0,sp,-1
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 6d05 addiu v0,sp,8
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0100 addiu v0,sp,256
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 7fff addiu v0,sp,32767
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d ffff addiu v0,sp,-1
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0008 addiu v0,sp,8
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0100 addiu v0,sp,256
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 7fff addiu v0,sp,32767
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd ffff addiu sp,sp,-1
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 0008 addiu sp,sp,8
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 0100 addiu sp,sp,256
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 7fff addiu sp,sp,32767
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 4fbe addiu sp,sp,-1
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 4c05 addiu sp,sp,8
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 4c81 addiu sp,sp,256
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 7fff addiu sp,sp,32767
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd ffff addiu sp,sp,-1
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 0008 addiu sp,sp,8
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 0100 addiu sp,sp,256
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 7fff addiu sp,sp,32767
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d ffff addiu v0,sp,-1
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0008 addiu v0,sp,8
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0100 addiu v0,sp,256
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 7fff addiu v0,sp,32767
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 41a1 0001 lui at,0x1
+([0-9a-f]+) <[^>]*> 003d 1150 addu v0,sp,at
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d ffff addiu v0,sp,-1
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0008 addiu v0,sp,8
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0100 addiu v0,sp,256
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 7fff addiu v0,sp,32767
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 41a1 0001 lui at,0x1
+([0-9a-f]+) <[^>]*> 003d 1150 addu v0,sp,at
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d ffff addiu v0,sp,-1
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0008 addiu v0,sp,8
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 0100 addiu v0,sp,256
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 305d 7fff addiu v0,sp,32767
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 41a1 0001 lui at,0x1
+([0-9a-f]+) <[^>]*> 003d 1150 addu v0,sp,at
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd ffff addiu sp,sp,-1
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 0008 addiu sp,sp,8
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 0100 addiu sp,sp,256
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 7fff addiu sp,sp,32767
+([0-9a-f]+) <[^>]*> 4022 fffe bltzal v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 41a1 0001 lui at,0x1
+([0-9a-f]+) <[^>]*> 003d e950 addu sp,sp,at
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd ffff addiu sp,sp,-1
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 0008 addiu sp,sp,8
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 0100 addiu sp,sp,256
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 7fff addiu sp,sp,32767
+([0-9a-f]+) <[^>]*> 4222 fffe bltzals v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 41a1 0001 lui at,0x1
+([0-9a-f]+) <[^>]*> 003d e950 addu sp,sp,at
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd ffff addiu sp,sp,-1
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 0008 addiu sp,sp,8
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 0100 addiu sp,sp,256
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 33bd 7fff addiu sp,sp,32767
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+([0-9a-f]+) <[^>]*> 41a1 0001 lui at,0x1
+([0-9a-f]+) <[^>]*> 003d e950 addu sp,sp,at
+([0-9a-f]+) <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:17: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:19: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:21: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:40: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:44: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:46: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:71: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:90: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
+.*:92: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:94: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:96: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:98: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:100: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:100: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
+.*:110: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
+.*:121: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
+.*:123: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:125: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:127: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:129: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:131: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:131: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
+.*:141: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
--- /dev/null
+# Source file used to test microMIPS branch delay slots.
+
+ .text
+foo:
+ .set noreorder
+ bltzal $2, .
+ li $2, -1
+ bltzal $2, .
+ li $2, 0x7fff
+ bltzal $2, .
+ li $2, 0xffff
+ bltzal $2, .
+ li $2, 0x10000
+ bltzals $2, .
+ li $2, -1
+ bltzals $2, .
+ li $2, 0x7fff
+ bltzals $2, .
+ li $2, 0xffff
+ bltzals $2, .
+ li $2, 0x10000
+ bltzall $2, .
+ li $2, -1
+ bltzall $2, .
+ li $2, 0x7fff
+ bltzall $2, .
+ li $2, 0xffff
+ bltzall $2, .
+ li $2, 0x10000
+
+ bltzal $2, .
+ addiu $2, $29, -1
+ bltzal $2, .
+ addiu $2, $29, 8
+ bltzal $2, .
+ addiu $2, $29, 256
+ bltzal $2, .
+ addiu $2, $29, 0x7fff
+ bltzals $2, .
+ addiu $2, $29, -1
+ bltzals $2, .
+ addiu $2, $29, 8
+ bltzals $2, .
+ addiu $2, $29, 256
+ bltzals $2, .
+ addiu $2, $29, 0x7fff
+ bltzall $2, .
+ addiu $2, $29, -1
+ bltzall $2, .
+ addiu $2, $29, 8
+ bltzall $2, .
+ addiu $2, $29, 256
+ bltzall $2, .
+ addiu $2, $29, 0x7fff
+
+ bltzal $2, .
+ addiu $29, $29, -1
+ bltzal $2, .
+ addiu $29, $29, 8
+ bltzal $2, .
+ addiu $29, $29, 256
+ bltzal $2, .
+ addiu $29, $29, 0x7fff
+ bltzals $2, .
+ addiu $29, $29, -1
+ bltzals $2, .
+ addiu $29, $29, 8
+ bltzals $2, .
+ addiu $29, $29, 256
+ bltzals $2, .
+ addiu $29, $29, 0x7fff
+ bltzall $2, .
+ addiu $29, $29, -1
+ bltzall $2, .
+ addiu $29, $29, 8
+ bltzall $2, .
+ addiu $29, $29, 256
+ bltzall $2, .
+ addiu $29, $29, 0x7fff
+
+ bltzal $2, .
+ addu $2, $29, -1
+ bltzal $2, .
+ addu $2, $29, 8
+ bltzal $2, .
+ addu $2, $29, 256
+ bltzal $2, .
+ addu $2, $29, 0x7fff
+ bltzal $2, .
+ addu $2, $29, 0x10000
+ bltzals $2, .
+ addu $2, $29, -1
+ bltzals $2, .
+ addu $2, $29, 8
+ bltzals $2, .
+ addu $2, $29, 256
+ bltzals $2, .
+ addu $2, $29, 0x7fff
+ bltzals $2, .
+ addu $2, $29, 0x10000
+ bltzall $2, .
+ addu $2, $29, -1
+ bltzall $2, .
+ addu $2, $29, 8
+ bltzall $2, .
+ addu $2, $29, 256
+ bltzall $2, .
+ addu $2, $29, 0x7fff
+ bltzall $2, .
+ addu $2, $29, 0x10000
+
+ bltzal $2, .
+ addu $29, $29, -1
+ bltzal $2, .
+ addu $29, $29, 8
+ bltzal $2, .
+ addu $29, $29, 256
+ bltzal $2, .
+ addu $29, $29, 0x7fff
+ bltzal $2, .
+ addu $29, $29, 0x10000
+ bltzals $2, .
+ addu $29, $29, -1
+ bltzals $2, .
+ addu $29, $29, 8
+ bltzals $2, .
+ addu $29, $29, 256
+ bltzals $2, .
+ addu $29, $29, 0x7fff
+ bltzals $2, .
+ addu $29, $29, 0x10000
+ bltzall $2, .
+ addu $29, $29, -1
+ bltzall $2, .
+ addu $29, $29, 8
+ bltzall $2, .
+ addu $29, $29, 256
+ bltzall $2, .
+ addu $29, $29, 0x7fff
+ bltzall $2, .
+ addu $29, $29, 0x10000
+ .set reorder
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr --show-raw-insn
+#name: Relax microMIPS branches (pic)
+#as: -mips32r2 -32 -relax-branch -KPIC
+#stderr: micromips-branch-relax-pic.l
+#source: micromips-branch-relax.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <test>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: cfff b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40e0 fffe bc [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 4260 fffe bals [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: cfff b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40e0 fffe bc [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 4260 fffe bals [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: cfff b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40e0 fffe bc [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 4260 fffe bals [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: ff3c 0001 lw t9,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3339 045d addiu t9,t9,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 03f9 0f3c jalr t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR test3
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45a1 jrc at
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45c1 jalr at
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45e1 jalrs at
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b483 fffe bne v1,a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9483 fffe beq v1,a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4003 fffe bltz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40d4 fffe bgtz s4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4094 fffe blez s4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40a3 fffe bnezc v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45a1 jrc at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40e3 fffe beqzc v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45a1 jrc at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 401e fffe bltz s8,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45c1 jalr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 405e fffe bgez s8,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45c1 jalr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 401e fffe bltz s8,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45e1 jalrs at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 405e fffe bgez s8,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45e1 jalrs at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 43a0 fffe bc1t [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 42a0 fffe bc2t [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4280 fffe bc2f [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b483 fffe bne v1,a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0083 0b50 slt at,v1,a0
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0083 0b50 slt at,v1,a0
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0083 0b90 sltu at,v1,a0
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0083 0b90 sltu at,v1,a0
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4003 fffe bltz v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45c1 jalr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4003 fffe bltz v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0064 0b50 slt at,a0,v1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0064 0b50 slt at,a0,v1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0064 0b90 sltu at,a0,v1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0064 0b90 sltu at,a0,v1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4083 fffe blez v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0064 0b50 slt at,a0,v1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0064 0b50 slt at,a0,v1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0064 0b90 sltu at,a0,v1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0064 0b90 sltu at,a0,v1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40c3 fffe bgtz v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0083 0b50 slt at,v1,a0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0083 0b50 slt at,v1,a0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0083 0b90 sltu at,v1,a0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0083 0b90 sltu at,v1,a0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 45c1 jalr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9483 fffe beq v1,a0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: fc3c 0001 lw at,1\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[ 0-9a-f]+: 3021 045d addiu at,at,1117
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[ 0-9a-f]+: 4581 jr at
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+ \.\.\.
+
+[0-9a-f]+ <test2>:
+ \.\.\.
+
+[0-9a-f]+ <test3>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:61: Warning: No .cprestore pseudo-op used in PIC code
+.*:59: Warning: Relaxed out-of-range branch into a jump
+.*:63: Warning: Relaxed out-of-range branch into a jump
+.*:65: Warning: Relaxed out-of-range branch into a jump
+.*:67: Warning: Relaxed out-of-range branch into a jump
+.*:69: Warning: Relaxed out-of-range branch into a jump
+.*:71: Warning: Relaxed out-of-range branch into a jump
+.*:73: Warning: Relaxed out-of-range branch into a jump
+.*:75: Warning: Relaxed out-of-range branch into a jump
+.*:77: Warning: Relaxed out-of-range branch into a jump
+.*:79: Warning: Relaxed out-of-range branch into a jump
+.*:81: Warning: Relaxed out-of-range branch into a jump
+.*:83: Warning: Relaxed out-of-range branch into a jump
+.*:85: Warning: Relaxed out-of-range branch into a jump
+.*:87: Warning: Relaxed out-of-range branch into a jump
+.*:89: Warning: Relaxed out-of-range branch into a jump
+.*:91: Warning: Relaxed out-of-range branch into a jump
+.*:93: Warning: Relaxed out-of-range branch into a jump
+.*:95: Warning: Relaxed out-of-range branch into a jump
+.*:97: Warning: Relaxed out-of-range branch into a jump
+.*:99: Warning: Relaxed out-of-range branch into a jump
+.*:101: Warning: Relaxed out-of-range branch into a jump
+.*:103: Warning: Relaxed out-of-range branch into a jump
+.*:105: Warning: Relaxed out-of-range branch into a jump
+.*:107: Warning: Relaxed out-of-range branch into a jump
+.*:109: Warning: Relaxed out-of-range branch into a jump
+.*:111: Warning: Relaxed out-of-range branch into a jump
+.*:113: Warning: Relaxed out-of-range branch into a jump
+.*:115: Warning: Relaxed out-of-range branch into a jump
+.*:117: Warning: Relaxed out-of-range branch into a jump
+.*:119: Warning: Relaxed out-of-range branch into a jump
+.*:121: Warning: Relaxed out-of-range branch into a jump
+.*:123: Warning: Relaxed out-of-range branch into a jump
+.*:125: Warning: Relaxed out-of-range branch into a jump
+.*:127: Warning: Relaxed out-of-range branch into a jump
+.*:129: Warning: Relaxed out-of-range branch into a jump
+.*:131: Warning: Relaxed out-of-range branch into a jump
+.*:133: Warning: Relaxed out-of-range branch into a jump
+.*:135: Warning: Relaxed out-of-range branch into a jump
+.*:137: Warning: Relaxed out-of-range branch into a jump
+.*:139: Warning: Relaxed out-of-range branch into a jump
+.*:141: Warning: Relaxed out-of-range branch into a jump
+.*:143: Warning: Relaxed out-of-range branch into a jump
+.*:145: Warning: Relaxed out-of-range branch into a jump
+.*:147: Warning: Relaxed out-of-range branch into a jump
+.*:149: Warning: Relaxed out-of-range branch into a jump
+.*:151: Warning: Relaxed out-of-range branch into a jump
+.*:153: Warning: Relaxed out-of-range branch into a jump
+.*:155: Warning: Relaxed out-of-range branch into a jump
--- /dev/null
+#objdump: -dr --show-raw-insn
+#name: Relax microMIPS branches
+#as: -mips32r2 -32 -relax-branch
+#stderr: micromips-branch-relax.l
+#source: micromips-branch-relax.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <test>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: cfff b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40e0 fffe bc [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 4260 fffe bals [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: cfff b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40e0 fffe bc [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 4260 fffe bals [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: cfff b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40e0 fffe bc [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 4260 fffe bals [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: f400 0000 jal 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: f400 0000 jal 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 7400 0000 jals 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b483 fffe bne v1,a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9483 fffe beq v1,a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4003 fffe bltz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40d4 fffe bgtz s4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4094 fffe blez s4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40a3 fffe bnezc v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 0c00 nop
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40e3 fffe beqzc v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 0c00 nop
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 401e fffe bltz s8,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: f400 0000 jal 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 405e fffe bgez s8,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: f400 0000 jal 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 401e fffe bltz s8,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 7400 0000 jals 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 405e fffe bgez s8,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 7400 0000 jals 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 43a0 fffe bc1t [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 42a0 fffe bc2t [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4280 fffe bc2f [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b483 fffe bne v1,a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0083 0b50 slt at,v1,a0
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0083 0b50 slt at,v1,a0
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0083 0b90 sltu at,v1,a0
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0083 0b90 sltu at,v1,a0
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4003 fffe bltz v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: f400 0000 jal 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4003 fffe bltz v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0064 0b50 slt at,a0,v1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0064 0b50 slt at,a0,v1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0064 0b90 sltu at,a0,v1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0064 0b90 sltu at,a0,v1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4083 fffe blez v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0064 0b50 slt at,a0,v1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0064 0b50 slt at,a0,v1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0064 0b90 sltu at,a0,v1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0064 0b90 sltu at,a0,v1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40c3 fffe bgtz v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0083 0b50 slt at,v1,a0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0083 0b50 slt at,v1,a0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0083 0b90 sltu at,v1,a0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 0083 0b90 sltu at,v1,a0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: f400 0000 jal 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9483 fffe beq v1,a0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+[ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: d400 0000 j 0 <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test3
+[ 0-9a-f]+: 00a4 1b10 xor v1,a0,a1
+
+[0-9a-f]+ <.*>:
+ \.\.\.
+
+[0-9a-f]+ <test2>:
+ \.\.\.
+
+[0-9a-f]+ <test3>:
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:63: Warning: Relaxed out-of-range branch into a jump
+.*:65: Warning: Relaxed out-of-range branch into a jump
+.*:67: Warning: Relaxed out-of-range branch into a jump
+.*:69: Warning: Relaxed out-of-range branch into a jump
+.*:71: Warning: Relaxed out-of-range branch into a jump
+.*:73: Warning: Relaxed out-of-range branch into a jump
+.*:75: Warning: Relaxed out-of-range branch into a jump
+.*:77: Warning: Relaxed out-of-range branch into a jump
+.*:79: Warning: Relaxed out-of-range branch into a jump
+.*:81: Warning: Relaxed out-of-range branch into a jump
+.*:83: Warning: Relaxed out-of-range branch into a jump
+.*:85: Warning: Relaxed out-of-range branch into a jump
+.*:87: Warning: Relaxed out-of-range branch into a jump
+.*:89: Warning: Relaxed out-of-range branch into a jump
+.*:91: Warning: Relaxed out-of-range branch into a jump
+.*:93: Warning: Relaxed out-of-range branch into a jump
+.*:95: Warning: Relaxed out-of-range branch into a jump
+.*:97: Warning: Relaxed out-of-range branch into a jump
+.*:99: Warning: Relaxed out-of-range branch into a jump
+.*:101: Warning: Relaxed out-of-range branch into a jump
+.*:103: Warning: Relaxed out-of-range branch into a jump
+.*:105: Warning: Relaxed out-of-range branch into a jump
+.*:107: Warning: Relaxed out-of-range branch into a jump
+.*:109: Warning: Relaxed out-of-range branch into a jump
+.*:111: Warning: Relaxed out-of-range branch into a jump
+.*:113: Warning: Relaxed out-of-range branch into a jump
+.*:115: Warning: Relaxed out-of-range branch into a jump
+.*:117: Warning: Relaxed out-of-range branch into a jump
+.*:119: Warning: Relaxed out-of-range branch into a jump
+.*:121: Warning: Relaxed out-of-range branch into a jump
+.*:123: Warning: Relaxed out-of-range branch into a jump
+.*:125: Warning: Relaxed out-of-range branch into a jump
+.*:127: Warning: Relaxed out-of-range branch into a jump
+.*:129: Warning: Relaxed out-of-range branch into a jump
+.*:131: Warning: Relaxed out-of-range branch into a jump
+.*:133: Warning: Relaxed out-of-range branch into a jump
+.*:135: Warning: Relaxed out-of-range branch into a jump
+.*:137: Warning: Relaxed out-of-range branch into a jump
+.*:139: Warning: Relaxed out-of-range branch into a jump
+.*:141: Warning: Relaxed out-of-range branch into a jump
+.*:143: Warning: Relaxed out-of-range branch into a jump
+.*:145: Warning: Relaxed out-of-range branch into a jump
+.*:147: Warning: Relaxed out-of-range branch into a jump
+.*:149: Warning: Relaxed out-of-range branch into a jump
+.*:151: Warning: Relaxed out-of-range branch into a jump
+.*:153: Warning: Relaxed out-of-range branch into a jump
+.*:155: Warning: Relaxed out-of-range branch into a jump
--- /dev/null
+ .text
+ .set micromips
+ .set noreorder
+test:
+ b32 test
+ addu $3, $4, $5
+ beqz32 $3, test
+ addu $3, $4, $5
+ bnez32 $3, test
+ addu $3, $4, $5
+ b test
+ addu $3, $4, $5
+ bc test
+ addu $3, $4, $5
+ bal test
+ addu $3, $4, $5
+ bals test
+ addu $3, $4, $5
+ beqz $3, test
+ addu $3, $4, $5
+ bnez $3, test
+ addu $3, $4, $5
+ b16 test2
+ addu $3, $4, $5
+ beqz16 $3, test2
+ addu $3, $4, $5
+ bnez16 $3, test2
+ addu $3, $4, $5
+ b test2
+ addu $3, $4, $5
+ bc test2
+ addu $3, $4, $5
+ bal test2
+ addu $3, $4, $5
+ bals test2
+ addu $3, $4, $5
+ beqz $3, test2
+ addu $3, $4, $5
+ bnez $3, test2
+ addu $3, $4, $5
+ b16 test3
+ addu $3, $4, $5
+ beqz16 $3, test3
+ addu $3, $4, $5
+ bnez16 $3, test3
+ addu $3, $4, $5
+ b32 test2
+ addu $3, $4, $5
+ bc32 test2
+ addu $3, $4, $5
+ bal32 test2
+ addu $3, $4, $5
+ bals32 test2
+ addu $3, $4, $5
+ beqz32 $3, test2
+ addu $3, $4, $5
+ bnez32 $3, test2
+ addu $3, $4, $5
+ j test3
+ addu $3, $4, $5
+ jal test3
+ addu $3, $4, $5
+ b test3
+ addu $3, $4, $5
+ bc test3
+ addu $3, $4, $5
+ bal test3
+ addu $3, $4, $5
+ bals test3
+ addu $3, $4, $5
+ beq $3, $4, test3
+ addu $3, $4, $5
+ bne $3, $4, test3
+ addu $3, $4, $5
+ bltz $3, test3
+ addu $3, $4, $5
+ bgez $3, test3
+ addu $3, $4, $5
+ blez $20, test3
+ addu $3, $4, $5
+ bgtz $20, test3
+ addu $3, $4, $5
+ beqzc $3, test3
+ addu $3, $4, $5
+ bnezc $3, test3
+ addu $3, $4, $5
+ bgezal $30, test3
+ addu $3, $4, $5
+ bltzal $30, test3
+ addu $3, $4, $5
+ bgezals $30, test3
+ addu $3, $4, $5
+ bltzals $30, test3
+ addu $3, $4, $5
+ bc1f test3
+ addu $3, $4, $5
+ bc1t test3
+ addu $3, $4, $5
+ bc2f test3
+ addu $3, $4, $5
+ bc2t test3
+ addu $3, $4, $5
+ beql $3, $4, test3
+ addu $3, $4, $5
+ beqz $3, test3
+ xor $3, $4, $5
+ bge $3, $4, test3
+ xor $3, $4, $5
+ bgel $3, $4, test3
+ xor $3, $4, $5
+ bgeu $3, $4, test3
+ xor $3, $4, $5
+ bgeul $3, $4, test3
+ xor $3, $4, $5
+ bgezall $3, test3
+ xor $3, $4, $5
+ bgezl $3, test3
+ xor $3, $4, $5
+ bgt $3, $4, test3
+ xor $3, $4, $5
+ bgtl $3, $4, test3
+ xor $3, $4, $5
+ bgtu $3, $4, test3
+ xor $3, $4, $5
+ bgtul $3, $4, test3
+ xor $3, $4, $5
+ bgtzl $3, test3
+ xor $3, $4, $5
+ ble $3, $4, test3
+ xor $3, $4, $5
+ blel $3, $4, test3
+ xor $3, $4, $5
+ bleu $3, $4, test3
+ xor $3, $4, $5
+ bleul $3, $4, test3
+ xor $3, $4, $5
+ blezl $3, test3
+ xor $3, $4, $5
+ blt $3, $4, test3
+ xor $3, $4, $5
+ bltl $3, $4, test3
+ xor $3, $4, $5
+ bltu $3, $4, test3
+ xor $3, $4, $5
+ bltul $3, $4, test3
+ xor $3, $4, $5
+ bltzall $3, test3
+ xor $3, $4, $5
+ bltzl $3, test3
+ xor $3, $4, $5
+ bnel $3, $4, test3
+ xor $3, $4, $5
+ bnez $3, test3
+ xor $3, $4, $5
+ bnezl $3, test3
+ xor $3, $4, $5
+
+ .skip 511 << 1
+test2:
+
+ .skip (32767 - 511) << 1
+test3:
+ addu $3, $4, $5
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+.*: Assembler messages:
+.*:15: Error: Illegal operands `addu16 \$12,\$14'
+.*:18: Error: Unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
+.*:22: Error: Unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
+.*:25: Error: Unrecognized opcode `jar \$23'
+.*:26: Error: Unrecognized opcode `jar16 \$23'
+.*:27: Error: Unrecognized opcode `jar32 \$23'
+.*:41: Error: Illegal operands `jalr16 \$30,\$26'
+.*:50: Error: Illegal operands `beqz16 \$27,bar'
+.*:58: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:66: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:70: Error: Unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
+.*:74: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:76: Error: Unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
+.*:77: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:78: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:80: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:82: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:84: Error: Unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
+.*:90: Error: Unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
+.*:95: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
+.*:95: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
+.*:98: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:104: Error: Unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
+.*:105: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
+.*:108: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:110: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:112: Error: Unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
+.*:120: Error: Illegal operands `sll16 \$2,\$3,13'
+.*:123: Error: Illegal operands `sll16 \$10,\$11,5'
+.*:128: Error: Unrecognized 16-bit version of microMIPS opcode `dsll16 \$2,\$3,5'
+.*:130: Error: Unrecognized 16-bit version of microMIPS opcode `dsll3216 \$2,\$3,5'
+.*:133: Error: Unrecognized 16-bit version of microMIPS opcode `dsll16 \$2,\$3,13'
+.*:135: Error: Unrecognized 16-bit version of microMIPS opcode `dsll3216 \$2,\$3,13'
+.*:138: Error: Unrecognized 16-bit version of microMIPS opcode `dsll16 \$10,\$11,5'
+.*:140: Error: Unrecognized 16-bit version of microMIPS opcode `dsll3216 \$10,\$11,5'
--- /dev/null
+# Source file used to test the microMIPS instruction size overrides (#0).
+
+ .text
+foo:
+# Smoke-test a trivial case.
+ nop
+ nop16
+ nop32
+
+# Test ALU operations.
+ addu $2, $4
+ addu16 $2, $4
+ addu32 $2, $4
+ addu $12, $14
+ addu16 $12, $14
+ addu32 $12, $14
+ add.ps $f2, $f4
+ add16.ps $f2, $f4
+ add32.ps $f2, $f4
+ addiusp 256
+ addiusp16 256
+ addiusp32 256
+
+# Test jumps and branches.
+ jar $23
+ jar16 $23
+ jar32 $23
+ jalr $4
+ jalr16 $4
+ jalr32 $4
+ jalr $24
+ jalr16 $24
+ jalr32 $24
+ jalr $31,$5
+ jalr16 $31,$5
+ jalr32 $31,$5
+ jalr $31,$25
+ jalr16 $31,$25
+ jalr32 $31,$25
+ jalr $30,$26
+ jalr16 $30,$26
+ jalr32 $30,$26
+ b bar
+ b16 bar
+ b32 bar
+ beqz $7, bar
+ beqz16 $7, bar
+ beqz32 $7, bar
+ beqz $27, bar
+ beqz16 $27, bar
+ beqz32 $27, bar
+
+# Test branch delay slots.
+ .set noreorder
+ bltzal $2, bar
+ addu $16, $17
+ bltzal $2, bar
+ addu16 $16, $17
+ bltzal $2, bar
+ addu32 $16, $17
+ bltzals $2, bar
+ addu $16, $17
+ bltzals $2, bar
+ addu16 $16, $17
+ bltzals $2, bar
+ addu32 $16, $17
+ bltzal $2, bar
+ add.ps $f2, $f4
+ bltzal $2, bar
+ add16.ps $f2, $f4
+ bltzal $2, bar
+ add32.ps $f2, $f4
+ bltzals $2, bar
+ add.ps $f2, $f4
+ bltzals $2, bar
+ add16.ps $f2, $f4
+ bltzals $2, bar
+ add32.ps $f2, $f4
+ bltzal $2, bar
+ addiusp 256
+ bltzal $2, bar
+ addiusp16 256
+ bltzal $2, bar
+ addiusp32 256
+ bltzals $2, bar
+ addiusp 256
+ bltzals $2, bar
+ addiusp16 256
+ bltzals $2, bar
+ addiusp32 256
+ .set reorder
+
+# Test macro delay slots.
+ .set noreorder
+ bltzall $2, bar
+ addu $16, $17
+ bltzall $2, bar
+ addu16 $16, $17
+ bltzall $2, bar
+ addu32 $16, $17
+ bltzall $2, bar
+ add.ps $f2, $f4
+ bltzall $2, bar
+ add16.ps $f2, $f4
+ bltzall $2, bar
+ add32.ps $f2, $f4
+ bltzall $2, bar
+ addiusp 256
+ bltzall $2, bar
+ addiusp16 256
+ bltzall $2, bar
+ addiusp32 256
+ .set reorder
+
+# Test shift instructions to complement 64-bit tests.
+ sll $2, $3, 5
+ sll16 $2, $3, 5
+ sll32 $2, $3, 5
+ sll $2, $3, 13
+ sll16 $2, $3, 13
+ sll32 $2, $3, 13
+ sll $10, $11, 5
+ sll16 $10, $11, 5
+ sll32 $10, $11, 5
+
+# Test 64-bit instructions.
+ dsll $2, $3, 5
+ dsll16 $2, $3, 5
+ dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
+ dsll3216 $2, $3, 5
+ dsll3232 $2, $3, 5
+ dsll $2, $3, 13
+ dsll16 $2, $3, 13
+ dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
+ dsll3216 $2, $3, 13
+ dsll3232 $2, $3, 13
+ dsll $10, $11, 5
+ dsll16 $10, $11, 5
+ dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
+ dsll3216 $10, $11, 5
+ dsll3232 $10, $11, 5
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:micromips
+#name: microMIPS instruction size 1
+#as: -32 -march=mips64 -mmicromips
+#source: micromips-size-1.s
+#stderr: micromips-size-1.l
+
+# Test microMIPS instruction size overrides (#1).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 0544 addu v0,v0,a0
+[0-9a-f]+ <[^>]*> 0544 addu v0,v0,a0
+[0-9a-f]+ <[^>]*> 0082 1150 addu v0,v0,a0
+[0-9a-f]+ <[^>]*> 01cc 6150 addu t4,t4,t6
+[0-9a-f]+ <[^>]*> 01cc 6150 addu t4,t4,t6
+[0-9a-f]+ <[^>]*> 5482 1230 add\.ps \$f2,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 5482 1230 add\.ps \$f2,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4c81 addiu sp,sp,256
+[0-9a-f]+ <[^>]*> 4c81 addiu sp,sp,256
+[0-9a-f]+ <[^>]*> 45c4 jalr a0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 45c4 jalr a0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 03e4 0f3c jalr a0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 45d8 jalr t8
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 45d8 jalr t8
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 03f8 0f3c jalr t8
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 45c5 jalr a1
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 45c5 jalr a1
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 03e5 0f3c jalr a1
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 45d9 jalr t9
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 45d9 jalr t9
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 03f9 0f3c jalr t9
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 03da 0f3c jalr s8,k0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 03da 0f3c jalr s8,k0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+0084 <.*\+0x84>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> cfff b 0+008a <.*\+0x8a>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+008e <.*\+0x8e>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9407 fffe beqz a3,0+0094 <.*\+0x94>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8fff beqz a3,0+009a <.*\+0x9a>
+ 9a: R_MICROMIPS_PC7_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9407 fffe beqz a3,0+009e <.*\+0x9e>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 941b fffe beqz k1,0+00a4 <.*\+0xa4>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 941b fffe beqz k1,0+00aa <.*\+0xaa>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4022 fffe bltzal v0,0+00b0 <.*\+0xb0>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0230 8150 addu s0,s0,s1
+[0-9a-f]+ <[^>]*> 4022 fffe bltzal v0,0+00b8 <.*\+0xb8>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0410 addu s0,s0,s1
+[0-9a-f]+ <[^>]*> 4022 fffe bltzal v0,0+00be <.*\+0xbe>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0230 8150 addu s0,s0,s1
+[0-9a-f]+ <[^>]*> 4222 fffe bltzals v0,0+00c6 <.*\+0xc6>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0410 addu s0,s0,s1
+[0-9a-f]+ <[^>]*> 4222 fffe bltzals v0,0+00cc <.*\+0xcc>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0410 addu s0,s0,s1
+[0-9a-f]+ <[^>]*> 4222 fffe bltzals v0,0+00d2 <.*\+0xd2>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0230 8150 addu s0,s0,s1
+[0-9a-f]+ <[^>]*> 4022 fffe bltzal v0,0+00da <.*\+0xda>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 5482 1230 add\.ps \$f2,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4022 fffe bltzal v0,0+00e2 <.*\+0xe2>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 5482 1230 add\.ps \$f2,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4222 fffe bltzals v0,0+00ea <.*\+0xea>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 5482 1230 add\.ps \$f2,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4222 fffe bltzals v0,0+00f2 <.*\+0xf2>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 5482 1230 add\.ps \$f2,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4022 fffe bltzal v0,0+00fa <.*\+0xfa>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 4c81 addiu sp,sp,256
+[0-9a-f]+ <[^>]*> 4022 fffe bltzal v0,0+0100 <.*\+0x100>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 4c81 addiu sp,sp,256
+[0-9a-f]+ <[^>]*> 4222 fffe bltzals v0,0+0106 <.*\+0x106>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 4c81 addiu sp,sp,256
+[0-9a-f]+ <[^>]*> 4222 fffe bltzals v0,0+010c <.*\+0x10c>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 4c81 addiu sp,sp,256
+[0-9a-f]+ <[^>]*> 4042 fffe bgez v0,0+0112 <.*\+0x112>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0118 <.*\+0x118>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0230 8150 addu s0,s0,s1
+[0-9a-f]+ <[^>]*> 4042 fffe bgez v0,0+0120 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0126 <.*\+0x6>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0410 addu s0,s0,s1
+[0-9a-f]+ <[^>]*> 4042 fffe bgez v0,0+012c <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0132 <.*\+0x6>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0230 8150 addu s0,s0,s1
+[0-9a-f]+ <[^>]*> 4042 fffe bgez v0,0+013a <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0140 <.*\+0x6>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 5482 1230 add\.ps \$f2,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4042 fffe bgez v0,0+0148 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+014e <.*\+0x6>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 5482 1230 add\.ps \$f2,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4042 fffe bgez v0,0+0156 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+015c <.*\+0x6>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 4c81 addiu sp,sp,256
+[0-9a-f]+ <[^>]*> 4042 fffe bgez v0,0+0162 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0168 <.*\+0x6>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 4c81 addiu sp,sp,256
+[0-9a-f]+ <[^>]*> 253a sll v0,v1,5
+[0-9a-f]+ <[^>]*> 253a sll v0,v1,5
+[0-9a-f]+ <[^>]*> 0043 2800 sll v0,v1,0x5
+[0-9a-f]+ <[^>]*> 0043 6800 sll v0,v1,0xd
+[0-9a-f]+ <[^>]*> 0043 6800 sll v0,v1,0xd
+[0-9a-f]+ <[^>]*> 014b 2800 sll t2,t3,0x5
+[0-9a-f]+ <[^>]*> 014b 2800 sll t2,t3,0x5
+[0-9a-f]+ <[^>]*> 5843 2800 dsll v0,v1,0x5
+[0-9a-f]+ <[^>]*> 5843 2808 dsll32 v0,v1,0x5
+[0-9a-f]+ <[^>]*> 5843 2808 dsll32 v0,v1,0x5
+[0-9a-f]+ <[^>]*> 5843 6800 dsll v0,v1,0xd
+[0-9a-f]+ <[^>]*> 5843 6808 dsll32 v0,v1,0xd
+[0-9a-f]+ <[^>]*> 5843 6808 dsll32 v0,v1,0xd
+[0-9a-f]+ <[^>]*> 594b 2800 dsll t2,t3,0x5
+[0-9a-f]+ <[^>]*> 594b 2808 dsll32 t2,t3,0x5
+[0-9a-f]+ <[^>]*> 594b 2808 dsll32 t2,t3,0x5
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:50: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:58: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:64: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:66: Warning: Wrong size instruction in a 16-bit branch delay slot
+.*:68: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:70: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:82: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:90: Warning: Wrong size instruction in a 32-bit branch delay slot
+.*:92: Warning: Wrong size instruction in a 32-bit branch delay slot
--- /dev/null
+# Source file used to test microMIPS instruction size overrides (#1).
+
+ .text
+foo:
+# Smoke-test a trivial case.
+ nop
+ nop16
+ nop32
+
+# Test ALU operations.
+ addu $2, $4
+ addu16 $2, $4
+ addu32 $2, $4
+ addu $12, $14
+ addu32 $12, $14
+ add.ps $f2, $f4
+ add32.ps $f2, $f4
+ addiusp 256
+ addiusp16 256
+
+# Test jumps and branches.
+ jalr $4
+ jalr16 $4
+ jalr32 $4
+ jalr $24
+ jalr16 $24
+ jalr32 $24
+ jalr $31,$5
+ jalr16 $31,$5
+ jalr32 $31,$5
+ jalr $31,$25
+ jalr16 $31,$25
+ jalr32 $31,$25
+ jalr $30,$26
+ jalr32 $30,$26
+ b bar
+ b16 bar
+ b32 bar
+ beqz $7, bar
+ beqz16 $7, bar
+ beqz32 $7, bar
+ beqz $27, bar
+ beqz32 $27, bar
+
+# Test branch delay slots.
+ .set noreorder
+ bltzal $2, bar
+ addu $16, $17
+ bltzal $2, bar
+ addu16 $16, $17
+ bltzal $2, bar
+ addu32 $16, $17
+ bltzals $2, bar
+ addu $16, $17
+ bltzals $2, bar
+ addu16 $16, $17
+ bltzals $2, bar
+ addu32 $16, $17
+ bltzal $2, bar
+ add.ps $f2, $f4
+ bltzal $2, bar
+ add32.ps $f2, $f4
+ bltzals $2, bar
+ add.ps $f2, $f4
+ bltzals $2, bar
+ add32.ps $f2, $f4
+ bltzal $2, bar
+ addiusp 256
+ bltzal $2, bar
+ addiusp16 256
+ bltzals $2, bar
+ addiusp 256
+ bltzals $2, bar
+ addiusp16 256
+ .set reorder
+
+# Test macro delay slots.
+ .set noreorder
+ bltzall $2, bar
+ addu $16, $17
+ bltzall $2, bar
+ addu16 $16, $17
+ bltzall $2, bar
+ addu32 $16, $17
+ bltzall $2, bar
+ add.ps $f2, $f4
+ bltzall $2, bar
+ add32.ps $f2, $f4
+ bltzall $2, bar
+ addiusp 256
+ bltzall $2, bar
+ addiusp16 256
+ .set reorder
+
+# Test shift instructions to complement 64-bit tests.
+ sll $2, $3, 5
+ sll16 $2, $3, 5
+ sll32 $2, $3, 5
+ sll $2, $3, 13
+ sll32 $2, $3, 13
+ sll $10, $11, 5
+ sll32 $10, $11, 5
+
+# Test 64-bit instructions.
+ dsll $2, $3, 5
+ dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
+ dsll3232 $2, $3, 5
+ dsll $2, $3, 13
+ dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
+ dsll3232 $2, $3, 13
+ dsll $10, $11, 5
+ dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
+ dsll3232 $10, $11, 5
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr --show-raw-insn
+#name: microMIPS for MIPS32r2 (w/traps)
+#as: -mips32r2 -32 -trap -mfp64 -EB
+#stderr: micromips.l
+#source: micromips.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <test>:
+[ 0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+[ 0-9a-f]+: 6000 27ff pref 0x0,2047\(zero\)
+[ 0-9a-f]+: 6000 2800 pref 0x0,-2048\(zero\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 6001 2800 pref 0x0,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 6001 27ff pref 0x0,2047\(at\)
+[ 0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+[ 0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+[ 0-9a-f]+: 6020 2000 pref 0x1,0\(zero\)
+[ 0-9a-f]+: 6040 2000 pref 0x2,0\(zero\)
+[ 0-9a-f]+: 6060 2000 pref 0x3,0\(zero\)
+[ 0-9a-f]+: 6080 2000 pref 0x4,0\(zero\)
+[ 0-9a-f]+: 60a0 2000 pref 0x5,0\(zero\)
+[ 0-9a-f]+: 60c0 2000 pref 0x6,0\(zero\)
+[ 0-9a-f]+: 60e0 2000 pref 0x7,0\(zero\)
+[ 0-9a-f]+: 60e0 21ff pref 0x7,511\(zero\)
+[ 0-9a-f]+: 60e0 2e00 pref 0x7,-512\(zero\)
+[ 0-9a-f]+: 63e0 27ff pref 0x1f,2047\(zero\)
+[ 0-9a-f]+: 63e0 2800 pref 0x1f,-2048\(zero\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 63e1 2800 pref 0x1f,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 63e1 27ff pref 0x1f,2047\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 2fff pref 0x3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+[ 0-9a-f]+: 63e2 27ff pref 0x1f,2047\(v0\)
+[ 0-9a-f]+: 63e2 2800 pref 0x1f,-2048\(v0\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 63e1 2800 pref 0x1f,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 63e1 27ff pref 0x1f,2047\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 6061 2fff pref 0x3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0000 0800 ssnop
+[ 0-9a-f]+: 0000 1800 ehb
+[ 0-9a-f]+: 0000 2800 pause
+[ 0-9a-f]+: ed7f li v0,-1
+[ 0-9a-f]+: edff li v1,-1
+[ 0-9a-f]+: ee7f li a0,-1
+[ 0-9a-f]+: eeff li a1,-1
+[ 0-9a-f]+: ef7f li a2,-1
+[ 0-9a-f]+: efff li a3,-1
+[ 0-9a-f]+: ec7f li s0,-1
+[ 0-9a-f]+: ecff li s1,-1
+[ 0-9a-f]+: ec80 li s1,0
+[ 0-9a-f]+: ecfd li s1,125
+[ 0-9a-f]+: ecfe li s1,126
+[ 0-9a-f]+: 3220 007f li s1,127
+[ 0-9a-f]+: 3040 0000 li v0,0
+[ 0-9a-f]+: 3040 0001 li v0,1
+[ 0-9a-f]+: 3040 7fff li v0,32767
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 5040 ffff li v0,0xffff
+[ 0-9a-f]+: 41a2 0001 lui v0,0x1
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 3040 8001 li v0,-32767
+[ 0-9a-f]+: 3040 ffff li v0,-1
+[ 0-9a-f]+: 41a2 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5678 ori v0,v0,0x5678
+[ 0-9a-f]+: 0c16 move zero,s6
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0c76 move v1,s6
+[ 0-9a-f]+: 0c96 move a0,s6
+[ 0-9a-f]+: 0cb6 move a1,s6
+[ 0-9a-f]+: 0cd6 move a2,s6
+[ 0-9a-f]+: 0cf6 move a3,s6
+[ 0-9a-f]+: 0d16 move t0,s6
+[ 0-9a-f]+: 0d36 move t1,s6
+[ 0-9a-f]+: 0d56 move t2,s6
+[ 0-9a-f]+: 0fd6 move s8,s6
+[ 0-9a-f]+: 0ff6 move ra,s6
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0c02 move zero,v0
+[ 0-9a-f]+: 0c03 move zero,v1
+[ 0-9a-f]+: 0c04 move zero,a0
+[ 0-9a-f]+: 0c05 move zero,a1
+[ 0-9a-f]+: 0c06 move zero,a2
+[ 0-9a-f]+: 0c07 move zero,a3
+[ 0-9a-f]+: 0c08 move zero,t0
+[ 0-9a-f]+: 0c09 move zero,t1
+[ 0-9a-f]+: 0c0a move zero,t2
+[ 0-9a-f]+: 0c1e move zero,s8
+[ 0-9a-f]+: 0c1f move zero,ra
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 0016 1150 move v0,s6
+[ 0-9a-f]+: 0002 b150 move s6,v0
+[ 0-9a-f]+: cfff b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: cfff b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: cfff b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: cfff b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: cfff b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: cfff b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c43 move v0,v1
+[ 0-9a-f]+: 0060 1190 neg v0,v1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4044 fffe bgez a0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c44 move v0,a0
+[ 0-9a-f]+: 0080 1190 neg v0,a0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0083 1110 add v0,v1,a0
+[ 0-9a-f]+: 03fe e910 add sp,s8,ra
+[ 0-9a-f]+: 0082 1110 add v0,v0,a0
+[ 0-9a-f]+: 0082 1110 add v0,v0,a0
+[ 0-9a-f]+: 1042 0000 addi v0,v0,0
+[ 0-9a-f]+: 1042 0001 addi v0,v0,1
+[ 0-9a-f]+: 1042 7fff addi v0,v0,32767
+[ 0-9a-f]+: 1042 8000 addi v0,v0,-32768
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 1110 add v0,v0,at
+[ 0-9a-f]+: 1064 8000 addi v1,a0,-32768
+[ 0-9a-f]+: 1064 0000 addi v1,a0,0
+[ 0-9a-f]+: 1064 7fff addi v1,a0,32767
+[ 0-9a-f]+: 1064 ffff addi v1,a0,-1
+[ 0-9a-f]+: 1063 ffff addi v1,v1,-1
+[ 0-9a-f]+: 1063 ffff addi v1,v1,-1
+[ 0-9a-f]+: 4c10 addiu zero,zero,-8
+[ 0-9a-f]+: 4c50 addiu v0,v0,-8
+[ 0-9a-f]+: 4c70 addiu v1,v1,-8
+[ 0-9a-f]+: 4c90 addiu a0,a0,-8
+[ 0-9a-f]+: 4cb0 addiu a1,a1,-8
+[ 0-9a-f]+: 4cd0 addiu a2,a2,-8
+[ 0-9a-f]+: 4cf0 addiu a3,a3,-8
+[ 0-9a-f]+: 4d10 addiu t0,t0,-8
+[ 0-9a-f]+: 4d30 addiu t1,t1,-8
+[ 0-9a-f]+: 4d50 addiu t2,t2,-8
+[ 0-9a-f]+: 4fd0 addiu s8,s8,-8
+[ 0-9a-f]+: 4ff0 addiu ra,ra,-8
+[ 0-9a-f]+: 4ff2 addiu ra,ra,-7
+[ 0-9a-f]+: 4fe0 addiu ra,ra,0
+[ 0-9a-f]+: 4fe2 addiu ra,ra,1
+[ 0-9a-f]+: 4fec addiu ra,ra,6
+[ 0-9a-f]+: 4fee addiu ra,ra,7
+[ 0-9a-f]+: 33ff 0008 addiu ra,ra,8
+[ 0-9a-f]+: 4ffd addiu sp,sp,-1032
+[ 0-9a-f]+: 4fff addiu sp,sp,-1028
+[ 0-9a-f]+: 4e01 addiu sp,sp,-1024
+[ 0-9a-f]+: 4dff addiu sp,sp,1020
+[ 0-9a-f]+: 4c01 addiu sp,sp,1024
+[ 0-9a-f]+: 4c03 addiu sp,sp,1028
+[ 0-9a-f]+: 4c03 addiu sp,sp,1028
+[ 0-9a-f]+: 33bd 0408 addiu sp,sp,1032
+[ 0-9a-f]+: 6d2e addiu v0,v0,-1
+[ 0-9a-f]+: 6d3e addiu v0,v1,-1
+[ 0-9a-f]+: 6d4e addiu v0,a0,-1
+[ 0-9a-f]+: 6d5e addiu v0,a1,-1
+[ 0-9a-f]+: 6d6e addiu v0,a2,-1
+[ 0-9a-f]+: 6d7e addiu v0,a3,-1
+[ 0-9a-f]+: 6d0e addiu v0,s0,-1
+[ 0-9a-f]+: 6d1e addiu v0,s1,-1
+[ 0-9a-f]+: 6d10 addiu v0,s1,1
+[ 0-9a-f]+: 6d12 addiu v0,s1,4
+[ 0-9a-f]+: 6d14 addiu v0,s1,8
+[ 0-9a-f]+: 6d16 addiu v0,s1,12
+[ 0-9a-f]+: 6d18 addiu v0,s1,16
+[ 0-9a-f]+: 6d1a addiu v0,s1,20
+[ 0-9a-f]+: 6d1c addiu v0,s1,24
+[ 0-9a-f]+: 6d9c addiu v1,s1,24
+[ 0-9a-f]+: 6e1c addiu a0,s1,24
+[ 0-9a-f]+: 6e9c addiu a1,s1,24
+[ 0-9a-f]+: 6f1c addiu a2,s1,24
+[ 0-9a-f]+: 6f9c addiu a3,s1,24
+[ 0-9a-f]+: 6c1c addiu s0,s1,24
+[ 0-9a-f]+: 6c9c addiu s1,s1,24
+[ 0-9a-f]+: 0c5d move v0,sp
+[ 0-9a-f]+: 6d03 addiu v0,sp,4
+[ 0-9a-f]+: 6d7d addiu v0,sp,248
+[ 0-9a-f]+: 6d7f addiu v0,sp,252
+[ 0-9a-f]+: 305d 0100 addiu v0,sp,256
+[ 0-9a-f]+: 6d7f addiu v0,sp,252
+[ 0-9a-f]+: 6dff addiu v1,sp,252
+[ 0-9a-f]+: 6e7f addiu a0,sp,252
+[ 0-9a-f]+: 6eff addiu a1,sp,252
+[ 0-9a-f]+: 6f7f addiu a2,sp,252
+[ 0-9a-f]+: 6fff addiu a3,sp,252
+[ 0-9a-f]+: 6c7f addiu s0,sp,252
+[ 0-9a-f]+: 6cff addiu s1,sp,252
+[ 0-9a-f]+: 3064 8000 addiu v1,a0,-32768
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 3064 7fff addiu v1,a0,32767
+[ 0-9a-f]+: 3064 ffff addiu v1,a0,-1
+[ 0-9a-f]+: 3063 ffff addiu v1,v1,-1
+[ 0-9a-f]+: 3063 ffff addiu v1,v1,-1
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 0526 addu v0,v1,v0
+[ 0-9a-f]+: 0536 addu v0,v1,v1
+[ 0-9a-f]+: 0546 addu v0,v1,a0
+[ 0-9a-f]+: 0556 addu v0,v1,a1
+[ 0-9a-f]+: 0566 addu v0,v1,a2
+[ 0-9a-f]+: 0576 addu v0,v1,a3
+[ 0-9a-f]+: 0506 addu v0,v1,s0
+[ 0-9a-f]+: 0516 addu v0,v1,s1
+[ 0-9a-f]+: 0514 addu v0,v0,s1
+[ 0-9a-f]+: 0516 addu v0,v1,s1
+[ 0-9a-f]+: 0518 addu v0,a0,s1
+[ 0-9a-f]+: 051a addu v0,a1,s1
+[ 0-9a-f]+: 051c addu v0,a2,s1
+[ 0-9a-f]+: 051e addu v0,a3,s1
+[ 0-9a-f]+: 0510 addu v0,s0,s1
+[ 0-9a-f]+: 0512 addu v0,s1,s1
+[ 0-9a-f]+: 0514 addu v0,v0,s1
+[ 0-9a-f]+: 0594 addu v1,v0,s1
+[ 0-9a-f]+: 0614 addu a0,v0,s1
+[ 0-9a-f]+: 0694 addu a1,v0,s1
+[ 0-9a-f]+: 0714 addu a2,v0,s1
+[ 0-9a-f]+: 0794 addu a3,v0,s1
+[ 0-9a-f]+: 0414 addu s0,v0,s1
+[ 0-9a-f]+: 0494 addu s1,v0,s1
+[ 0-9a-f]+: 07ae addu a3,a3,v0
+[ 0-9a-f]+: 07ae addu a3,a3,v0
+[ 0-9a-f]+: 07f4 addu a3,v0,a3
+[ 0-9a-f]+: 03fe e950 addu sp,s8,ra
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ 0-9a-f]+: 3042 0001 addiu v0,v0,1
+[ 0-9a-f]+: 3042 7fff addiu v0,v0,32767
+[ 0-9a-f]+: 3042 8000 addiu v0,v0,-32768
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 1150 addu v0,v0,at
+[ 0-9a-f]+: 4492 and v0,v0,v0
+[ 0-9a-f]+: 4493 and v0,v0,v1
+[ 0-9a-f]+: 4494 and v0,v0,a0
+[ 0-9a-f]+: 4495 and v0,v0,a1
+[ 0-9a-f]+: 4496 and v0,v0,a2
+[ 0-9a-f]+: 4497 and v0,v0,a3
+[ 0-9a-f]+: 4490 and v0,v0,s0
+[ 0-9a-f]+: 4491 and v0,v0,s1
+[ 0-9a-f]+: 449a and v1,v1,v0
+[ 0-9a-f]+: 44a2 and a0,a0,v0
+[ 0-9a-f]+: 44aa and a1,a1,v0
+[ 0-9a-f]+: 44b2 and a2,a2,v0
+[ 0-9a-f]+: 44ba and a3,a3,v0
+[ 0-9a-f]+: 4482 and s0,s0,v0
+[ 0-9a-f]+: 448a and s1,s1,v0
+[ 0-9a-f]+: 4493 and v0,v0,v1
+[ 0-9a-f]+: 4493 and v0,v0,v1
+[ 0-9a-f]+: 4493 and v0,v0,v1
+[ 0-9a-f]+: 4493 and v0,v0,v1
+[ 0-9a-f]+: 0062 1250 and v0,v0,v1
+[ 0-9a-f]+: 2d21 andi v0,v0,0x1
+[ 0-9a-f]+: 2d22 andi v0,v0,0x2
+[ 0-9a-f]+: 2d23 andi v0,v0,0x3
+[ 0-9a-f]+: 2d24 andi v0,v0,0x4
+[ 0-9a-f]+: 2d25 andi v0,v0,0x7
+[ 0-9a-f]+: 2d26 andi v0,v0,0x8
+[ 0-9a-f]+: 2d27 andi v0,v0,0xf
+[ 0-9a-f]+: 2d28 andi v0,v0,0x10
+[ 0-9a-f]+: 2d29 andi v0,v0,0x1f
+[ 0-9a-f]+: 2d2a andi v0,v0,0x20
+[ 0-9a-f]+: 2d2b andi v0,v0,0x3f
+[ 0-9a-f]+: 2d2c andi v0,v0,0x40
+[ 0-9a-f]+: 2d20 andi v0,v0,0x80
+[ 0-9a-f]+: 2d2d andi v0,v0,0xff
+[ 0-9a-f]+: 2d2e andi v0,v0,0x8000
+[ 0-9a-f]+: 2d2f andi v0,v0,0xffff
+[ 0-9a-f]+: 2d3f andi v0,v1,0xffff
+[ 0-9a-f]+: 2d4f andi v0,a0,0xffff
+[ 0-9a-f]+: 2d5f andi v0,a1,0xffff
+[ 0-9a-f]+: 2d6f andi v0,a2,0xffff
+[ 0-9a-f]+: 2d7f andi v0,a3,0xffff
+[ 0-9a-f]+: 2d0f andi v0,s0,0xffff
+[ 0-9a-f]+: 2d1f andi v0,s1,0xffff
+[ 0-9a-f]+: 2d9f andi v1,s1,0xffff
+[ 0-9a-f]+: 2e1f andi a0,s1,0xffff
+[ 0-9a-f]+: 2e9f andi a1,s1,0xffff
+[ 0-9a-f]+: 2f1f andi a2,s1,0xffff
+[ 0-9a-f]+: 2f9f andi a3,s1,0xffff
+[ 0-9a-f]+: 2c1f andi s0,s1,0xffff
+[ 0-9a-f]+: 2c9f andi s1,s1,0xffff
+[ 0-9a-f]+: 2fff andi a3,a3,0xffff
+[ 0-9a-f]+: 2fff andi a3,a3,0xffff
+[ 0-9a-f]+: 2fff andi a3,a3,0xffff
+[ 0-9a-f]+: d0e7 ffff andi a3,a3,0xffff
+[ 0-9a-f]+: 0083 1250 and v0,v1,a0
+[ 0-9a-f]+: 0082 1250 and v0,v0,a0
+[ 0-9a-f]+: 0082 1250 and v0,v0,a0
+[ 0-9a-f]+: d043 0000 andi v0,v1,0x0
+[ 0-9a-f]+: d043 ffff andi v0,v1,0xffff
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1250 and v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0023 1250 and v0,v1,at
+[ 0-9a-f]+: 4280 fffe bc2f [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4280 fffe bc2f [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4284 fffe bc2f \$cc1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4288 fffe bc2f \$cc2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 428c fffe bc2f \$cc3,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4290 fffe bc2f \$cc4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4294 fffe bc2f \$cc5,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4298 fffe bc2f \$cc6,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 429c fffe bc2f \$cc7,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42a0 fffe bc2t [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42a0 fffe bc2t [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42a4 fffe bc2t \$cc1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42a8 fffe bc2t \$cc2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42ac fffe bc2t \$cc3,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42b0 fffe bc2t \$cc4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42b4 fffe bc2t \$cc5,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42b8 fffe bc2t \$cc6,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42bc fffe bc2t \$cc7,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42a4 fffe bc2t \$cc1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4288 fffe bc2f \$cc2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0107 3150 addu a2,a3,t0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 428c fffe bc2f \$cc3,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 42b0 fffe bc2t \$cc4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0107 3150 addu a2,a3,t0
+
+[0-9a-f]+ <test2>:
+[ 0-9a-f]+: 8d7f beqz v0,[0-9a-f]+ <test2>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8e7f beqz a0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8eff beqz a1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8f7f beqz a2,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8fff beqz a3,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8c7f beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8cff beqz s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8d7f beqz v0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8e7f beqz a0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8eff beqz a1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8f7f beqz a2,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8fff beqz a3,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8c7f beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8cff beqz s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8d7f beqz v0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8e7f beqz a0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8eff beqz a1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8f7f beqz a2,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8fff beqz a3,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8c7f beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8cff beqz s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8c7f beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9410 fffe beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8cff beqz s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9411 fffe beqz s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 40f1 fffe beqzc s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 9410 fffe beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: 9430 fffe beq s0,at,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 9430 fffe beq s0,at,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 9430 fffe beq s0,at,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: b630 fffe bne s0,s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b630 fffe bne s0,s1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b410 fffe bnez s0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b410 fffe bnez s0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b630 fffe bne s0,s1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b630 fffe bne s0,s1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b410 fffe bnez s0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b410 fffe bnez s0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9630 fffe beq s0,s1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9411 fffe beqz s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ad7f bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ae7f bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: aeff bnez a1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: af7f bnez a2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: afff bnez a3,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ac7f bnez s0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: acff bnez s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ad7f bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ae7f bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: aeff bnez a1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: af7f bnez a2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: afff bnez a3,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ac7f bnez s0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: acff bnez s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ad7f bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ae7f bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: aeff bnez a1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: af7f bnez a2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: afff bnez a3,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ac7f bnez s0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: acff bnez s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ac7f bnez s0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: b410 fffe bnez s0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: b411 fffe bnez s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: b411 fffe bnez s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+
+[0-9a-f]+ <test3>:
+[ 0-9a-f]+: 40b1 fffe bnezc s1,[0-9a-f]+ <test3>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 4680 break
+[ 0-9a-f]+: 4680 break
+[ 0-9a-f]+: 4681 break 0x1
+[ 0-9a-f]+: 4682 break 0x2
+[ 0-9a-f]+: 4683 break 0x3
+[ 0-9a-f]+: 4684 break 0x4
+[ 0-9a-f]+: 4685 break 0x5
+[ 0-9a-f]+: 4686 break 0x6
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 4688 break 0x8
+[ 0-9a-f]+: 4689 break 0x9
+[ 0-9a-f]+: 468a break 0xa
+[ 0-9a-f]+: 468b break 0xb
+[ 0-9a-f]+: 468c break 0xc
+[ 0-9a-f]+: 468d break 0xd
+[ 0-9a-f]+: 468e break 0xe
+[ 0-9a-f]+: 468f break 0xf
+[ 0-9a-f]+: 003f 0007 break 0x3f
+[ 0-9a-f]+: 0040 0007 break 0x40
+[ 0-9a-f]+: 03ff 0007 break 0x3ff
+[ 0-9a-f]+: 03ff ffc7 break 0x3ff,0x3ff
+[ 0-9a-f]+: 0000 0007 break
+[ 0-9a-f]+: 0000 0007 break
+[ 0-9a-f]+: 0001 0007 break 0x1
+[ 0-9a-f]+: 0002 0007 break 0x2
+[ 0-9a-f]+: 000f 0007 break 0xf
+[ 0-9a-f]+: 003f 0007 break 0x3f
+[ 0-9a-f]+: 0040 0007 break 0x40
+[ 0-9a-f]+: 03ff 0007 break 0x3ff
+[ 0-9a-f]+: 03ff ffc7 break 0x3ff,0x3ff
+[ 0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+[ 0-9a-f]+: 2000 6800 cache 0x0,-2048\(zero\)
+[ 0-9a-f]+: 2000 67ff cache 0x0,2047\(zero\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 2001 67ff cache 0x0,2047\(at\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 2001 6800 cache 0x0,-2048\(at\)
+[ 0-9a-f]+: 2002 6000 cache 0x0,0\(v0\)
+[ 0-9a-f]+: 2002 6800 cache 0x0,-2048\(v0\)
+[ 0-9a-f]+: 2002 67ff cache 0x0,2047\(v0\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 2001 67ff cache 0x0,2047\(at\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 2001 6800 cache 0x0,-2048\(at\)
+[ 0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+[ 0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+[ 0-9a-f]+: 2020 6000 cache 0x1,0\(zero\)
+[ 0-9a-f]+: 2040 6000 cache 0x2,0\(zero\)
+[ 0-9a-f]+: 2060 6000 cache 0x3,0\(zero\)
+[ 0-9a-f]+: 2080 6000 cache 0x4,0\(zero\)
+[ 0-9a-f]+: 20a0 6000 cache 0x5,0\(zero\)
+[ 0-9a-f]+: 20c0 6000 cache 0x6,0\(zero\)
+[ 0-9a-f]+: 23e0 6000 cache 0x1f,0\(zero\)
+[ 0-9a-f]+: 23e0 67ff cache 0x1f,2047\(zero\)
+[ 0-9a-f]+: 23e0 6800 cache 0x1f,-2048\(zero\)
+[ 0-9a-f]+: 2000 67ff cache 0x0,2047\(zero\)
+[ 0-9a-f]+: 2000 6800 cache 0x0,-2048\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6800 cache 0x1f,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 67ff cache 0x1f,2047\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 23e3 6fff cache 0x1f,-1\(v1\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6fff cache 0x1f,-1\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 23e1 6800 cache 0x1f,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 23e1 67ff cache 0x1f,2047\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 23e0 6fff cache 0x1f,-1\(zero\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 23e1 6fff cache 0x1f,-1\(at\)
+[ 0-9a-f]+: 0043 4b3c clo v0,v1
+[ 0-9a-f]+: 0062 4b3c clo v1,v0
+[ 0-9a-f]+: 0043 5b3c clz v0,v1
+[ 0-9a-f]+: 0062 5b3c clz v1,v0
+[ 0-9a-f]+: 0000 e37c deret
+[ 0-9a-f]+: 0000 477c di
+[ 0-9a-f]+: 0000 477c di
+[ 0-9a-f]+: 0002 477c di v0
+[ 0-9a-f]+: 0003 477c di v1
+[ 0-9a-f]+: 001e 477c di s8
+[ 0-9a-f]+: 001f 477c di ra
+[ 0-9a-f]+: 0062 ab3c div zero,v0,v1
+[ 0-9a-f]+: 03fe ab3c div zero,s8,ra
+[ 0-9a-f]+: 0060 ab3c div zero,zero,v1
+[ 0-9a-f]+: 03e0 ab3c div zero,zero,ra
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0004 703c teq a0,zero,0x7
+[ 0-9a-f]+: 0083 ab3c div zero,v1,a0
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b424 fffe bne a0,at,[0-9a-f]+ <test3\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: 0023 603c teq v1,at,0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 0080 1990 neg v1,a0
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 0024 ab3c div zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 0062 bb3c divu zero,v0,v1
+[ 0-9a-f]+: 03fe bb3c divu zero,s8,ra
+[ 0-9a-f]+: 0060 bb3c divu zero,zero,v1
+[ 0-9a-f]+: 03e0 bb3c divu zero,zero,ra
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0003 bb3c divu zero,v1,zero
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0004 703c teq a0,zero,0x7
+[ 0-9a-f]+: 0083 bb3c divu zero,v1,a0
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0024 bb3c divu zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 0024 bb3c divu zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 0000 577c ei
+[ 0-9a-f]+: 0000 577c ei
+[ 0-9a-f]+: 0002 577c ei v0
+[ 0-9a-f]+: 0003 577c ei v1
+[ 0-9a-f]+: 001e 577c ei s8
+[ 0-9a-f]+: 001f 577c ei ra
+[ 0-9a-f]+: 0000 f37c eret
+[ 0-9a-f]+: 0043 716c ext v0,v1,0x5,0xf
+[ 0-9a-f]+: 0043 f82c ext v0,v1,0x0,0x20
+[ 0-9a-f]+: 0043 07ec ext v0,v1,0x1f,0x1
+[ 0-9a-f]+: 03fe 07ec ext ra,s8,0x1f,0x1
+[ 0-9a-f]+: 0043 994c ins v0,v1,0x5,0xf
+[ 0-9a-f]+: 0043 f80c ins v0,v1,0x0,0x20
+[ 0-9a-f]+: 0043 ffcc ins v0,v1,0x1f,0x1
+[ 0-9a-f]+: 03fe ffcc ins ra,s8,0x1f,0x1
+[ 0-9a-f]+: 4580 jr zero
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4582 jr v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4583 jr v1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4584 jr a0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4585 jr a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4586 jr a2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4587 jr a3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4588 jr t0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 459e jr s8
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 459f jr ra
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0000 0f3c jr zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0002 0f3c jr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0003 0f3c jr v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0004 0f3c jr a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0005 0f3c jr a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0006 0f3c jr a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0007 0f3c jr a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0008 0f3c jr t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 001e 0f3c jr s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 001f 0f3c jr ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45a0 jrc zero
+[ 0-9a-f]+: 45a2 jrc v0
+[ 0-9a-f]+: 45a3 jrc v1
+[ 0-9a-f]+: 45a4 jrc a0
+[ 0-9a-f]+: 45a5 jrc a1
+[ 0-9a-f]+: 45a6 jrc a2
+[ 0-9a-f]+: 45a7 jrc a3
+[ 0-9a-f]+: 45a8 jrc t0
+[ 0-9a-f]+: 45be jrc s8
+[ 0-9a-f]+: 45bf jrc ra
+[ 0-9a-f]+: 0000 1f3c jr\.hb zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0002 1f3c jr\.hb v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0003 1f3c jr\.hb v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0004 1f3c jr\.hb a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0005 1f3c jr\.hb a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0006 1f3c jr\.hb a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0007 1f3c jr\.hb a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0008 1f3c jr\.hb t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 001e 1f3c jr\.hb s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 001f 1f3c jr\.hb ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4580 jr zero
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4582 jr v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4583 jr v1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4584 jr a0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4585 jr a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4586 jr a2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4587 jr a3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4588 jr t0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 459e jr s8
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 459f jr ra
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 45c0 jalr zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c2 jalr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c3 jalr v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c4 jalr a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c5 jalr a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c6 jalr a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c7 jalr a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c8 jalr t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45de jalr s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e0 0f3c jalr zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e2 0f3c jalr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e3 0f3c jalr v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e4 0f3c jalr a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e5 0f3c jalr a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e6 0f3c jalr a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e7 0f3c jalr a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e8 0f3c jalr t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03fe 0f3c jalr s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c0 jalr zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c2 jalr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c3 jalr v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c4 jalr a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c5 jalr a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c6 jalr a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c7 jalr a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c8 jalr t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45de jalr s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03df 0f3c jalr s8,ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0040 0f3c jalr v0,zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0062 0f3c jalr v1,v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0043 0f3c jalr v0,v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0044 0f3c jalr v0,a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0045 0f3c jalr v0,a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0046 0f3c jalr v0,a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0047 0f3c jalr v0,a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0048 0f3c jalr v0,t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 005e 0f3c jalr v0,s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 005f 0f3c jalr v0,ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e0 1f3c jalr\.hb zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e2 1f3c jalr\.hb v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e3 1f3c jalr\.hb v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e4 1f3c jalr\.hb a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e5 1f3c jalr\.hb a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e6 1f3c jalr\.hb a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e7 1f3c jalr\.hb a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e8 1f3c jalr\.hb t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03fe 1f3c jalr\.hb s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e0 1f3c jalr\.hb zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e2 1f3c jalr\.hb v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e3 1f3c jalr\.hb v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e4 1f3c jalr\.hb a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e5 1f3c jalr\.hb a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e6 1f3c jalr\.hb a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e7 1f3c jalr\.hb a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e8 1f3c jalr\.hb t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03fe 1f3c jalr\.hb s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03df 1f3c jalr\.hb s8,ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0040 1f3c jalr\.hb v0,zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0062 1f3c jalr\.hb v1,v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0043 1f3c jalr\.hb v0,v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0044 1f3c jalr\.hb v0,a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0045 1f3c jalr\.hb v0,a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0046 1f3c jalr\.hb v0,a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0047 1f3c jalr\.hb v0,a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0048 1f3c jalr\.hb v0,t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 005e 1f3c jalr\.hb v0,s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 005f 1f3c jalr\.hb v0,ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0043 0f3c jalr v0,v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03df 0f3c jalr s8,ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c3 jalr v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45df jalr ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: f400 0000 jal [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: f400 0000 jal [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: f000 0000 jalx [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: f000 0000 jalx [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 41a2 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 41a2 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 1c60 0000 lb v1,0\(zero\)
+[ 0-9a-f]+: 1c60 0004 lb v1,4\(zero\)
+[ 0-9a-f]+: 1c60 0000 lb v1,0\(zero\)
+[ 0-9a-f]+: 1c60 0004 lb v1,4\(zero\)
+[ 0-9a-f]+: 1c60 7fff lb v1,32767\(zero\)
+[ 0-9a-f]+: 1c60 8000 lb v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 1c63 ffff lb v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c60 8000 lb v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 1c63 0001 lb v1,1\(v1\)
+[ 0-9a-f]+: 1c60 8001 lb v1,-32767\(zero\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c60 ffff lb v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 1c63 5678 lb v1,22136\(v1\)
+[ 0-9a-f]+: 1c64 0000 lb v1,0\(a0\)
+[ 0-9a-f]+: 1c64 0000 lb v1,0\(a0\)
+[ 0-9a-f]+: 1c64 0004 lb v1,4\(a0\)
+[ 0-9a-f]+: 1c64 7fff lb v1,32767\(a0\)
+[ 0-9a-f]+: 1c64 8000 lb v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 ffff lb v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c64 8000 lb v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 0001 lb v1,1\(v1\)
+[ 0-9a-f]+: 1c64 8001 lb v1,-32767\(a0\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c64 ffff lb v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 5678 lb v1,22136\(v1\)
+[ 0-9a-f]+: 093f lbu v0,-1\(v1\)
+[ 0-9a-f]+: 0930 lbu v0,0\(v1\)
+[ 0-9a-f]+: 0930 lbu v0,0\(v1\)
+[ 0-9a-f]+: 0931 lbu v0,1\(v1\)
+[ 0-9a-f]+: 0932 lbu v0,2\(v1\)
+[ 0-9a-f]+: 0933 lbu v0,3\(v1\)
+[ 0-9a-f]+: 0934 lbu v0,4\(v1\)
+[ 0-9a-f]+: 0935 lbu v0,5\(v1\)
+[ 0-9a-f]+: 0936 lbu v0,6\(v1\)
+[ 0-9a-f]+: 0937 lbu v0,7\(v1\)
+[ 0-9a-f]+: 0938 lbu v0,8\(v1\)
+[ 0-9a-f]+: 0939 lbu v0,9\(v1\)
+[ 0-9a-f]+: 093a lbu v0,10\(v1\)
+[ 0-9a-f]+: 093b lbu v0,11\(v1\)
+[ 0-9a-f]+: 093c lbu v0,12\(v1\)
+[ 0-9a-f]+: 093d lbu v0,13\(v1\)
+[ 0-9a-f]+: 093e lbu v0,14\(v1\)
+[ 0-9a-f]+: 092e lbu v0,14\(v0\)
+[ 0-9a-f]+: 094e lbu v0,14\(a0\)
+[ 0-9a-f]+: 095e lbu v0,14\(a1\)
+[ 0-9a-f]+: 096e lbu v0,14\(a2\)
+[ 0-9a-f]+: 097e lbu v0,14\(a3\)
+[ 0-9a-f]+: 090e lbu v0,14\(s0\)
+[ 0-9a-f]+: 091e lbu v0,14\(s1\)
+[ 0-9a-f]+: 099e lbu v1,14\(s1\)
+[ 0-9a-f]+: 0a1e lbu a0,14\(s1\)
+[ 0-9a-f]+: 0a9e lbu a1,14\(s1\)
+[ 0-9a-f]+: 0b1e lbu a2,14\(s1\)
+[ 0-9a-f]+: 0b9e lbu a3,14\(s1\)
+[ 0-9a-f]+: 081e lbu s0,14\(s1\)
+[ 0-9a-f]+: 089e lbu s1,14\(s1\)
+[ 0-9a-f]+: 1460 0000 lbu v1,0\(zero\)
+[ 0-9a-f]+: 1460 0004 lbu v1,4\(zero\)
+[ 0-9a-f]+: 1460 0000 lbu v1,0\(zero\)
+[ 0-9a-f]+: 1460 0004 lbu v1,4\(zero\)
+[ 0-9a-f]+: 1460 7fff lbu v1,32767\(zero\)
+[ 0-9a-f]+: 1460 8000 lbu v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 1463 ffff lbu v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1460 8000 lbu v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 1463 0001 lbu v1,1\(v1\)
+[ 0-9a-f]+: 1460 8001 lbu v1,-32767\(zero\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1460 ffff lbu v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 1463 5678 lbu v1,22136\(v1\)
+[ 0-9a-f]+: 09c0 lbu v1,0\(a0\)
+[ 0-9a-f]+: 09c0 lbu v1,0\(a0\)
+[ 0-9a-f]+: 09c4 lbu v1,4\(a0\)
+[ 0-9a-f]+: 1464 7fff lbu v1,32767\(a0\)
+[ 0-9a-f]+: 1464 8000 lbu v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 ffff lbu v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1464 8000 lbu v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 0001 lbu v1,1\(v1\)
+[ 0-9a-f]+: 1464 8001 lbu v1,-32767\(a0\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1464 ffff lbu v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 5678 lbu v1,22136\(v1\)
+[ 0-9a-f]+: 3c60 0000 lh v1,0\(zero\)
+[ 0-9a-f]+: 3c60 0004 lh v1,4\(zero\)
+[ 0-9a-f]+: 3c60 0000 lh v1,0\(zero\)
+[ 0-9a-f]+: 3c60 0004 lh v1,4\(zero\)
+[ 0-9a-f]+: 3c60 7fff lh v1,32767\(zero\)
+[ 0-9a-f]+: 3c60 8000 lh v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 3c63 ffff lh v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c60 8000 lh v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 3c63 0001 lh v1,1\(v1\)
+[ 0-9a-f]+: 3c60 8001 lh v1,-32767\(zero\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c60 ffff lh v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 3c63 5678 lh v1,22136\(v1\)
+[ 0-9a-f]+: 3c64 0000 lh v1,0\(a0\)
+[ 0-9a-f]+: 3c64 0000 lh v1,0\(a0\)
+[ 0-9a-f]+: 3c64 0004 lh v1,4\(a0\)
+[ 0-9a-f]+: 3c64 7fff lh v1,32767\(a0\)
+[ 0-9a-f]+: 3c64 8000 lh v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 ffff lh v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c64 8000 lh v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 0001 lh v1,1\(v1\)
+[ 0-9a-f]+: 3c64 8001 lh v1,-32767\(a0\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c64 ffff lh v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 5678 lh v1,22136\(v1\)
+[ 0-9a-f]+: 2930 lhu v0,0\(v1\)
+[ 0-9a-f]+: 2930 lhu v0,0\(v1\)
+[ 0-9a-f]+: 2931 lhu v0,2\(v1\)
+[ 0-9a-f]+: 2932 lhu v0,4\(v1\)
+[ 0-9a-f]+: 2933 lhu v0,6\(v1\)
+[ 0-9a-f]+: 2934 lhu v0,8\(v1\)
+[ 0-9a-f]+: 2935 lhu v0,10\(v1\)
+[ 0-9a-f]+: 2936 lhu v0,12\(v1\)
+[ 0-9a-f]+: 2937 lhu v0,14\(v1\)
+[ 0-9a-f]+: 2938 lhu v0,16\(v1\)
+[ 0-9a-f]+: 2939 lhu v0,18\(v1\)
+[ 0-9a-f]+: 293a lhu v0,20\(v1\)
+[ 0-9a-f]+: 293b lhu v0,22\(v1\)
+[ 0-9a-f]+: 293c lhu v0,24\(v1\)
+[ 0-9a-f]+: 293d lhu v0,26\(v1\)
+[ 0-9a-f]+: 293e lhu v0,28\(v1\)
+[ 0-9a-f]+: 293f lhu v0,30\(v1\)
+[ 0-9a-f]+: 294f lhu v0,30\(a0\)
+[ 0-9a-f]+: 295f lhu v0,30\(a1\)
+[ 0-9a-f]+: 296f lhu v0,30\(a2\)
+[ 0-9a-f]+: 297f lhu v0,30\(a3\)
+[ 0-9a-f]+: 292f lhu v0,30\(v0\)
+[ 0-9a-f]+: 290f lhu v0,30\(s0\)
+[ 0-9a-f]+: 291f lhu v0,30\(s1\)
+[ 0-9a-f]+: 299f lhu v1,30\(s1\)
+[ 0-9a-f]+: 2a1f lhu a0,30\(s1\)
+[ 0-9a-f]+: 2a9f lhu a1,30\(s1\)
+[ 0-9a-f]+: 2b1f lhu a2,30\(s1\)
+[ 0-9a-f]+: 2b9f lhu a3,30\(s1\)
+[ 0-9a-f]+: 281f lhu s0,30\(s1\)
+[ 0-9a-f]+: 289f lhu s1,30\(s1\)
+[ 0-9a-f]+: 3460 0000 lhu v1,0\(zero\)
+[ 0-9a-f]+: 3460 0004 lhu v1,4\(zero\)
+[ 0-9a-f]+: 3460 0000 lhu v1,0\(zero\)
+[ 0-9a-f]+: 3460 0004 lhu v1,4\(zero\)
+[ 0-9a-f]+: 3460 7fff lhu v1,32767\(zero\)
+[ 0-9a-f]+: 3460 8000 lhu v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 3463 ffff lhu v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3460 8000 lhu v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 3463 0001 lhu v1,1\(v1\)
+[ 0-9a-f]+: 3460 8001 lhu v1,-32767\(zero\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3460 ffff lhu v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 3463 5678 lhu v1,22136\(v1\)
+[ 0-9a-f]+: 29c0 lhu v1,0\(a0\)
+[ 0-9a-f]+: 29c0 lhu v1,0\(a0\)
+[ 0-9a-f]+: 29c2 lhu v1,4\(a0\)
+[ 0-9a-f]+: 3464 7fff lhu v1,32767\(a0\)
+[ 0-9a-f]+: 3464 8000 lhu v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 ffff lhu v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3464 8000 lhu v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 0001 lhu v1,1\(v1\)
+[ 0-9a-f]+: 3464 8001 lhu v1,-32767\(a0\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3464 ffff lhu v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 5678 lhu v1,22136\(v1\)
+[ 0-9a-f]+: 6060 3000 ll v1,0\(zero\)
+[ 0-9a-f]+: 6060 3000 ll v1,0\(zero\)
+[ 0-9a-f]+: 6060 3004 ll v1,4\(zero\)
+[ 0-9a-f]+: 6060 3004 ll v1,4\(zero\)
+[ 0-9a-f]+: 5060 8000 li v1,0x8000
+[ 0-9a-f]+: 6063 3fff ll v1,-1\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 6063 3fff ll v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 6060 3fff ll v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 5063 5000 ori v1,v1,0x5000
+[ 0-9a-f]+: 6063 3678 ll v1,1656\(v1\)
+[ 0-9a-f]+: 6064 3000 ll v1,0\(a0\)
+[ 0-9a-f]+: 6064 3000 ll v1,0\(a0\)
+[ 0-9a-f]+: 6064 3004 ll v1,4\(a0\)
+[ 0-9a-f]+: 5060 8000 li v1,0x8000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3fff ll v1,-1\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3fff ll v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 6064 3fff ll v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 5063 5000 ori v1,v1,0x5000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3678 ll v1,1656\(v1\)
+[ 0-9a-f]+: 41a3 0000 lui v1,0x0
+[ 0-9a-f]+: 41a3 7fff lui v1,0x7fff
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 6940 lw v0,0\(a0\)
+[ 0-9a-f]+: 6940 lw v0,0\(a0\)
+[ 0-9a-f]+: 6941 lw v0,4\(a0\)
+[ 0-9a-f]+: 6942 lw v0,8\(a0\)
+[ 0-9a-f]+: 6943 lw v0,12\(a0\)
+[ 0-9a-f]+: 6944 lw v0,16\(a0\)
+[ 0-9a-f]+: 6945 lw v0,20\(a0\)
+[ 0-9a-f]+: 6946 lw v0,24\(a0\)
+[ 0-9a-f]+: 6947 lw v0,28\(a0\)
+[ 0-9a-f]+: 6948 lw v0,32\(a0\)
+[ 0-9a-f]+: 6949 lw v0,36\(a0\)
+[ 0-9a-f]+: 694a lw v0,40\(a0\)
+[ 0-9a-f]+: 694b lw v0,44\(a0\)
+[ 0-9a-f]+: 694c lw v0,48\(a0\)
+[ 0-9a-f]+: 694d lw v0,52\(a0\)
+[ 0-9a-f]+: 694e lw v0,56\(a0\)
+[ 0-9a-f]+: 694f lw v0,60\(a0\)
+[ 0-9a-f]+: 695f lw v0,60\(a1\)
+[ 0-9a-f]+: 696f lw v0,60\(a2\)
+[ 0-9a-f]+: 697f lw v0,60\(a3\)
+[ 0-9a-f]+: 692f lw v0,60\(v0\)
+[ 0-9a-f]+: 693f lw v0,60\(v1\)
+[ 0-9a-f]+: 690f lw v0,60\(s0\)
+[ 0-9a-f]+: 691f lw v0,60\(s1\)
+[ 0-9a-f]+: 699f lw v1,60\(s1\)
+[ 0-9a-f]+: 6a1f lw a0,60\(s1\)
+[ 0-9a-f]+: 6a9f lw a1,60\(s1\)
+[ 0-9a-f]+: 6b1f lw a2,60\(s1\)
+[ 0-9a-f]+: 6b9f lw a3,60\(s1\)
+[ 0-9a-f]+: 681f lw s0,60\(s1\)
+[ 0-9a-f]+: 689f lw s1,60\(s1\)
+[ 0-9a-f]+: 4880 lw a0,0\(sp\)
+[ 0-9a-f]+: 4880 lw a0,0\(sp\)
+[ 0-9a-f]+: 4881 lw a0,4\(sp\)
+[ 0-9a-f]+: 4882 lw a0,8\(sp\)
+[ 0-9a-f]+: 4883 lw a0,12\(sp\)
+[ 0-9a-f]+: 4884 lw a0,16\(sp\)
+[ 0-9a-f]+: 4885 lw a0,20\(sp\)
+[ 0-9a-f]+: 489f lw a0,124\(sp\)
+[ 0-9a-f]+: 485f lw v0,124\(sp\)
+[ 0-9a-f]+: 485f lw v0,124\(sp\)
+[ 0-9a-f]+: 487f lw v1,124\(sp\)
+[ 0-9a-f]+: 489f lw a0,124\(sp\)
+[ 0-9a-f]+: 48bf lw a1,124\(sp\)
+[ 0-9a-f]+: 48df lw a2,124\(sp\)
+[ 0-9a-f]+: 48ff lw a3,124\(sp\)
+[ 0-9a-f]+: 491f lw t0,124\(sp\)
+[ 0-9a-f]+: 493f lw t1,124\(sp\)
+[ 0-9a-f]+: 495f lw t2,124\(sp\)
+[ 0-9a-f]+: 4bdf lw s8,124\(sp\)
+[ 0-9a-f]+: 4bff lw ra,124\(sp\)
+[ 0-9a-f]+: fc9d 01f8 lw a0,504\(sp\)
+[ 0-9a-f]+: fc9d 01fc lw a0,508\(sp\)
+[ 0-9a-f]+: fe1d 01fc lw s0,508\(sp\)
+[ 0-9a-f]+: fe3d 01fc lw s1,508\(sp\)
+[ 0-9a-f]+: fe5d 01fc lw s2,508\(sp\)
+[ 0-9a-f]+: fe7d 01fc lw s3,508\(sp\)
+[ 0-9a-f]+: fe9d 01fc lw s4,508\(sp\)
+[ 0-9a-f]+: febd 01fc lw s5,508\(sp\)
+[ 0-9a-f]+: fffd 01fc lw ra,508\(sp\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc60 7fff lw v1,32767\(zero\)
+[ 0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: fc63 ffff lw v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: fc63 0001 lw v1,1\(v1\)
+[ 0-9a-f]+: fc60 8001 lw v1,-32767\(zero\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc60 ffff lw v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: fc63 5678 lw v1,22136\(v1\)
+[ 0-9a-f]+: 69c0 lw v1,0\(a0\)
+[ 0-9a-f]+: 69c0 lw v1,0\(a0\)
+[ 0-9a-f]+: 69c1 lw v1,4\(a0\)
+[ 0-9a-f]+: fc64 7fff lw v1,32767\(a0\)
+[ 0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 ffff lw v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 0001 lw v1,1\(v1\)
+[ 0-9a-f]+: fc64 8001 lw v1,-32767\(a0\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc64 ffff lw v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 5678 lw v1,22136\(v1\)
+[ 0-9a-f]+: 450c lwm s0,ra,48\(sp\)
+[ 0-9a-f]+: 451c lwm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 451c lwm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 452c lwm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 452c lwm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 453c lwm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 453c lwm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 4500 lwm s0,ra,0\(sp\)
+[ 0-9a-f]+: 4500 lwm s0,ra,0\(sp\)
+[ 0-9a-f]+: 4501 lwm s0,ra,4\(sp\)
+[ 0-9a-f]+: 4502 lwm s0,ra,8\(sp\)
+[ 0-9a-f]+: 4503 lwm s0,ra,12\(sp\)
+[ 0-9a-f]+: 4504 lwm s0,ra,16\(sp\)
+[ 0-9a-f]+: 4505 lwm s0,ra,20\(sp\)
+[ 0-9a-f]+: 4506 lwm s0,ra,24\(sp\)
+[ 0-9a-f]+: 4507 lwm s0,ra,28\(sp\)
+[ 0-9a-f]+: 4508 lwm s0,ra,32\(sp\)
+[ 0-9a-f]+: 4509 lwm s0,ra,36\(sp\)
+[ 0-9a-f]+: 450a lwm s0,ra,40\(sp\)
+[ 0-9a-f]+: 450b lwm s0,ra,44\(sp\)
+[ 0-9a-f]+: 450c lwm s0,ra,48\(sp\)
+[ 0-9a-f]+: 450d lwm s0,ra,52\(sp\)
+[ 0-9a-f]+: 450e lwm s0,ra,56\(sp\)
+[ 0-9a-f]+: 450f lwm s0,ra,60\(sp\)
+[ 0-9a-f]+: 2020 5000 lwm s0,0\(zero\)
+[ 0-9a-f]+: 2020 5004 lwm s0,4\(zero\)
+[ 0-9a-f]+: 2025 5000 lwm s0,0\(a1\)
+[ 0-9a-f]+: 2025 57ff lwm s0,2047\(a1\)
+[ 0-9a-f]+: 2045 57ff lwm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 57ff lwm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 57ff lwm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 57ff lwm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 57ff lwm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 57ff lwm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 57ff lwm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 57ff lwm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 57ff lwm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 5000 lwm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 5000 lwm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 5000 lwm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 5000 lwm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 5000 lwm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 5000 lwm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 5000 lwm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 5000 lwm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 5000 lwm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+[ 0-9a-f]+: 2020 5000 lwm s0,0\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+[ 0-9a-f]+: 203d 5000 lwm s0,0\(sp\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+[ 0-9a-f]+: 2040 1000 lwp v0,0\(zero\)
+[ 0-9a-f]+: 2040 1004 lwp v0,4\(zero\)
+[ 0-9a-f]+: 205d 1000 lwp v0,0\(sp\)
+[ 0-9a-f]+: 205d 1000 lwp v0,0\(sp\)
+[ 0-9a-f]+: 2043 1800 lwp v0,-2048\(v1\)
+[ 0-9a-f]+: 2043 17ff lwp v0,2047\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 1000 lwp v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 1fff lwp v0,-1\(at\)
+[ 0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 1fff lwp v0,-1\(at\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
+[ 0-9a-f]+: 5060 8000 li v1,0x8000
+[ 0-9a-f]+: 2043 1fff lwp v0,-1\(v1\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 2043 1fff lwp v0,-1\(v1\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 07ff lwl v1,2047\(zero\)
+[ 0-9a-f]+: 6060 0800 lwl v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6060 0fff lwl v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 0678 lwl v1,1656\(at\)
+[ 0-9a-f]+: 6064 0000 lwl v1,0\(a0\)
+[ 0-9a-f]+: 6064 0000 lwl v1,0\(a0\)
+[ 0-9a-f]+: 6064 07ff lwl v1,2047\(a0\)
+[ 0-9a-f]+: 6064 0800 lwl v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6064 0fff lwl v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0678 lwl v1,1656\(at\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 07ff lwl v1,2047\(zero\)
+[ 0-9a-f]+: 6060 0800 lwl v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6060 0fff lwl v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 0678 lwl v1,1656\(at\)
+[ 0-9a-f]+: 6064 0000 lwl v1,0\(a0\)
+[ 0-9a-f]+: 6064 0000 lwl v1,0\(a0\)
+[ 0-9a-f]+: 6064 07ff lwl v1,2047\(a0\)
+[ 0-9a-f]+: 6064 0800 lwl v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6064 0fff lwl v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0678 lwl v1,1656\(at\)
+[ 0-9a-f]+: 6060 1004 lwr v1,4\(zero\)
+[ 0-9a-f]+: 6060 1004 lwr v1,4\(zero\)
+[ 0-9a-f]+: 6060 1000 lwr v1,0\(zero\)
+[ 0-9a-f]+: 6060 1000 lwr v1,0\(zero\)
+[ 0-9a-f]+: 6060 17ff lwr v1,2047\(zero\)
+[ 0-9a-f]+: 6060 1800 lwr v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 6060 1fff lwr v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 1678 lwr v1,1656\(at\)
+[ 0-9a-f]+: 6064 1000 lwr v1,0\(a0\)
+[ 0-9a-f]+: 6064 1000 lwr v1,0\(a0\)
+[ 0-9a-f]+: 6064 17ff lwr v1,2047\(a0\)
+[ 0-9a-f]+: 6064 1800 lwr v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 6064 1fff lwr v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1678 lwr v1,1656\(at\)
+[ 0-9a-f]+: 6060 1004 lwr v1,4\(zero\)
+[ 0-9a-f]+: 6060 1004 lwr v1,4\(zero\)
+[ 0-9a-f]+: 6060 1000 lwr v1,0\(zero\)
+[ 0-9a-f]+: 6060 1000 lwr v1,0\(zero\)
+[ 0-9a-f]+: 6060 17ff lwr v1,2047\(zero\)
+[ 0-9a-f]+: 6060 1800 lwr v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 6060 1fff lwr v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 1678 lwr v1,1656\(at\)
+[ 0-9a-f]+: 6064 1000 lwr v1,0\(a0\)
+[ 0-9a-f]+: 6064 1000 lwr v1,0\(a0\)
+[ 0-9a-f]+: 6064 17ff lwr v1,2047\(a0\)
+[ 0-9a-f]+: 6064 1800 lwr v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 6064 1fff lwr v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1678 lwr v1,1656\(at\)
+[ 0-9a-f]+: 0085 1918 lwxs v1,a0\(a1\)
+[ 0-9a-f]+: 00a4 cb3c madd a0,a1
+[ 0-9a-f]+: 00a4 db3c maddu a0,a1
+[ 0-9a-f]+: 0040 00fc mfc0 v0,c0_index
+[ 0-9a-f]+: 0041 00fc mfc0 v0,c0_random
+[ 0-9a-f]+: 0042 00fc mfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0043 00fc mfc0 v0,c0_entrylo1
+[ 0-9a-f]+: 0044 00fc mfc0 v0,c0_context
+[ 0-9a-f]+: 0045 00fc mfc0 v0,c0_pagemask
+[ 0-9a-f]+: 0046 00fc mfc0 v0,c0_wired
+[ 0-9a-f]+: 0047 00fc mfc0 v0,c0_hwrena
+[ 0-9a-f]+: 0048 00fc mfc0 v0,c0_badvaddr
+[ 0-9a-f]+: 0049 00fc mfc0 v0,c0_count
+[ 0-9a-f]+: 004a 00fc mfc0 v0,c0_entryhi
+[ 0-9a-f]+: 004b 00fc mfc0 v0,c0_compare
+[ 0-9a-f]+: 004c 00fc mfc0 v0,c0_status
+[ 0-9a-f]+: 004d 00fc mfc0 v0,c0_cause
+[ 0-9a-f]+: 004e 00fc mfc0 v0,c0_epc
+[ 0-9a-f]+: 004f 00fc mfc0 v0,c0_prid
+[ 0-9a-f]+: 0050 00fc mfc0 v0,c0_config
+[ 0-9a-f]+: 0051 00fc mfc0 v0,c0_lladdr
+[ 0-9a-f]+: 0052 00fc mfc0 v0,c0_watchlo
+[ 0-9a-f]+: 0053 00fc mfc0 v0,c0_watchhi
+[ 0-9a-f]+: 0054 00fc mfc0 v0,c0_xcontext
+[ 0-9a-f]+: 0055 00fc mfc0 v0,\$21
+[ 0-9a-f]+: 0056 00fc mfc0 v0,\$22
+[ 0-9a-f]+: 0057 00fc mfc0 v0,c0_debug
+[ 0-9a-f]+: 0058 00fc mfc0 v0,c0_depc
+[ 0-9a-f]+: 0059 00fc mfc0 v0,c0_perfcnt
+[ 0-9a-f]+: 005a 00fc mfc0 v0,c0_errctl
+[ 0-9a-f]+: 005b 00fc mfc0 v0,c0_cacheerr
+[ 0-9a-f]+: 005c 00fc mfc0 v0,c0_taglo
+[ 0-9a-f]+: 005d 00fc mfc0 v0,c0_taghi
+[ 0-9a-f]+: 005e 00fc mfc0 v0,c0_errorepc
+[ 0-9a-f]+: 005f 00fc mfc0 v0,c0_desave
+[ 0-9a-f]+: 0040 00fc mfc0 v0,c0_index
+[ 0-9a-f]+: 0040 08fc mfc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 0040 10fc mfc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 0040 18fc mfc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 0040 20fc mfc0 v0,\$0,4
+[ 0-9a-f]+: 0040 28fc mfc0 v0,\$0,5
+[ 0-9a-f]+: 0040 30fc mfc0 v0,\$0,6
+[ 0-9a-f]+: 0040 38fc mfc0 v0,\$0,7
+[ 0-9a-f]+: 0041 00fc mfc0 v0,c0_random
+[ 0-9a-f]+: 0041 08fc mfc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 0041 10fc mfc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 0041 18fc mfc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 0041 20fc mfc0 v0,c0_yqmask
+[ 0-9a-f]+: 0041 28fc mfc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 0041 30fc mfc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 0041 38fc mfc0 v0,\$1,7
+[ 0-9a-f]+: 0042 00fc mfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0042 08fc mfc0 v0,c0_tcstatus
+[ 0-9a-f]+: 0042 10fc mfc0 v0,c0_tcbind
+[ 0-9a-f]+: 0042 18fc mfc0 v0,c0_tcrestart
+[ 0-9a-f]+: 0042 20fc mfc0 v0,c0_tchalt
+[ 0-9a-f]+: 0042 28fc mfc0 v0,c0_tccontext
+[ 0-9a-f]+: 0042 30fc mfc0 v0,c0_tcschedule
+[ 0-9a-f]+: 0042 38fc mfc0 v0,c0_tcschefback
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 4602 mfhi v0
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 4604 mfhi a0
+[ 0-9a-f]+: 461d mfhi sp
+[ 0-9a-f]+: 461e mfhi s8
+[ 0-9a-f]+: 461f mfhi ra
+[ 0-9a-f]+: 0000 0d7c mfhi zero
+[ 0-9a-f]+: 0002 0d7c mfhi v0
+[ 0-9a-f]+: 0003 0d7c mfhi v1
+[ 0-9a-f]+: 0004 0d7c mfhi a0
+[ 0-9a-f]+: 001d 0d7c mfhi sp
+[ 0-9a-f]+: 001e 0d7c mfhi s8
+[ 0-9a-f]+: 001f 0d7c mfhi ra
+[ 0-9a-f]+: 4640 mflo zero
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 4644 mflo a0
+[ 0-9a-f]+: 465d mflo sp
+[ 0-9a-f]+: 465e mflo s8
+[ 0-9a-f]+: 465f mflo ra
+[ 0-9a-f]+: 0000 1d7c mflo zero
+[ 0-9a-f]+: 0002 1d7c mflo v0
+[ 0-9a-f]+: 0003 1d7c mflo v1
+[ 0-9a-f]+: 0004 1d7c mflo a0
+[ 0-9a-f]+: 001d 1d7c mflo sp
+[ 0-9a-f]+: 001e 1d7c mflo s8
+[ 0-9a-f]+: 001f 1d7c mflo ra
+[ 0-9a-f]+: 0062 1018 movn v0,v0,v1
+[ 0-9a-f]+: 0062 1018 movn v0,v0,v1
+[ 0-9a-f]+: 0083 1018 movn v0,v1,a0
+[ 0-9a-f]+: 0062 1058 movz v0,v0,v1
+[ 0-9a-f]+: 0062 1058 movz v0,v0,v1
+[ 0-9a-f]+: 0083 1058 movz v0,v1,a0
+[ 0-9a-f]+: 00a4 eb3c msub a0,a1
+[ 0-9a-f]+: 00a4 fb3c msubu a0,a1
+[ 0-9a-f]+: 0040 02fc mtc0 v0,c0_index
+[ 0-9a-f]+: 0041 02fc mtc0 v0,c0_random
+[ 0-9a-f]+: 0042 02fc mtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0043 02fc mtc0 v0,c0_entrylo1
+[ 0-9a-f]+: 0044 02fc mtc0 v0,c0_context
+[ 0-9a-f]+: 0045 02fc mtc0 v0,c0_pagemask
+[ 0-9a-f]+: 0046 02fc mtc0 v0,c0_wired
+[ 0-9a-f]+: 0047 02fc mtc0 v0,c0_hwrena
+[ 0-9a-f]+: 0048 02fc mtc0 v0,c0_badvaddr
+[ 0-9a-f]+: 0049 02fc mtc0 v0,c0_count
+[ 0-9a-f]+: 004a 02fc mtc0 v0,c0_entryhi
+[ 0-9a-f]+: 004b 02fc mtc0 v0,c0_compare
+[ 0-9a-f]+: 004c 02fc mtc0 v0,c0_status
+[ 0-9a-f]+: 004d 02fc mtc0 v0,c0_cause
+[ 0-9a-f]+: 004e 02fc mtc0 v0,c0_epc
+[ 0-9a-f]+: 004f 02fc mtc0 v0,c0_prid
+[ 0-9a-f]+: 0050 02fc mtc0 v0,c0_config
+[ 0-9a-f]+: 0051 02fc mtc0 v0,c0_lladdr
+[ 0-9a-f]+: 0052 02fc mtc0 v0,c0_watchlo
+[ 0-9a-f]+: 0053 02fc mtc0 v0,c0_watchhi
+[ 0-9a-f]+: 0054 02fc mtc0 v0,c0_xcontext
+[ 0-9a-f]+: 0055 02fc mtc0 v0,\$21
+[ 0-9a-f]+: 0056 02fc mtc0 v0,\$22
+[ 0-9a-f]+: 0057 02fc mtc0 v0,c0_debug
+[ 0-9a-f]+: 0058 02fc mtc0 v0,c0_depc
+[ 0-9a-f]+: 0059 02fc mtc0 v0,c0_perfcnt
+[ 0-9a-f]+: 005a 02fc mtc0 v0,c0_errctl
+[ 0-9a-f]+: 005b 02fc mtc0 v0,c0_cacheerr
+[ 0-9a-f]+: 005c 02fc mtc0 v0,c0_taglo
+[ 0-9a-f]+: 005d 02fc mtc0 v0,c0_taghi
+[ 0-9a-f]+: 005e 02fc mtc0 v0,c0_errorepc
+[ 0-9a-f]+: 005f 02fc mtc0 v0,c0_desave
+[ 0-9a-f]+: 0040 02fc mtc0 v0,c0_index
+[ 0-9a-f]+: 0040 0afc mtc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 0040 12fc mtc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 0040 1afc mtc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 0040 22fc mtc0 v0,\$0,4
+[ 0-9a-f]+: 0040 2afc mtc0 v0,\$0,5
+[ 0-9a-f]+: 0040 32fc mtc0 v0,\$0,6
+[ 0-9a-f]+: 0040 3afc mtc0 v0,\$0,7
+[ 0-9a-f]+: 0041 02fc mtc0 v0,c0_random
+[ 0-9a-f]+: 0041 0afc mtc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 0041 12fc mtc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 0041 1afc mtc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 0041 22fc mtc0 v0,c0_yqmask
+[ 0-9a-f]+: 0041 2afc mtc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 0041 32fc mtc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 0041 3afc mtc0 v0,\$1,7
+[ 0-9a-f]+: 0042 02fc mtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0042 0afc mtc0 v0,c0_tcstatus
+[ 0-9a-f]+: 0042 12fc mtc0 v0,c0_tcbind
+[ 0-9a-f]+: 0042 1afc mtc0 v0,c0_tcrestart
+[ 0-9a-f]+: 0042 22fc mtc0 v0,c0_tchalt
+[ 0-9a-f]+: 0042 2afc mtc0 v0,c0_tccontext
+[ 0-9a-f]+: 0042 32fc mtc0 v0,c0_tcschedule
+[ 0-9a-f]+: 0042 3afc mtc0 v0,c0_tcschefback
+[ 0-9a-f]+: 0000 2d7c mthi zero
+[ 0-9a-f]+: 0002 2d7c mthi v0
+[ 0-9a-f]+: 0003 2d7c mthi v1
+[ 0-9a-f]+: 0004 2d7c mthi a0
+[ 0-9a-f]+: 001d 2d7c mthi sp
+[ 0-9a-f]+: 001e 2d7c mthi s8
+[ 0-9a-f]+: 001f 2d7c mthi ra
+[ 0-9a-f]+: 0000 3d7c mtlo zero
+[ 0-9a-f]+: 0002 3d7c mtlo v0
+[ 0-9a-f]+: 0003 3d7c mtlo v1
+[ 0-9a-f]+: 0004 3d7c mtlo a0
+[ 0-9a-f]+: 001d 3d7c mtlo sp
+[ 0-9a-f]+: 001e 3d7c mtlo s8
+[ 0-9a-f]+: 001f 3d7c mtlo ra
+[ 0-9a-f]+: 0083 1210 mul v0,v1,a0
+[ 0-9a-f]+: 03fe ea10 mul sp,s8,ra
+[ 0-9a-f]+: 0082 1210 mul v0,v0,a0
+[ 0-9a-f]+: 0082 1210 mul v0,v0,a0
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0022 8b3c mult v0,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 0022 8b3c mult v0,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0022 8b3c mult v0,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 8b3c mult v0,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 8b3c mult v0,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0083 8b3c mult v1,a0
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 0022 6c3c tne v0,at,0x6
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 3020 0004 li at,4
+[ 0-9a-f]+: 0023 8b3c mult v1,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 0022 6c3c tne v0,at,0x6
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0083 9b3c multu v1,a0
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0001 6c3c tne at,zero,0x6
+[ 0-9a-f]+: 3020 0004 li at,4
+[ 0-9a-f]+: 0023 9b3c multu v1,at
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0001 6c3c tne at,zero,0x6
+[ 0-9a-f]+: 0062 8b3c mult v0,v1
+[ 0-9a-f]+: 0062 9b3c multu v0,v1
+[ 0-9a-f]+: 0060 1190 neg v0,v1
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+[ 0-9a-f]+: 0060 11d0 negu v0,v1
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0060 11d0 negu v0,v1
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 4412 not v0,v0
+[ 0-9a-f]+: 4412 not v0,v0
+[ 0-9a-f]+: 4413 not v0,v1
+[ 0-9a-f]+: 4414 not v0,a0
+[ 0-9a-f]+: 4415 not v0,a1
+[ 0-9a-f]+: 4416 not v0,a2
+[ 0-9a-f]+: 4417 not v0,a3
+[ 0-9a-f]+: 4410 not v0,s0
+[ 0-9a-f]+: 4411 not v0,s1
+[ 0-9a-f]+: 4419 not v1,s1
+[ 0-9a-f]+: 4421 not a0,s1
+[ 0-9a-f]+: 4429 not a1,s1
+[ 0-9a-f]+: 4431 not a2,s1
+[ 0-9a-f]+: 4439 not a3,s1
+[ 0-9a-f]+: 4401 not s0,s1
+[ 0-9a-f]+: 4409 not s1,s1
+[ 0-9a-f]+: 4417 not v0,a3
+[ 0-9a-f]+: 4417 not v0,a3
+[ 0-9a-f]+: 0083 12d0 nor v0,v1,a0
+[ 0-9a-f]+: 03fe ead0 nor sp,s8,ra
+[ 0-9a-f]+: 0082 12d0 nor v0,v0,a0
+[ 0-9a-f]+: 0082 12d0 nor v0,v0,a0
+[ 0-9a-f]+: 5043 8000 ori v0,v1,0x8000
+[ 0-9a-f]+: 0002 12d0 not v0,v0
+[ 0-9a-f]+: 5043 ffff ori v0,v1,0xffff
+[ 0-9a-f]+: 0002 12d0 not v0,v0
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 44d2 or v0,v0,v0
+[ 0-9a-f]+: 44d3 or v0,v0,v1
+[ 0-9a-f]+: 44d4 or v0,v0,a0
+[ 0-9a-f]+: 44d5 or v0,v0,a1
+[ 0-9a-f]+: 44d6 or v0,v0,a2
+[ 0-9a-f]+: 44d7 or v0,v0,a3
+[ 0-9a-f]+: 44d0 or v0,v0,s0
+[ 0-9a-f]+: 44d1 or v0,v0,s1
+[ 0-9a-f]+: 44da or v1,v1,v0
+[ 0-9a-f]+: 44e2 or a0,a0,v0
+[ 0-9a-f]+: 44ea or a1,a1,v0
+[ 0-9a-f]+: 44f2 or a2,a2,v0
+[ 0-9a-f]+: 44fa or a3,a3,v0
+[ 0-9a-f]+: 44c2 or s0,s0,v0
+[ 0-9a-f]+: 44ca or s1,s1,v0
+[ 0-9a-f]+: 44d2 or v0,v0,v0
+[ 0-9a-f]+: 44d3 or v0,v0,v1
+[ 0-9a-f]+: 44d3 or v0,v0,v1
+[ 0-9a-f]+: 0083 1290 or v0,v1,a0
+[ 0-9a-f]+: 03fe ea90 or sp,s8,ra
+[ 0-9a-f]+: 0082 1290 or v0,v0,a0
+[ 0-9a-f]+: 0082 1290 or v0,v0,a0
+[ 0-9a-f]+: 5043 8000 ori v0,v1,0x8000
+[ 0-9a-f]+: 5043 ffff ori v0,v1,0xffff
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1290 or v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0023 1290 or v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1290 or v0,v1,at
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 5064 7fff ori v1,a0,0x7fff
+[ 0-9a-f]+: 5064 ffff ori v1,a0,0xffff
+[ 0-9a-f]+: 5063 ffff ori v1,v1,0xffff
+[ 0-9a-f]+: 5063 ffff ori v1,v1,0xffff
+[ 0-9a-f]+: 0040 6b3c rdhwr v0,hwr_cpunum
+[ 0-9a-f]+: 0041 6b3c rdhwr v0,hwr_synci_step
+[ 0-9a-f]+: 0042 6b3c rdhwr v0,hwr_cc
+[ 0-9a-f]+: 0043 6b3c rdhwr v0,hwr_ccres
+[ 0-9a-f]+: 0044 6b3c rdhwr v0,\$4
+[ 0-9a-f]+: 0045 6b3c rdhwr v0,\$5
+[ 0-9a-f]+: 0046 6b3c rdhwr v0,\$6
+[ 0-9a-f]+: 0047 6b3c rdhwr v0,\$7
+[ 0-9a-f]+: 0048 6b3c rdhwr v0,\$8
+[ 0-9a-f]+: 0049 6b3c rdhwr v0,\$9
+[ 0-9a-f]+: 004a 6b3c rdhwr v0,\$10
+[ 0-9a-f]+: 0043 e17c rdpgpr v0,v1
+[ 0-9a-f]+: 0042 e17c rdpgpr v0,v0
+[ 0-9a-f]+: 0042 e17c rdpgpr v0,v0
+[ 0-9a-f]+: 0062 ab3c div zero,v0,v1
+[ 0-9a-f]+: 03fe ab3c div zero,s8,ra
+[ 0-9a-f]+: 0003 703c teq v1,zero,0x7
+[ 0-9a-f]+: 0060 ab3c div zero,zero,v1
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b423 fffe bne v1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: 0020 603c teq zero,at,0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 001f 703c teq ra,zero,0x7
+[ 0-9a-f]+: 03e0 ab3c div zero,zero,ra
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b43f fffe bne ra,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: 0020 603c teq zero,at,0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0004 703c teq a0,zero,0x7
+[ 0-9a-f]+: 0083 ab3c div zero,v1,a0
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b424 fffe bne a0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: 0023 603c teq v1,at,0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4602 mfhi v0
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 0024 ab3c div zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 0062 bb3c divu zero,v0,v1
+[ 0-9a-f]+: 03fe bb3c divu zero,s8,ra
+[ 0-9a-f]+: 0003 703c teq v1,zero,0x7
+[ 0-9a-f]+: 0060 bb3c divu zero,zero,v1
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 001f 703c teq ra,zero,0x7
+[ 0-9a-f]+: 03e0 bb3c divu zero,zero,ra
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0003 bb3c divu zero,v1,zero
+[ 0-9a-f]+: 4602 mfhi v0
+[ 0-9a-f]+: 0004 703c teq a0,zero,0x7
+[ 0-9a-f]+: 0083 bb3c divu zero,v1,a0
+[ 0-9a-f]+: 4602 mfhi v0
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0024 bb3c divu zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 0024 bb3c divu zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 0080 11d0 negu v0,a0
+[ 0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ 0-9a-f]+: 0080 09d0 negu at,a0
+[ 0-9a-f]+: 0041 10d0 rorv v0,v0,at
+[ 0-9a-f]+: 0060 11d0 negu v0,v1
+[ 0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ 0-9a-f]+: 0043 00c0 ror v0,v1,0x0
+[ 0-9a-f]+: 0043 f8c0 ror v0,v1,0x1f
+[ 0-9a-f]+: 0043 08c0 ror v0,v1,0x1
+[ 0-9a-f]+: 0042 08c0 ror v0,v0,0x1
+[ 0-9a-f]+: 0042 08c0 ror v0,v0,0x1
+[ 0-9a-f]+: 0043 00c0 ror v0,v1,0x0
+[ 0-9a-f]+: 0043 08c0 ror v0,v1,0x1
+[ 0-9a-f]+: 0043 f8c0 ror v0,v1,0x1f
+[ 0-9a-f]+: 0042 f8c0 ror v0,v0,0x1f
+[ 0-9a-f]+: 0042 f8c0 ror v0,v0,0x1f
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 8830 sb zero,0\(v1\)
+[ 0-9a-f]+: 8830 sb zero,0\(v1\)
+[ 0-9a-f]+: 8831 sb zero,1\(v1\)
+[ 0-9a-f]+: 8832 sb zero,2\(v1\)
+[ 0-9a-f]+: 8833 sb zero,3\(v1\)
+[ 0-9a-f]+: 8834 sb zero,4\(v1\)
+[ 0-9a-f]+: 8835 sb zero,5\(v1\)
+[ 0-9a-f]+: 8836 sb zero,6\(v1\)
+[ 0-9a-f]+: 8837 sb zero,7\(v1\)
+[ 0-9a-f]+: 8838 sb zero,8\(v1\)
+[ 0-9a-f]+: 8839 sb zero,9\(v1\)
+[ 0-9a-f]+: 883a sb zero,10\(v1\)
+[ 0-9a-f]+: 883b sb zero,11\(v1\)
+[ 0-9a-f]+: 883c sb zero,12\(v1\)
+[ 0-9a-f]+: 883d sb zero,13\(v1\)
+[ 0-9a-f]+: 883e sb zero,14\(v1\)
+[ 0-9a-f]+: 883f sb zero,15\(v1\)
+[ 0-9a-f]+: 893f sb v0,15\(v1\)
+[ 0-9a-f]+: 89bf sb v1,15\(v1\)
+[ 0-9a-f]+: 8a3f sb a0,15\(v1\)
+[ 0-9a-f]+: 8abf sb a1,15\(v1\)
+[ 0-9a-f]+: 8b3f sb a2,15\(v1\)
+[ 0-9a-f]+: 8bbf sb a3,15\(v1\)
+[ 0-9a-f]+: 88bf sb s1,15\(v1\)
+[ 0-9a-f]+: 88cf sb s1,15\(a0\)
+[ 0-9a-f]+: 88df sb s1,15\(a1\)
+[ 0-9a-f]+: 88ef sb s1,15\(a2\)
+[ 0-9a-f]+: 88ff sb s1,15\(a3\)
+[ 0-9a-f]+: 88af sb s1,15\(v0\)
+[ 0-9a-f]+: 888f sb s1,15\(s0\)
+[ 0-9a-f]+: 889f sb s1,15\(s1\)
+[ 0-9a-f]+: 1860 0004 sb v1,4\(zero\)
+[ 0-9a-f]+: 1860 0004 sb v1,4\(zero\)
+[ 0-9a-f]+: 1860 7fff sb v1,32767\(zero\)
+[ 0-9a-f]+: 1860 8000 sb v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 1861 ffff sb v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1860 8000 sb v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 1860 8001 sb v1,-32767\(zero\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1860 ffff sb v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 1861 5678 sb v1,22136\(at\)
+[ 0-9a-f]+: 1864 0000 sb v1,0\(a0\)
+[ 0-9a-f]+: 1864 0000 sb v1,0\(a0\)
+[ 0-9a-f]+: 1864 7fff sb v1,32767\(a0\)
+[ 0-9a-f]+: 1864 8000 sb v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 ffff sb v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1864 8000 sb v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 1864 8001 sb v1,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1864 ffff sb v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 5678 sb v1,22136\(at\)
+[ 0-9a-f]+: 6060 b004 sc v1,4\(zero\)
+[ 0-9a-f]+: 6060 b004 sc v1,4\(zero\)
+[ 0-9a-f]+: 6060 b7ff sc v1,2047\(zero\)
+[ 0-9a-f]+: 6060 b800 sc v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 bfff sc v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 bfff sc v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 6060 bfff sc v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 b678 sc v1,1656\(at\)
+[ 0-9a-f]+: 6064 b000 sc v1,0\(a0\)
+[ 0-9a-f]+: 6064 b000 sc v1,0\(a0\)
+[ 0-9a-f]+: 6064 b7ff sc v1,2047\(a0\)
+[ 0-9a-f]+: 6064 b800 sc v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 bfff sc v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 bfff sc v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 6064 bfff sc v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b678 sc v1,1656\(at\)
+[ 0-9a-f]+: 46c0 sdbbp
+[ 0-9a-f]+: 46c0 sdbbp
+[ 0-9a-f]+: 46c1 sdbbp 0x1
+[ 0-9a-f]+: 46c2 sdbbp 0x2
+[ 0-9a-f]+: 46c3 sdbbp 0x3
+[ 0-9a-f]+: 46c4 sdbbp 0x4
+[ 0-9a-f]+: 46c5 sdbbp 0x5
+[ 0-9a-f]+: 46c6 sdbbp 0x6
+[ 0-9a-f]+: 46c7 sdbbp 0x7
+[ 0-9a-f]+: 46c8 sdbbp 0x8
+[ 0-9a-f]+: 46c9 sdbbp 0x9
+[ 0-9a-f]+: 46ca sdbbp 0xa
+[ 0-9a-f]+: 46cb sdbbp 0xb
+[ 0-9a-f]+: 46cc sdbbp 0xc
+[ 0-9a-f]+: 46cd sdbbp 0xd
+[ 0-9a-f]+: 46ce sdbbp 0xe
+[ 0-9a-f]+: 46cf sdbbp 0xf
+[ 0-9a-f]+: 0000 db7c sdbbp
+[ 0-9a-f]+: 0000 db7c sdbbp
+[ 0-9a-f]+: 0001 db7c sdbbp 0x1
+[ 0-9a-f]+: 0002 db7c sdbbp 0x2
+[ 0-9a-f]+: 00ff db7c sdbbp 0xff
+[ 0-9a-f]+: 0043 2b3c seb v0,v1
+[ 0-9a-f]+: 0042 2b3c seb v0,v0
+[ 0-9a-f]+: 0042 2b3c seb v0,v0
+[ 0-9a-f]+: 0043 3b3c seh v0,v1
+[ 0-9a-f]+: 0042 3b3c seh v0,v0
+[ 0-9a-f]+: 0042 3b3c seh v0,v0
+[ 0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: b043 0001 sltiu v0,v1,1
+[ 0-9a-f]+: b044 0001 sltiu v0,a0,1
+[ 0-9a-f]+: b043 0001 sltiu v0,v1,1
+[ 0-9a-f]+: 7043 0001 xori v0,v1,0x1
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: 3043 0001 addiu v0,v1,1
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: 0083 1350 slt v0,v1,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 8000 slti v0,v1,-32768
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 7fff slti v0,v1,32767
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0083 1390 sltu v0,v1,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 8000 sltiu v0,v1,-32768
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 7fff sltiu v0,v1,32767
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0064 1350 slt v0,a0,v1
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 0064 1390 sltu v0,a0,v1
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: a930 sh v0,0\(v1\)
+[ 0-9a-f]+: a930 sh v0,0\(v1\)
+[ 0-9a-f]+: a931 sh v0,2\(v1\)
+[ 0-9a-f]+: a932 sh v0,4\(v1\)
+[ 0-9a-f]+: a933 sh v0,6\(v1\)
+[ 0-9a-f]+: a934 sh v0,8\(v1\)
+[ 0-9a-f]+: a935 sh v0,10\(v1\)
+[ 0-9a-f]+: a936 sh v0,12\(v1\)
+[ 0-9a-f]+: a937 sh v0,14\(v1\)
+[ 0-9a-f]+: a938 sh v0,16\(v1\)
+[ 0-9a-f]+: a939 sh v0,18\(v1\)
+[ 0-9a-f]+: a93a sh v0,20\(v1\)
+[ 0-9a-f]+: a93b sh v0,22\(v1\)
+[ 0-9a-f]+: a93c sh v0,24\(v1\)
+[ 0-9a-f]+: a93d sh v0,26\(v1\)
+[ 0-9a-f]+: a93e sh v0,28\(v1\)
+[ 0-9a-f]+: a93f sh v0,30\(v1\)
+[ 0-9a-f]+: a94f sh v0,30\(a0\)
+[ 0-9a-f]+: a95f sh v0,30\(a1\)
+[ 0-9a-f]+: a96f sh v0,30\(a2\)
+[ 0-9a-f]+: a97f sh v0,30\(a3\)
+[ 0-9a-f]+: a92f sh v0,30\(v0\)
+[ 0-9a-f]+: a90f sh v0,30\(s0\)
+[ 0-9a-f]+: a91f sh v0,30\(s1\)
+[ 0-9a-f]+: a99f sh v1,30\(s1\)
+[ 0-9a-f]+: aa1f sh a0,30\(s1\)
+[ 0-9a-f]+: aa9f sh a1,30\(s1\)
+[ 0-9a-f]+: ab1f sh a2,30\(s1\)
+[ 0-9a-f]+: ab9f sh a3,30\(s1\)
+[ 0-9a-f]+: a89f sh s1,30\(s1\)
+[ 0-9a-f]+: a81f sh zero,30\(s1\)
+[ 0-9a-f]+: 3860 0004 sh v1,4\(zero\)
+[ 0-9a-f]+: 3860 0004 sh v1,4\(zero\)
+[ 0-9a-f]+: 3860 7fff sh v1,32767\(zero\)
+[ 0-9a-f]+: 3860 8000 sh v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 3861 ffff sh v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3860 8000 sh v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 3861 0001 sh v1,1\(at\)
+[ 0-9a-f]+: 3860 8001 sh v1,-32767\(zero\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3860 ffff sh v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 3861 5678 sh v1,22136\(at\)
+[ 0-9a-f]+: 3864 0000 sh v1,0\(a0\)
+[ 0-9a-f]+: 3864 0000 sh v1,0\(a0\)
+[ 0-9a-f]+: 3864 7fff sh v1,32767\(a0\)
+[ 0-9a-f]+: 3864 8000 sh v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 ffff sh v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3864 8000 sh v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 0001 sh v1,1\(at\)
+[ 0-9a-f]+: 3864 8001 sh v1,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3864 ffff sh v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 5678 sh v1,22136\(at\)
+[ 0-9a-f]+: 0064 1350 slt v0,a0,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0064 1390 sltu v0,a0,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 2522 sll v0,v0,1
+[ 0-9a-f]+: 2524 sll v0,v0,2
+[ 0-9a-f]+: 2526 sll v0,v0,3
+[ 0-9a-f]+: 2528 sll v0,v0,4
+[ 0-9a-f]+: 252a sll v0,v0,5
+[ 0-9a-f]+: 252c sll v0,v0,6
+[ 0-9a-f]+: 252e sll v0,v0,7
+[ 0-9a-f]+: 2520 sll v0,v0,8
+[ 0-9a-f]+: 2530 sll v0,v1,8
+[ 0-9a-f]+: 2540 sll v0,a0,8
+[ 0-9a-f]+: 2550 sll v0,a1,8
+[ 0-9a-f]+: 2560 sll v0,a2,8
+[ 0-9a-f]+: 2570 sll v0,a3,8
+[ 0-9a-f]+: 2500 sll v0,s0,8
+[ 0-9a-f]+: 2510 sll v0,s1,8
+[ 0-9a-f]+: 25a0 sll v1,v0,8
+[ 0-9a-f]+: 2620 sll a0,v0,8
+[ 0-9a-f]+: 26a0 sll a1,v0,8
+[ 0-9a-f]+: 2720 sll a2,v0,8
+[ 0-9a-f]+: 27a0 sll a3,v0,8
+[ 0-9a-f]+: 2420 sll s0,v0,8
+[ 0-9a-f]+: 24a0 sll s1,v0,8
+[ 0-9a-f]+: 2522 sll v0,v0,1
+[ 0-9a-f]+: 25b2 sll v1,v1,1
+[ 0-9a-f]+: 0064 1010 sllv v0,v1,a0
+[ 0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ 0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ 0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ 0-9a-f]+: 0044 0000 sll v0,a0,0x0
+[ 0-9a-f]+: 0044 0800 sll v0,a0,0x1
+[ 0-9a-f]+: 0044 f800 sll v0,a0,0x1f
+[ 0-9a-f]+: 0042 f800 sll v0,v0,0x1f
+[ 0-9a-f]+: 0042 f800 sll v0,v0,0x1f
+[ 0-9a-f]+: 0083 1350 slt v0,v1,a0
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 9043 8000 slti v0,v1,-32768
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 9043 7fff slti v0,v1,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 9064 8000 slti v1,a0,-32768
+[ 0-9a-f]+: 9064 0000 slti v1,a0,0
+[ 0-9a-f]+: 9064 7fff slti v1,a0,32767
+[ 0-9a-f]+: 9064 ffff slti v1,a0,-1
+[ 0-9a-f]+: 9063 ffff slti v1,v1,-1
+[ 0-9a-f]+: 9063 ffff slti v1,v1,-1
+[ 0-9a-f]+: b064 8000 sltiu v1,a0,-32768
+[ 0-9a-f]+: b064 0000 sltiu v1,a0,0
+[ 0-9a-f]+: b064 7fff sltiu v1,a0,32767
+[ 0-9a-f]+: b064 ffff sltiu v1,a0,-1
+[ 0-9a-f]+: b063 ffff sltiu v1,v1,-1
+[ 0-9a-f]+: b063 ffff sltiu v1,v1,-1
+[ 0-9a-f]+: 0083 1390 sltu v0,v1,a0
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: b043 8000 sltiu v0,v1,-32768
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: b043 7fff sltiu v0,v1,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 0080 1390 sltu v0,zero,a0
+[ 0-9a-f]+: 0060 1390 sltu v0,zero,v1
+[ 0-9a-f]+: 0060 1390 sltu v0,zero,v1
+[ 0-9a-f]+: 7043 0001 xori v0,v1,0x1
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 3043 0001 addiu v0,v1,1
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 0064 1090 srav v0,v1,a0
+[ 0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ 0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ 0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ 0-9a-f]+: 0044 0080 sra v0,a0,0x0
+[ 0-9a-f]+: 0044 0880 sra v0,a0,0x1
+[ 0-9a-f]+: 0044 f880 sra v0,a0,0x1f
+[ 0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ 0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ 0-9a-f]+: 0064 1050 srlv v0,v1,a0
+[ 0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ 0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ 0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ 0-9a-f]+: 0044 0040 srl v0,a0,0x0
+[ 0-9a-f]+: 2543 srl v0,a0,1
+[ 0-9a-f]+: 0044 f840 srl v0,a0,0x1f
+[ 0-9a-f]+: 0042 f840 srl v0,v0,0x1f
+[ 0-9a-f]+: 0042 f840 srl v0,v0,0x1f
+[ 0-9a-f]+: 2523 srl v0,v0,1
+[ 0-9a-f]+: 2525 srl v0,v0,2
+[ 0-9a-f]+: 2527 srl v0,v0,3
+[ 0-9a-f]+: 2529 srl v0,v0,4
+[ 0-9a-f]+: 252b srl v0,v0,5
+[ 0-9a-f]+: 252d srl v0,v0,6
+[ 0-9a-f]+: 252f srl v0,v0,7
+[ 0-9a-f]+: 2521 srl v0,v0,8
+[ 0-9a-f]+: 2531 srl v0,v1,8
+[ 0-9a-f]+: 2541 srl v0,a0,8
+[ 0-9a-f]+: 2551 srl v0,a1,8
+[ 0-9a-f]+: 2561 srl v0,a2,8
+[ 0-9a-f]+: 2571 srl v0,a3,8
+[ 0-9a-f]+: 2501 srl v0,s0,8
+[ 0-9a-f]+: 2511 srl v0,s1,8
+[ 0-9a-f]+: 2521 srl v0,v0,8
+[ 0-9a-f]+: 25a1 srl v1,v0,8
+[ 0-9a-f]+: 2621 srl a0,v0,8
+[ 0-9a-f]+: 26a1 srl a1,v0,8
+[ 0-9a-f]+: 2721 srl a2,v0,8
+[ 0-9a-f]+: 27a1 srl a3,v0,8
+[ 0-9a-f]+: 2421 srl s0,v0,8
+[ 0-9a-f]+: 24a1 srl s1,v0,8
+[ 0-9a-f]+: 25b3 srl v1,v1,1
+[ 0-9a-f]+: 25b3 srl v1,v1,1
+[ 0-9a-f]+: 0083 1190 sub v0,v1,a0
+[ 0-9a-f]+: 03fe e990 sub sp,s8,ra
+[ 0-9a-f]+: 0082 1190 sub v0,v0,a0
+[ 0-9a-f]+: 0082 1190 sub v0,v0,a0
+[ 0-9a-f]+: 1042 0000 addi v0,v0,0
+[ 0-9a-f]+: 1042 ffff addi v0,v0,-1
+[ 0-9a-f]+: 1042 8001 addi v0,v0,-32767
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 1190 sub v0,v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 1190 sub v0,v0,at
+[ 0-9a-f]+: 0527 subu v0,v1,v0
+[ 0-9a-f]+: 0537 subu v0,v1,v1
+[ 0-9a-f]+: 0547 subu v0,v1,a0
+[ 0-9a-f]+: 0557 subu v0,v1,a1
+[ 0-9a-f]+: 0567 subu v0,v1,a2
+[ 0-9a-f]+: 0577 subu v0,v1,a3
+[ 0-9a-f]+: 0507 subu v0,v1,s0
+[ 0-9a-f]+: 0517 subu v0,v1,s1
+[ 0-9a-f]+: 0515 subu v0,v0,s1
+[ 0-9a-f]+: 0519 subu v0,a0,s1
+[ 0-9a-f]+: 051b subu v0,a1,s1
+[ 0-9a-f]+: 051d subu v0,a2,s1
+[ 0-9a-f]+: 051f subu v0,a3,s1
+[ 0-9a-f]+: 0511 subu v0,s0,s1
+[ 0-9a-f]+: 0513 subu v0,s1,s1
+[ 0-9a-f]+: 0515 subu v0,v0,s1
+[ 0-9a-f]+: 0595 subu v1,v0,s1
+[ 0-9a-f]+: 0615 subu a0,v0,s1
+[ 0-9a-f]+: 0695 subu a1,v0,s1
+[ 0-9a-f]+: 0715 subu a2,v0,s1
+[ 0-9a-f]+: 0795 subu a3,v0,s1
+[ 0-9a-f]+: 0415 subu s0,v0,s1
+[ 0-9a-f]+: 0495 subu s1,v0,s1
+[ 0-9a-f]+: 07af subu a3,a3,v0
+[ 0-9a-f]+: 07af subu a3,a3,v0
+[ 0-9a-f]+: 0083 11d0 subu v0,v1,a0
+[ 0-9a-f]+: 03fe e9d0 subu sp,s8,ra
+[ 0-9a-f]+: 0082 11d0 subu v0,v0,a0
+[ 0-9a-f]+: 0082 11d0 subu v0,v0,a0
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ 0-9a-f]+: 3042 ffff addiu v0,v0,-1
+[ 0-9a-f]+: 3042 8001 addiu v0,v0,-32767
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 11d0 subu v0,v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 11d0 subu v0,v0,at
+[ 0-9a-f]+: e940 sw v0,0\(a0\)
+[ 0-9a-f]+: e940 sw v0,0\(a0\)
+[ 0-9a-f]+: e941 sw v0,4\(a0\)
+[ 0-9a-f]+: e942 sw v0,8\(a0\)
+[ 0-9a-f]+: e943 sw v0,12\(a0\)
+[ 0-9a-f]+: e944 sw v0,16\(a0\)
+[ 0-9a-f]+: e945 sw v0,20\(a0\)
+[ 0-9a-f]+: e946 sw v0,24\(a0\)
+[ 0-9a-f]+: e947 sw v0,28\(a0\)
+[ 0-9a-f]+: e948 sw v0,32\(a0\)
+[ 0-9a-f]+: e949 sw v0,36\(a0\)
+[ 0-9a-f]+: e94a sw v0,40\(a0\)
+[ 0-9a-f]+: e94b sw v0,44\(a0\)
+[ 0-9a-f]+: e94c sw v0,48\(a0\)
+[ 0-9a-f]+: e94d sw v0,52\(a0\)
+[ 0-9a-f]+: e94e sw v0,56\(a0\)
+[ 0-9a-f]+: e94f sw v0,60\(a0\)
+[ 0-9a-f]+: e95f sw v0,60\(a1\)
+[ 0-9a-f]+: e96f sw v0,60\(a2\)
+[ 0-9a-f]+: e97f sw v0,60\(a3\)
+[ 0-9a-f]+: e90f sw v0,60\(s0\)
+[ 0-9a-f]+: e91f sw v0,60\(s1\)
+[ 0-9a-f]+: e92f sw v0,60\(v0\)
+[ 0-9a-f]+: e93f sw v0,60\(v1\)
+[ 0-9a-f]+: e9bf sw v1,60\(v1\)
+[ 0-9a-f]+: ea3f sw a0,60\(v1\)
+[ 0-9a-f]+: eabf sw a1,60\(v1\)
+[ 0-9a-f]+: eb3f sw a2,60\(v1\)
+[ 0-9a-f]+: ebbf sw a3,60\(v1\)
+[ 0-9a-f]+: e8bf sw s1,60\(v1\)
+[ 0-9a-f]+: e83f sw zero,60\(v1\)
+[ 0-9a-f]+: c800 sw zero,0\(sp\)
+[ 0-9a-f]+: c800 sw zero,0\(sp\)
+[ 0-9a-f]+: c801 sw zero,4\(sp\)
+[ 0-9a-f]+: c802 sw zero,8\(sp\)
+[ 0-9a-f]+: c803 sw zero,12\(sp\)
+[ 0-9a-f]+: c804 sw zero,16\(sp\)
+[ 0-9a-f]+: c805 sw zero,20\(sp\)
+[ 0-9a-f]+: c81e sw zero,120\(sp\)
+[ 0-9a-f]+: c81f sw zero,124\(sp\)
+[ 0-9a-f]+: c85f sw v0,124\(sp\)
+[ 0-9a-f]+: ca3f sw s1,124\(sp\)
+[ 0-9a-f]+: c87f sw v1,124\(sp\)
+[ 0-9a-f]+: c89f sw a0,124\(sp\)
+[ 0-9a-f]+: c8bf sw a1,124\(sp\)
+[ 0-9a-f]+: c8df sw a2,124\(sp\)
+[ 0-9a-f]+: c8ff sw a3,124\(sp\)
+[ 0-9a-f]+: cbff sw ra,124\(sp\)
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f860 7fff sw v1,32767\(zero\)
+[ 0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f860 8001 sw v1,-32767\(zero\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f860 ffff sw v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f864 7fff sw v1,32767\(a0\)
+[ 0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f864 8001 sw v1,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f864 ffff sw v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 87ff swl v1,2047\(zero\)
+[ 0-9a-f]+: 6060 8800 swl v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6060 8fff swl v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 8678 swl v1,1656\(at\)
+[ 0-9a-f]+: 6064 8000 swl v1,0\(a0\)
+[ 0-9a-f]+: 6064 8000 swl v1,0\(a0\)
+[ 0-9a-f]+: 6064 87ff swl v1,2047\(a0\)
+[ 0-9a-f]+: 6064 8800 swl v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6064 8fff swl v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8678 swl v1,1656\(at\)
+[ 0-9a-f]+: 6060 9004 swr v1,4\(zero\)
+[ 0-9a-f]+: 6060 9004 swr v1,4\(zero\)
+[ 0-9a-f]+: 6060 97ff swr v1,2047\(zero\)
+[ 0-9a-f]+: 6060 9800 swr v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 6060 9fff swr v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 9678 swr v1,1656\(at\)
+[ 0-9a-f]+: 6064 9000 swr v1,0\(a0\)
+[ 0-9a-f]+: 6064 9000 swr v1,0\(a0\)
+[ 0-9a-f]+: 6064 97ff swr v1,2047\(a0\)
+[ 0-9a-f]+: 6064 9800 swr v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 6064 9fff swr v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9678 swr v1,1656\(at\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 87ff swl v1,2047\(zero\)
+[ 0-9a-f]+: 6060 8800 swl v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6060 8fff swl v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 8678 swl v1,1656\(at\)
+[ 0-9a-f]+: 6064 8000 swl v1,0\(a0\)
+[ 0-9a-f]+: 6064 8000 swl v1,0\(a0\)
+[ 0-9a-f]+: 6064 87ff swl v1,2047\(a0\)
+[ 0-9a-f]+: 6064 8800 swl v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6064 8fff swl v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8678 swl v1,1656\(at\)
+[ 0-9a-f]+: 6060 9004 swr v1,4\(zero\)
+[ 0-9a-f]+: 6060 9004 swr v1,4\(zero\)
+[ 0-9a-f]+: 6060 97ff swr v1,2047\(zero\)
+[ 0-9a-f]+: 6060 9800 swr v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 6060 9fff swr v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 9678 swr v1,1656\(at\)
+[ 0-9a-f]+: 6064 9000 swr v1,0\(a0\)
+[ 0-9a-f]+: 6064 9000 swr v1,0\(a0\)
+[ 0-9a-f]+: 6064 97ff swr v1,2047\(a0\)
+[ 0-9a-f]+: 6064 9800 swr v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 6064 9fff swr v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9678 swr v1,1656\(at\)
+[ 0-9a-f]+: 454c swm s0,ra,48\(sp\)
+[ 0-9a-f]+: 455c swm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 455c swm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 456c swm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 456c swm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 457c swm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 457c swm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 4540 swm s0,ra,0\(sp\)
+[ 0-9a-f]+: 4540 swm s0,ra,0\(sp\)
+[ 0-9a-f]+: 4541 swm s0,ra,4\(sp\)
+[ 0-9a-f]+: 4542 swm s0,ra,8\(sp\)
+[ 0-9a-f]+: 4543 swm s0,ra,12\(sp\)
+[ 0-9a-f]+: 4544 swm s0,ra,16\(sp\)
+[ 0-9a-f]+: 4545 swm s0,ra,20\(sp\)
+[ 0-9a-f]+: 4546 swm s0,ra,24\(sp\)
+[ 0-9a-f]+: 4547 swm s0,ra,28\(sp\)
+[ 0-9a-f]+: 4548 swm s0,ra,32\(sp\)
+[ 0-9a-f]+: 4549 swm s0,ra,36\(sp\)
+[ 0-9a-f]+: 454a swm s0,ra,40\(sp\)
+[ 0-9a-f]+: 454b swm s0,ra,44\(sp\)
+[ 0-9a-f]+: 454c swm s0,ra,48\(sp\)
+[ 0-9a-f]+: 454d swm s0,ra,52\(sp\)
+[ 0-9a-f]+: 454e swm s0,ra,56\(sp\)
+[ 0-9a-f]+: 454f swm s0,ra,60\(sp\)
+[ 0-9a-f]+: 2020 d000 swm s0,0\(zero\)
+[ 0-9a-f]+: 2020 d004 swm s0,4\(zero\)
+[ 0-9a-f]+: 2020 d7ff swm s0,2047\(zero\)
+[ 0-9a-f]+: 2020 d800 swm s0,-2048\(zero\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 2021 d800 swm s0,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 2021 d7ff swm s0,2047\(at\)
+[ 0-9a-f]+: 2025 d000 swm s0,0\(a1\)
+[ 0-9a-f]+: 2025 d7ff swm s0,2047\(a1\)
+[ 0-9a-f]+: 2025 d800 swm s0,-2048\(a1\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 00a1 0950 addu at,at,a1
+[ 0-9a-f]+: 2021 d800 swm s0,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 00a1 0950 addu at,at,a1
+[ 0-9a-f]+: 2021 d7ff swm s0,2047\(at\)
+[ 0-9a-f]+: 2045 d7ff swm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 d7ff swm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 d7ff swm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 d7ff swm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 d7ff swm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 d7ff swm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 d7ff swm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 d7ff swm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 d7ff swm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 d000 swm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 d000 swm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 d000 swm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 d000 swm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 d000 swm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 d000 swm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 d000 swm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 d000 swm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 d000 swm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 dfff swm s0,-1\(at\)
+[ 0-9a-f]+: 203d d000 swm s0,0\(sp\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 dfff swm s0,-1\(at\)
+[ 0-9a-f]+: 2040 9000 swp v0,0\(zero\)
+[ 0-9a-f]+: 2040 9004 swp v0,4\(zero\)
+[ 0-9a-f]+: 2040 97ff swp v0,2047\(zero\)
+[ 0-9a-f]+: 2040 9800 swp v0,-2048\(zero\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 2041 9800 swp v0,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 2041 97ff swp v0,2047\(at\)
+[ 0-9a-f]+: 205d 9000 swp v0,0\(sp\)
+[ 0-9a-f]+: 205d 9000 swp v0,0\(sp\)
+[ 0-9a-f]+: 2043 97ff swp v0,2047\(v1\)
+[ 0-9a-f]+: 2043 9800 swp v0,-2048\(v1\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 9800 swp v0,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 97ff swp v0,2047\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 9fff swp v0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 2043 9000 swp v0,0\(v1\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 9fff swp v0,-1\(at\)
+[ 0-9a-f]+: 0000 6b7c sync
+[ 0-9a-f]+: 0000 6b7c sync
+[ 0-9a-f]+: 0001 6b7c sync 0x1
+[ 0-9a-f]+: 0002 6b7c sync 0x2
+[ 0-9a-f]+: 0003 6b7c sync 0x3
+[ 0-9a-f]+: 0004 6b7c sync_wmb
+[ 0-9a-f]+: 001e 6b7c sync 0x1e
+[ 0-9a-f]+: 001f 6b7c sync 0x1f
+[ 0-9a-f]+: 4200 0000 synci 0\(zero\)
+[ 0-9a-f]+: 4200 0000 synci 0\(zero\)
+[ 0-9a-f]+: 4200 0000 synci 0\(zero\)
+[ 0-9a-f]+: 4200 07ff synci 2047\(zero\)
+[ 0-9a-f]+: 4200 f800 synci -2048\(zero\)
+[ 0-9a-f]+: 4200 0800 synci 2048\(zero\)
+[ 0-9a-f]+: 4200 f7ff synci -2049\(zero\)
+[ 0-9a-f]+: 4200 7fff synci 32767\(zero\)
+[ 0-9a-f]+: 4200 8000 synci -32768\(zero\)
+[ 0-9a-f]+: 4202 0000 synci 0\(v0\)
+[ 0-9a-f]+: 4203 0000 synci 0\(v1\)
+[ 0-9a-f]+: 4203 07ff synci 2047\(v1\)
+[ 0-9a-f]+: 4203 f800 synci -2048\(v1\)
+[ 0-9a-f]+: 4203 0800 synci 2048\(v1\)
+[ 0-9a-f]+: 4203 f7ff synci -2049\(v1\)
+[ 0-9a-f]+: 4203 7fff synci 32767\(v1\)
+[ 0-9a-f]+: 4203 8000 synci -32768\(v1\)
+[ 0-9a-f]+: 0000 8b7c syscall
+[ 0-9a-f]+: 0000 8b7c syscall
+[ 0-9a-f]+: 0001 8b7c syscall 0x1
+[ 0-9a-f]+: 0002 8b7c syscall 0x2
+[ 0-9a-f]+: 00ff 8b7c syscall 0xff
+[ 0-9a-f]+: 41c2 0000 teqi v0,0
+[ 0-9a-f]+: 41c2 8000 teqi v0,-32768
+[ 0-9a-f]+: 41c2 7fff teqi v0,32767
+[ 0-9a-f]+: 41c2 ffff teqi v0,-1
+[ 0-9a-f]+: 0062 003c teq v0,v1
+[ 0-9a-f]+: 0043 003c teq v1,v0
+[ 0-9a-f]+: 0062 003c teq v0,v1
+[ 0-9a-f]+: 0062 103c teq v0,v1,0x1
+[ 0-9a-f]+: 0062 f03c teq v0,v1,0xf
+[ 0-9a-f]+: 41c2 0000 teqi v0,0
+[ 0-9a-f]+: 41c2 8000 teqi v0,-32768
+[ 0-9a-f]+: 41c2 7fff teqi v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 003c teq v0,at
+[ 0-9a-f]+: 4122 0000 tgei v0,0
+[ 0-9a-f]+: 4122 8000 tgei v0,-32768
+[ 0-9a-f]+: 4122 7fff tgei v0,32767
+[ 0-9a-f]+: 4122 ffff tgei v0,-1
+[ 0-9a-f]+: 0062 023c tge v0,v1
+[ 0-9a-f]+: 0043 023c tge v1,v0
+[ 0-9a-f]+: 0062 023c tge v0,v1
+[ 0-9a-f]+: 0062 123c tge v0,v1,0x1
+[ 0-9a-f]+: 0062 f23c tge v0,v1,0xf
+[ 0-9a-f]+: 4122 0000 tgei v0,0
+[ 0-9a-f]+: 4122 8000 tgei v0,-32768
+[ 0-9a-f]+: 4122 7fff tgei v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 023c tge v0,at
+[ 0-9a-f]+: 4162 0000 tgeiu v0,0
+[ 0-9a-f]+: 4162 8000 tgeiu v0,-32768
+[ 0-9a-f]+: 4162 7fff tgeiu v0,32767
+[ 0-9a-f]+: 4162 ffff tgeiu v0,-1
+[ 0-9a-f]+: 0062 043c tgeu v0,v1
+[ 0-9a-f]+: 0043 043c tgeu v1,v0
+[ 0-9a-f]+: 0062 043c tgeu v0,v1
+[ 0-9a-f]+: 0062 143c tgeu v0,v1,0x1
+[ 0-9a-f]+: 0062 f43c tgeu v0,v1,0xf
+[ 0-9a-f]+: 4162 0000 tgeiu v0,0
+[ 0-9a-f]+: 4162 8000 tgeiu v0,-32768
+[ 0-9a-f]+: 4162 7fff tgeiu v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 043c tgeu v0,at
+[ 0-9a-f]+: 0000 037c tlbp
+[ 0-9a-f]+: 0000 137c tlbr
+[ 0-9a-f]+: 0000 237c tlbwi
+[ 0-9a-f]+: 0000 337c tlbwr
+[ 0-9a-f]+: 4102 0000 tlti v0,0
+[ 0-9a-f]+: 4102 8000 tlti v0,-32768
+[ 0-9a-f]+: 4102 7fff tlti v0,32767
+[ 0-9a-f]+: 4102 ffff tlti v0,-1
+[ 0-9a-f]+: 0062 083c tlt v0,v1
+[ 0-9a-f]+: 0043 083c tlt v1,v0
+[ 0-9a-f]+: 0062 083c tlt v0,v1
+[ 0-9a-f]+: 0062 183c tlt v0,v1,0x1
+[ 0-9a-f]+: 0062 f83c tlt v0,v1,0xf
+[ 0-9a-f]+: 4102 0000 tlti v0,0
+[ 0-9a-f]+: 4102 8000 tlti v0,-32768
+[ 0-9a-f]+: 4102 7fff tlti v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 083c tlt v0,at
+[ 0-9a-f]+: 4142 0000 tltiu v0,0
+[ 0-9a-f]+: 4142 8000 tltiu v0,-32768
+[ 0-9a-f]+: 4142 7fff tltiu v0,32767
+[ 0-9a-f]+: 4142 ffff tltiu v0,-1
+[ 0-9a-f]+: 0062 0a3c tltu v0,v1
+[ 0-9a-f]+: 0043 0a3c tltu v1,v0
+[ 0-9a-f]+: 0062 0a3c tltu v0,v1
+[ 0-9a-f]+: 0062 1a3c tltu v0,v1,0x1
+[ 0-9a-f]+: 0062 fa3c tltu v0,v1,0xf
+[ 0-9a-f]+: 4142 0000 tltiu v0,0
+[ 0-9a-f]+: 4142 8000 tltiu v0,-32768
+[ 0-9a-f]+: 4142 7fff tltiu v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 4182 0000 tnei v0,0
+[ 0-9a-f]+: 4182 8000 tnei v0,-32768
+[ 0-9a-f]+: 4182 7fff tnei v0,32767
+[ 0-9a-f]+: 4182 ffff tnei v0,-1
+[ 0-9a-f]+: 0062 0c3c tne v0,v1
+[ 0-9a-f]+: 0043 0c3c tne v1,v0
+[ 0-9a-f]+: 0062 0c3c tne v0,v1
+[ 0-9a-f]+: 0062 1c3c tne v0,v1,0x1
+[ 0-9a-f]+: 0062 fc3c tne v0,v1,0xf
+[ 0-9a-f]+: 4182 0000 tnei v0,0
+[ 0-9a-f]+: 4182 8000 tnei v0,-32768
+[ 0-9a-f]+: 4182 7fff tnei v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 1c20 0004 lb at,4\(zero\)
+[ 0-9a-f]+: 1460 0005 lbu v1,5\(zero\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1c20 0004 lb at,4\(zero\)
+[ 0-9a-f]+: 1460 0005 lbu v1,5\(zero\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1c24 0000 lb at,0\(a0\)
+[ 0-9a-f]+: 1464 0001 lbu v1,1\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1c24 0000 lb at,0\(a0\)
+[ 0-9a-f]+: 1464 0001 lbu v1,1\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1c24 7ffb lb at,32763\(a0\)
+[ 0-9a-f]+: 1464 7ffc lbu v1,32764\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1c24 8000 lb at,-32768\(a0\)
+[ 0-9a-f]+: 1464 8001 lbu v1,-32767\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1420 0004 lbu at,4\(zero\)
+[ 0-9a-f]+: 1460 0005 lbu v1,5\(zero\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1420 0004 lbu at,4\(zero\)
+[ 0-9a-f]+: 1460 0005 lbu v1,5\(zero\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1424 0000 lbu at,0\(a0\)
+[ 0-9a-f]+: 1464 0001 lbu v1,1\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1424 0000 lbu at,0\(a0\)
+[ 0-9a-f]+: 1464 0001 lbu v1,1\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1424 7ffb lbu at,32763\(a0\)
+[ 0-9a-f]+: 1464 7ffc lbu v1,32764\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1424 8000 lbu at,-32768\(a0\)
+[ 0-9a-f]+: 1464 8001 lbu v1,-32767\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 1003 lwr v1,3\(zero\)
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 1003 lwr v1,3\(zero\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 1007 lwr v1,7\(zero\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 1007 lwr v1,7\(zero\)
+[ 0-9a-f]+: 3020 07ff li at,2047
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 6060 0800 lwl v1,-2048\(zero\)
+[ 0-9a-f]+: 6060 1803 lwr v1,-2045\(zero\)
+[ 0-9a-f]+: 3020 0800 li at,2048
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 f7ff li at,-2049
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 7ffb li at,32763
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 6064 0000 lwl v1,0\(a0\)
+[ 0-9a-f]+: 6064 1003 lwr v1,3\(a0\)
+[ 0-9a-f]+: 6064 0004 lwl v1,4\(a0\)
+[ 0-9a-f]+: 6064 1007 lwr v1,7\(a0\)
+[ 0-9a-f]+: 3024 07ff addiu at,a0,2047
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 6064 0800 lwl v1,-2048\(a0\)
+[ 0-9a-f]+: 6064 1803 lwr v1,-2045\(a0\)
+[ 0-9a-f]+: 3024 0800 addiu at,a0,2048
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3024 f7ff addiu at,a0,-2049
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3024 7ffb addiu at,a0,32763
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 1860 0005 sb v1,5\(zero\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1820 0004 sb at,4\(zero\)
+[ 0-9a-f]+: 1860 0005 sb v1,5\(zero\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1820 0004 sb at,4\(zero\)
+[ 0-9a-f]+: 1864 0001 sb v1,1\(a0\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1824 0000 sb at,0\(a0\)
+[ 0-9a-f]+: 1864 0001 sb v1,1\(a0\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1824 0000 sb at,0\(a0\)
+[ 0-9a-f]+: 1864 7ffc sb v1,32764\(a0\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1824 7ffb sb at,32763\(a0\)
+[ 0-9a-f]+: 1864 8001 sb v1,-32767\(a0\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1824 8000 sb at,-32768\(a0\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 6060 8000 swl v1,0\(zero\)
+[ 0-9a-f]+: 6060 9003 swr v1,3\(zero\)
+[ 0-9a-f]+: 6060 8000 swl v1,0\(zero\)
+[ 0-9a-f]+: 6060 9003 swr v1,3\(zero\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 9007 swr v1,7\(zero\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 9007 swr v1,7\(zero\)
+[ 0-9a-f]+: 3020 07ff li at,2047
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 6060 8800 swl v1,-2048\(zero\)
+[ 0-9a-f]+: 6060 9803 swr v1,-2045\(zero\)
+[ 0-9a-f]+: 3020 0800 li at,2048
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 f7ff li at,-2049
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 7ffb li at,32763
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 6064 8000 swl v1,0\(a0\)
+[ 0-9a-f]+: 6064 9003 swr v1,3\(a0\)
+[ 0-9a-f]+: 6064 8004 swl v1,4\(a0\)
+[ 0-9a-f]+: 6064 9007 swr v1,7\(a0\)
+[ 0-9a-f]+: 3024 07ff addiu at,a0,2047
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 6064 8800 swl v1,-2048\(a0\)
+[ 0-9a-f]+: 6064 9803 swr v1,-2045\(a0\)
+[ 0-9a-f]+: 3024 0800 addiu at,a0,2048
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3024 f7ff addiu at,a0,-2049
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3024 7ffb addiu at,a0,32763
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 0000 937c wait
+[ 0-9a-f]+: 0000 937c wait
+[ 0-9a-f]+: 0001 937c wait 0x1
+[ 0-9a-f]+: 00ff 937c wait 0xff
+[ 0-9a-f]+: 0043 f17c wrpgpr v0,v1
+[ 0-9a-f]+: 0044 f17c wrpgpr v0,a0
+[ 0-9a-f]+: 0042 f17c wrpgpr v0,v0
+[ 0-9a-f]+: 0042 f17c wrpgpr v0,v0
+[ 0-9a-f]+: 0043 7b3c wsbh v0,v1
+[ 0-9a-f]+: 0044 7b3c wsbh v0,a0
+[ 0-9a-f]+: 0042 7b3c wsbh v0,v0
+[ 0-9a-f]+: 0042 7b3c wsbh v0,v0
+[ 0-9a-f]+: 4452 xor v0,v0,v0
+[ 0-9a-f]+: 4453 xor v0,v0,v1
+[ 0-9a-f]+: 4454 xor v0,v0,a0
+[ 0-9a-f]+: 4455 xor v0,v0,a1
+[ 0-9a-f]+: 4456 xor v0,v0,a2
+[ 0-9a-f]+: 4457 xor v0,v0,a3
+[ 0-9a-f]+: 4450 xor v0,v0,s0
+[ 0-9a-f]+: 4451 xor v0,v0,s1
+[ 0-9a-f]+: 4459 xor v1,v1,s1
+[ 0-9a-f]+: 4461 xor a0,a0,s1
+[ 0-9a-f]+: 4469 xor a1,a1,s1
+[ 0-9a-f]+: 4471 xor a2,a2,s1
+[ 0-9a-f]+: 4479 xor a3,a3,s1
+[ 0-9a-f]+: 4441 xor s0,s0,s1
+[ 0-9a-f]+: 4449 xor s1,s1,s1
+[ 0-9a-f]+: 4453 xor v0,v0,v1
+[ 0-9a-f]+: 4453 xor v0,v0,v1
+[ 0-9a-f]+: 4453 xor v0,v0,v1
+[ 0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ 0-9a-f]+: 03fe eb10 xor sp,s8,ra
+[ 0-9a-f]+: 0082 1310 xor v0,v0,a0
+[ 0-9a-f]+: 0082 1310 xor v0,v0,a0
+[ 0-9a-f]+: 7043 8000 xori v0,v1,0x8000
+[ 0-9a-f]+: 7043 ffff xori v0,v1,0xffff
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 7064 0000 xori v1,a0,0x0
+[ 0-9a-f]+: 7064 7fff xori v1,a0,0x7fff
+[ 0-9a-f]+: 7064 ffff xori v1,a0,0xffff
+[ 0-9a-f]+: 7063 ffff xori v1,v1,0xffff
+[ 0-9a-f]+: 7063 ffff xori v1,v1,0xffff
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9549 fffe beq t1,t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 9429 fffe beq t1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 404a fffe bgez t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 404a fffe bgez t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 408a fffe blez t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 016a 0b50 slt at,t2,t3
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 404a fffe bgez t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40ca fffe bgtz t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 902a 0002 slti at,t2,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9440 fffe beq zero,v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0062 0b90 sltu at,v0,v1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b402 fffe bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b022 0002 sltiu at,v0,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4062 fffe bgezal v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 40c2 fffe bgtz v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4002 fffe bltz v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 012a 0b50 slt at,t2,t1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0029 0b50 slt at,t1,at
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 012a 0b90 sltu at,t2,t1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 404a fffe bgez t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 012a 0b50 slt at,t2,t1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4009 fffe bltz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 012a 0b90 sltu at,t2,t1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4009 fffe bltz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40ca fffe bgtz t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0149 0b50 slt at,t1,t2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4009 fffe bltz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b540 fffe bne zero,t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0149 0b90 sltu at,t1,t2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4009 fffe bltz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4029 fffe bltzal t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b549 fffe bne t1,t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: b429 fffe bne t1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b549 fffe bne t1,t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: b429 fffe bne t1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 400a fffe bltz t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 400a fffe bltz t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40ca fffe bgtz t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 016a 0b50 slt at,t2,t3
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 400a fffe bltz t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 408a fffe blez t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 902a 0002 slti at,t2,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b440 fffe bne zero,v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0062 0b90 sltu at,v0,v1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9402 fffe beqz v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b022 0002 sltiu at,v0,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4002 fffe bltz v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4002 fffe bltz v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4082 fffe blez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 012a 0b50 slt at,t2,t1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4009 fffe bltz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0029 0b50 slt at,t1,at
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 012a 0b90 sltu at,t2,t1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 400a fffe bltz t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 012a 0b50 slt at,t2,t1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 012a 0b90 sltu at,t2,t1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 408a fffe blez t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0149 0b50 slt at,t1,t2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9540 fffe beq zero,t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0149 0b90 sltu at,t1,t2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9549 fffe beq t1,t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 9429 fffe beq t1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 6d01 addiu v0,sp,0
+[ 0-9a-f]+: 6d03 addiu v0,sp,4
+[ 0-9a-f]+: 6d05 addiu v0,sp,8
+[ 0-9a-f]+: 6d07 addiu v0,sp,12
+[ 0-9a-f]+: 6d09 addiu v0,sp,16
+[ 0-9a-f]+: 6d7f addiu v0,sp,252
+[ 0-9a-f]+: 6dff addiu v1,sp,252
+[ 0-9a-f]+: 6e7f addiu a0,sp,252
+[ 0-9a-f]+: 6eff addiu a1,sp,252
+[ 0-9a-f]+: 6f7f addiu a2,sp,252
+[ 0-9a-f]+: 6fff addiu a3,sp,252
+[ 0-9a-f]+: 6c7f addiu s0,sp,252
+[ 0-9a-f]+: 6cff addiu s1,sp,252
+[ 0-9a-f]+: 6d2e addiu v0,v0,-1
+[ 0-9a-f]+: 6d3e addiu v0,v1,-1
+[ 0-9a-f]+: 6d4e addiu v0,a0,-1
+[ 0-9a-f]+: 6d5e addiu v0,a1,-1
+[ 0-9a-f]+: 6d6e addiu v0,a2,-1
+[ 0-9a-f]+: 6d7e addiu v0,a3,-1
+[ 0-9a-f]+: 6d0e addiu v0,s0,-1
+[ 0-9a-f]+: 6d1e addiu v0,s1,-1
+[ 0-9a-f]+: 6d9e addiu v1,s1,-1
+[ 0-9a-f]+: 6e1e addiu a0,s1,-1
+[ 0-9a-f]+: 6e9e addiu a1,s1,-1
+[ 0-9a-f]+: 6f1e addiu a2,s1,-1
+[ 0-9a-f]+: 6f9e addiu a3,s1,-1
+[ 0-9a-f]+: 6c1e addiu s0,s1,-1
+[ 0-9a-f]+: 6c9e addiu s1,s1,-1
+[ 0-9a-f]+: 6c90 addiu s1,s1,1
+[ 0-9a-f]+: 6c92 addiu s1,s1,4
+[ 0-9a-f]+: 6c94 addiu s1,s1,8
+[ 0-9a-f]+: 6c96 addiu s1,s1,12
+[ 0-9a-f]+: 6c98 addiu s1,s1,16
+[ 0-9a-f]+: 6c9a addiu s1,s1,20
+[ 0-9a-f]+: 6c9c addiu s1,s1,24
+[ 0-9a-f]+: 4c05 addiu sp,sp,8
+[ 0-9a-f]+: 4c07 addiu sp,sp,12
+[ 0-9a-f]+: 4dfd addiu sp,sp,1016
+[ 0-9a-f]+: 4dff addiu sp,sp,1020
+[ 0-9a-f]+: 4c01 addiu sp,sp,1024
+[ 0-9a-f]+: 4c03 addiu sp,sp,1028
+[ 0-9a-f]+: 4ffb addiu sp,sp,-12
+[ 0-9a-f]+: 4ff9 addiu sp,sp,-16
+[ 0-9a-f]+: 4e03 addiu sp,sp,-1020
+[ 0-9a-f]+: 4e01 addiu sp,sp,-1024
+[ 0-9a-f]+: 4fff addiu sp,sp,-1028
+[ 0-9a-f]+: 4ffd addiu sp,sp,-1032
+[ 0-9a-f]+: 4c00 addiu zero,zero,0
+[ 0-9a-f]+: 4c40 addiu v0,v0,0
+[ 0-9a-f]+: 4c60 addiu v1,v1,0
+[ 0-9a-f]+: 4fc0 addiu s8,s8,0
+[ 0-9a-f]+: 4fe0 addiu ra,ra,0
+[ 0-9a-f]+: 4fe2 addiu ra,ra,1
+[ 0-9a-f]+: 4fe4 addiu ra,ra,2
+[ 0-9a-f]+: 4fe6 addiu ra,ra,3
+[ 0-9a-f]+: 4fee addiu ra,ra,7
+[ 0-9a-f]+: 4ff4 addiu ra,ra,-6
+[ 0-9a-f]+: 4ff2 addiu ra,ra,-7
+[ 0-9a-f]+: 4ff0 addiu ra,ra,-8
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f880 0008 sw a0,8\(zero\)
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f880 0008 sw a0,8\(zero\)
+[ 0-9a-f]+: f860 7fff sw v1,32767\(zero\)
+[ 0-9a-f]+: f880 8003 sw a0,-32765\(zero\)
+[ 0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ 0-9a-f]+: f880 8004 sw a0,-32764\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: f861 8000 sw v1,-32768\(at\)
+[ 0-9a-f]+: f881 8004 sw a0,-32764\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f881 0005 sw a0,5\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: f861 8001 sw v1,-32767\(at\)
+[ 0-9a-f]+: f881 8005 sw a0,-32763\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: f881 567c sw a0,22140\(at\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f884 0004 sw a0,4\(a0\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f884 0004 sw a0,4\(a0\)
+[ 0-9a-f]+: f864 7fff sw v1,32767\(a0\)
+[ 0-9a-f]+: f884 8003 sw a0,-32765\(a0\)
+[ 0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ 0-9a-f]+: f884 8004 sw a0,-32764\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 8000 sw v1,-32768\(at\)
+[ 0-9a-f]+: f881 8004 sw a0,-32764\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f881 0005 sw a0,5\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 8001 sw v1,-32767\(at\)
+[ 0-9a-f]+: f881 8005 sw a0,-32763\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: f881 567c sw a0,22140\(at\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc80 0008 lw a0,8\(zero\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc80 0008 lw a0,8\(zero\)
+[ 0-9a-f]+: fc60 7fff lw v1,32767\(zero\)
+[ 0-9a-f]+: fc80 8003 lw a0,-32765\(zero\)
+[ 0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ 0-9a-f]+: fc80 8004 lw a0,-32764\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ 0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: fc61 8000 lw v1,-32768\(at\)
+[ 0-9a-f]+: fc81 8004 lw a0,-32764\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: fc61 0001 lw v1,1\(at\)
+[ 0-9a-f]+: fc81 0005 lw a0,5\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: fc61 8001 lw v1,-32767\(at\)
+[ 0-9a-f]+: fc81 8005 lw a0,-32763\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ 0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: fc61 5678 lw v1,22136\(at\)
+[ 0-9a-f]+: fc81 567c lw a0,22140\(at\)
+[ 0-9a-f]+: fc64 0000 lw v1,0\(a0\)
+[ 0-9a-f]+: fc84 0004 lw a0,4\(a0\)
+[ 0-9a-f]+: fc64 0000 lw v1,0\(a0\)
+[ 0-9a-f]+: fc84 0004 lw a0,4\(a0\)
+[ 0-9a-f]+: fc64 7fff lw v1,32767\(a0\)
+[ 0-9a-f]+: fc84 8003 lw a0,-32765\(a0\)
+[ 0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ 0-9a-f]+: fc84 8004 lw a0,-32764\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ 0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 8000 lw v1,-32768\(at\)
+[ 0-9a-f]+: fc81 8004 lw a0,-32764\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 0001 lw v1,1\(at\)
+[ 0-9a-f]+: fc81 0005 lw a0,5\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 8001 lw v1,-32767\(at\)
+[ 0-9a-f]+: fc81 8005 lw a0,-32763\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ 0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 5678 lw v1,22136\(at\)
+[ 0-9a-f]+: fc81 567c lw a0,22140\(at\)
+[ 0-9a-f]+: 4700 jraddiusp 0
+[ 0-9a-f]+: 4701 jraddiusp 4
+[ 0-9a-f]+: 4702 jraddiusp 8
+[ 0-9a-f]+: 4703 jraddiusp 12
+[ 0-9a-f]+: 4704 jraddiusp 16
+[ 0-9a-f]+: 4705 jraddiusp 20
+[ 0-9a-f]+: 4706 jraddiusp 24
+[ 0-9a-f]+: 4707 jraddiusp 28
+[ 0-9a-f]+: 4708 jraddiusp 32
+[ 0-9a-f]+: 4709 jraddiusp 36
+[ 0-9a-f]+: 470a jraddiusp 40
+[ 0-9a-f]+: 471e jraddiusp 120
+[ 0-9a-f]+: 471f jraddiusp 124
+[ 0-9a-f]+: 2060 2000 ldc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 2000 ldc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 2004 ldc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 2004 ldc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 2000 ldc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 2000 ldc2 \$3,0\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2fff ldc2 \$3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2fff ldc2 \$3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2001 ldc2 \$3,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2001 ldc2 \$3,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 2fff ldc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2678 ldc2 \$3,1656\(at\)
+[ 0-9a-f]+: 2060 0000 lwc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 0000 lwc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 0004 lwc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 0004 lwc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 0000 lwc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 0000 lwc2 \$3,0\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0fff lwc2 \$3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0fff lwc2 \$3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0001 lwc2 \$3,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0001 lwc2 \$3,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 0fff lwc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0678 lwc2 \$3,1656\(at\)
+[ 0-9a-f]+: 00a0 4d3c mfc2 a1,\$0
+[ 0-9a-f]+: 00a1 4d3c mfc2 a1,\$1
+[ 0-9a-f]+: 00a2 4d3c mfc2 a1,\$2
+[ 0-9a-f]+: 00a3 4d3c mfc2 a1,\$3
+[ 0-9a-f]+: 00a4 4d3c mfc2 a1,\$4
+[ 0-9a-f]+: 00a5 4d3c mfc2 a1,\$5
+[ 0-9a-f]+: 00a6 4d3c mfc2 a1,\$6
+[ 0-9a-f]+: 00a7 4d3c mfc2 a1,\$7
+[ 0-9a-f]+: 00a8 4d3c mfc2 a1,\$8
+[ 0-9a-f]+: 00a9 4d3c mfc2 a1,\$9
+[ 0-9a-f]+: 00aa 4d3c mfc2 a1,\$10
+[ 0-9a-f]+: 00ab 4d3c mfc2 a1,\$11
+[ 0-9a-f]+: 00ac 4d3c mfc2 a1,\$12
+[ 0-9a-f]+: 00ad 4d3c mfc2 a1,\$13
+[ 0-9a-f]+: 00ae 4d3c mfc2 a1,\$14
+[ 0-9a-f]+: 00af 4d3c mfc2 a1,\$15
+[ 0-9a-f]+: 00b0 4d3c mfc2 a1,\$16
+[ 0-9a-f]+: 00b1 4d3c mfc2 a1,\$17
+[ 0-9a-f]+: 00b2 4d3c mfc2 a1,\$18
+[ 0-9a-f]+: 00b3 4d3c mfc2 a1,\$19
+[ 0-9a-f]+: 00b4 4d3c mfc2 a1,\$20
+[ 0-9a-f]+: 00b5 4d3c mfc2 a1,\$21
+[ 0-9a-f]+: 00b6 4d3c mfc2 a1,\$22
+[ 0-9a-f]+: 00b7 4d3c mfc2 a1,\$23
+[ 0-9a-f]+: 00b8 4d3c mfc2 a1,\$24
+[ 0-9a-f]+: 00b9 4d3c mfc2 a1,\$25
+[ 0-9a-f]+: 00ba 4d3c mfc2 a1,\$26
+[ 0-9a-f]+: 00bb 4d3c mfc2 a1,\$27
+[ 0-9a-f]+: 00bc 4d3c mfc2 a1,\$28
+[ 0-9a-f]+: 00bd 4d3c mfc2 a1,\$29
+[ 0-9a-f]+: 00be 4d3c mfc2 a1,\$30
+[ 0-9a-f]+: 00bf 4d3c mfc2 a1,\$31
+[ 0-9a-f]+: 00a0 8d3c mfhc2 a1,\$0
+[ 0-9a-f]+: 00a1 8d3c mfhc2 a1,\$1
+[ 0-9a-f]+: 00a2 8d3c mfhc2 a1,\$2
+[ 0-9a-f]+: 00a3 8d3c mfhc2 a1,\$3
+[ 0-9a-f]+: 00a4 8d3c mfhc2 a1,\$4
+[ 0-9a-f]+: 00a5 8d3c mfhc2 a1,\$5
+[ 0-9a-f]+: 00a6 8d3c mfhc2 a1,\$6
+[ 0-9a-f]+: 00a7 8d3c mfhc2 a1,\$7
+[ 0-9a-f]+: 00a8 8d3c mfhc2 a1,\$8
+[ 0-9a-f]+: 00a9 8d3c mfhc2 a1,\$9
+[ 0-9a-f]+: 00aa 8d3c mfhc2 a1,\$10
+[ 0-9a-f]+: 00ab 8d3c mfhc2 a1,\$11
+[ 0-9a-f]+: 00ac 8d3c mfhc2 a1,\$12
+[ 0-9a-f]+: 00ad 8d3c mfhc2 a1,\$13
+[ 0-9a-f]+: 00ae 8d3c mfhc2 a1,\$14
+[ 0-9a-f]+: 00af 8d3c mfhc2 a1,\$15
+[ 0-9a-f]+: 00b0 8d3c mfhc2 a1,\$16
+[ 0-9a-f]+: 00b1 8d3c mfhc2 a1,\$17
+[ 0-9a-f]+: 00b2 8d3c mfhc2 a1,\$18
+[ 0-9a-f]+: 00b3 8d3c mfhc2 a1,\$19
+[ 0-9a-f]+: 00b4 8d3c mfhc2 a1,\$20
+[ 0-9a-f]+: 00b5 8d3c mfhc2 a1,\$21
+[ 0-9a-f]+: 00b6 8d3c mfhc2 a1,\$22
+[ 0-9a-f]+: 00b7 8d3c mfhc2 a1,\$23
+[ 0-9a-f]+: 00b8 8d3c mfhc2 a1,\$24
+[ 0-9a-f]+: 00b9 8d3c mfhc2 a1,\$25
+[ 0-9a-f]+: 00ba 8d3c mfhc2 a1,\$26
+[ 0-9a-f]+: 00bb 8d3c mfhc2 a1,\$27
+[ 0-9a-f]+: 00bc 8d3c mfhc2 a1,\$28
+[ 0-9a-f]+: 00bd 8d3c mfhc2 a1,\$29
+[ 0-9a-f]+: 00be 8d3c mfhc2 a1,\$30
+[ 0-9a-f]+: 00bf 8d3c mfhc2 a1,\$31
+[ 0-9a-f]+: 00a0 5d3c mtc2 a1,\$0
+[ 0-9a-f]+: 00a1 5d3c mtc2 a1,\$1
+[ 0-9a-f]+: 00a2 5d3c mtc2 a1,\$2
+[ 0-9a-f]+: 00a3 5d3c mtc2 a1,\$3
+[ 0-9a-f]+: 00a4 5d3c mtc2 a1,\$4
+[ 0-9a-f]+: 00a5 5d3c mtc2 a1,\$5
+[ 0-9a-f]+: 00a6 5d3c mtc2 a1,\$6
+[ 0-9a-f]+: 00a7 5d3c mtc2 a1,\$7
+[ 0-9a-f]+: 00a8 5d3c mtc2 a1,\$8
+[ 0-9a-f]+: 00a9 5d3c mtc2 a1,\$9
+[ 0-9a-f]+: 00aa 5d3c mtc2 a1,\$10
+[ 0-9a-f]+: 00ab 5d3c mtc2 a1,\$11
+[ 0-9a-f]+: 00ac 5d3c mtc2 a1,\$12
+[ 0-9a-f]+: 00ad 5d3c mtc2 a1,\$13
+[ 0-9a-f]+: 00ae 5d3c mtc2 a1,\$14
+[ 0-9a-f]+: 00af 5d3c mtc2 a1,\$15
+[ 0-9a-f]+: 00b0 5d3c mtc2 a1,\$16
+[ 0-9a-f]+: 00b1 5d3c mtc2 a1,\$17
+[ 0-9a-f]+: 00b2 5d3c mtc2 a1,\$18
+[ 0-9a-f]+: 00b3 5d3c mtc2 a1,\$19
+[ 0-9a-f]+: 00b4 5d3c mtc2 a1,\$20
+[ 0-9a-f]+: 00b5 5d3c mtc2 a1,\$21
+[ 0-9a-f]+: 00b6 5d3c mtc2 a1,\$22
+[ 0-9a-f]+: 00b7 5d3c mtc2 a1,\$23
+[ 0-9a-f]+: 00b8 5d3c mtc2 a1,\$24
+[ 0-9a-f]+: 00b9 5d3c mtc2 a1,\$25
+[ 0-9a-f]+: 00ba 5d3c mtc2 a1,\$26
+[ 0-9a-f]+: 00bb 5d3c mtc2 a1,\$27
+[ 0-9a-f]+: 00bc 5d3c mtc2 a1,\$28
+[ 0-9a-f]+: 00bd 5d3c mtc2 a1,\$29
+[ 0-9a-f]+: 00be 5d3c mtc2 a1,\$30
+[ 0-9a-f]+: 00bf 5d3c mtc2 a1,\$31
+[ 0-9a-f]+: 00a0 9d3c mthc2 a1,\$0
+[ 0-9a-f]+: 00a1 9d3c mthc2 a1,\$1
+[ 0-9a-f]+: 00a2 9d3c mthc2 a1,\$2
+[ 0-9a-f]+: 00a3 9d3c mthc2 a1,\$3
+[ 0-9a-f]+: 00a4 9d3c mthc2 a1,\$4
+[ 0-9a-f]+: 00a5 9d3c mthc2 a1,\$5
+[ 0-9a-f]+: 00a6 9d3c mthc2 a1,\$6
+[ 0-9a-f]+: 00a7 9d3c mthc2 a1,\$7
+[ 0-9a-f]+: 00a8 9d3c mthc2 a1,\$8
+[ 0-9a-f]+: 00a9 9d3c mthc2 a1,\$9
+[ 0-9a-f]+: 00aa 9d3c mthc2 a1,\$10
+[ 0-9a-f]+: 00ab 9d3c mthc2 a1,\$11
+[ 0-9a-f]+: 00ac 9d3c mthc2 a1,\$12
+[ 0-9a-f]+: 00ad 9d3c mthc2 a1,\$13
+[ 0-9a-f]+: 00ae 9d3c mthc2 a1,\$14
+[ 0-9a-f]+: 00af 9d3c mthc2 a1,\$15
+[ 0-9a-f]+: 00b0 9d3c mthc2 a1,\$16
+[ 0-9a-f]+: 00b1 9d3c mthc2 a1,\$17
+[ 0-9a-f]+: 00b2 9d3c mthc2 a1,\$18
+[ 0-9a-f]+: 00b3 9d3c mthc2 a1,\$19
+[ 0-9a-f]+: 00b4 9d3c mthc2 a1,\$20
+[ 0-9a-f]+: 00b5 9d3c mthc2 a1,\$21
+[ 0-9a-f]+: 00b6 9d3c mthc2 a1,\$22
+[ 0-9a-f]+: 00b7 9d3c mthc2 a1,\$23
+[ 0-9a-f]+: 00b8 9d3c mthc2 a1,\$24
+[ 0-9a-f]+: 00b9 9d3c mthc2 a1,\$25
+[ 0-9a-f]+: 00ba 9d3c mthc2 a1,\$26
+[ 0-9a-f]+: 00bb 9d3c mthc2 a1,\$27
+[ 0-9a-f]+: 00bc 9d3c mthc2 a1,\$28
+[ 0-9a-f]+: 00bd 9d3c mthc2 a1,\$29
+[ 0-9a-f]+: 00be 9d3c mthc2 a1,\$30
+[ 0-9a-f]+: 00bf 9d3c mthc2 a1,\$31
+[ 0-9a-f]+: 2060 a000 sdc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 a000 sdc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 a004 sdc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 a004 sdc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 a000 sdc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 a000 sdc2 \$3,0\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 afff sdc2 \$3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 afff sdc2 \$3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a001 sdc2 \$3,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a001 sdc2 \$3,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 afff sdc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a678 sdc2 \$3,1656\(at\)
+[ 0-9a-f]+: 2060 8000 swc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 8000 swc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 8004 swc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 8004 swc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 8000 swc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 8000 swc2 \$3,0\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8fff swc2 \$3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8fff swc2 \$3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8001 swc2 \$3,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8001 swc2 \$3,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 8fff swc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8678 swc2 \$3,1656\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2041 1000 lwp v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 3043 0000 addiu v0,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6042 3000 ll v0,0\(v0\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 b000 sc v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 0000 lwl v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 1000 lwr v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 8000 swl v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 9000 swr v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 0000 lwc2 \$16,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 8000 swc2 \$16,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 0000 lwl v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 1000 lwr v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 8000 swl v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 9000 swr v0,0\(at\)
+[ 0-9a-f]+: 03ff db7c sdbbp 0x3ff
+[ 0-9a-f]+: 03ff 937c wait 0x3ff
+[ 0-9a-f]+: 03ff 8b7c syscall 0x3ff
+[ 0-9a-f]+: 03ff fffa cop2 0x7fffff
+
+[0-9a-f]+ <fp_test>:
+[ 0-9a-f]+: 5400 01a0 prefx 0x0,zero\(zero\)
+[ 0-9a-f]+: 5402 01a0 prefx 0x0,zero\(v0\)
+[ 0-9a-f]+: 541f 01a0 prefx 0x0,zero\(ra\)
+[ 0-9a-f]+: 545f 01a0 prefx 0x0,v0\(ra\)
+[ 0-9a-f]+: 57ff 01a0 prefx 0x0,ra\(ra\)
+[ 0-9a-f]+: 57ff 09a0 prefx 0x1,ra\(ra\)
+[ 0-9a-f]+: 57ff 11a0 prefx 0x2,ra\(ra\)
+[ 0-9a-f]+: 57ff f9a0 prefx 0x1f,ra\(ra\)
+[ 0-9a-f]+: 5401 037b abs\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 037b abs\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 037b abs\.s \$f2,\$f2
+[ 0-9a-f]+: 5442 037b abs\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 237b abs\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 237b abs\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 237b abs\.d \$f2,\$f2
+[ 0-9a-f]+: 5442 237b abs\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 437b abs\.ps \$f0,\$f1
+[ 0-9a-f]+: 57df 437b abs\.ps \$f30,\$f31
+[ 0-9a-f]+: 5442 437b abs\.ps \$f2,\$f2
+[ 0-9a-f]+: 5442 437b abs\.ps \$f2,\$f2
+[ 0-9a-f]+: 5441 0030 add\.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e830 add\.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e830 add\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e830 add\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0130 add\.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e930 add\.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e930 add\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e930 add\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0230 add\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe ea30 add\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd ea30 add\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd ea30 add\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0019 alnv\.ps \$f0,\$f1,\$f2,zero
+[ 0-9a-f]+: 5441 0099 alnv\.ps \$f0,\$f1,\$f2,v0
+[ 0-9a-f]+: 5441 07d9 alnv\.ps \$f0,\$f1,\$f2,ra
+[ 0-9a-f]+: 57fe efd9 alnv\.ps \$f29,\$f30,\$f31,ra
+[ 0-9a-f]+: 57fd efd9 alnv\.ps \$f29,\$f29,\$f31,ra
+[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4384 fffe bc1f \$fcc1,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4388 fffe bc1f \$fcc2,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 438c fffe bc1f \$fcc3,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4390 fffe bc1f \$fcc4,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4394 fffe bc1f \$fcc5,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4398 fffe bc1f \$fcc6,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 439c fffe bc1f \$fcc7,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43a0 fffe bc1t [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43a0 fffe bc1t [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43a4 fffe bc1t \$fcc1,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43a8 fffe bc1t \$fcc2,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43ac fffe bc1t \$fcc3,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43b0 fffe bc1t \$fcc4,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43b4 fffe bc1t \$fcc5,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43b8 fffe bc1t \$fcc6,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43bc fffe bc1t \$fcc7,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 5420 043c c\.f\.d \$f0,\$f1
+[ 0-9a-f]+: 57fe 043c c\.f\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 043c c\.f\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 243c c\.f\.d \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e43c c\.f\.d \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 003c c\.f\.s \$f0,\$f1
+[ 0-9a-f]+: 57fe 003c c\.f\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 003c c\.f\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 203c c\.f\.s \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e03c c\.f\.s \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 083c c\.f\.ps \$f0,\$f1
+[ 0-9a-f]+: 57fe 083c c\.f\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 083c c\.f\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 483c c\.f\.ps \$fcc2,\$f30,\$f31
+[ 0-9a-f]+: 57fe c83c c\.f\.ps \$fcc6,\$f30,\$f31
+[ 0-9a-f]+: 5420 047c c\.un\.d \$f0,\$f1
+[ 0-9a-f]+: 57fe 047c c\.un\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 047c c\.un\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 247c c\.un\.d \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e47c c\.un\.d \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 007c c\.un\.s \$f0,\$f1
+[ 0-9a-f]+: 57fe 007c c\.un\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 007c c\.un\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 207c c\.un\.s \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e07c c\.un\.s \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 087c c\.un\.ps \$f0,\$f1
+[ 0-9a-f]+: 57fe 087c c\.un\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 087c c\.un\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 487c c\.un\.ps \$fcc2,\$f30,\$f31
+[ 0-9a-f]+: 57fe c87c c\.un\.ps \$fcc6,\$f30,\$f31
+[ 0-9a-f]+: 5420 04bc c\.eq\.d \$f0,\$f1
+[ 0-9a-f]+: 57fe 04bc c\.eq\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 04bc c\.eq\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 24bc c\.eq\.d \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e4bc c\.eq\.d \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 00bc c\.eq\.s \$f0,\$f1
+[ 0-9a-f]+: 57fe 00bc c\.eq\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 00bc c\.eq\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 20bc c\.eq\.s \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e0bc c\.eq\.s \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 08bc c\.eq\.ps \$f0,\$f1
+[ 0-9a-f]+: 57fe 08bc c\.eq\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 08bc c\.eq\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 48bc c\.eq\.ps \$fcc2,\$f30,\$f31
+[ 0-9a-f]+: 57fe c8bc c\.eq\.ps \$fcc6,\$f30,\$f31
+[ 0-9a-f]+: 5420 04fc c\.ueq\.d \$f0,\$f1
+[ 0-9a-f]+: 57fe 04fc c\.ueq\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 04fc c\.ueq\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 24fc c\.ueq\.d \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e4fc c\.ueq\.d \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 00fc c\.ueq\.s \$f0,\$f1
+[ 0-9a-f]+: 57fe 00fc c\.ueq\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 00fc c\.ueq\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 20fc c\.ueq\.s \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e0fc c\.ueq\.s \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 08fc c\.ueq\.ps \$f0,\$f1
+[ 0-9a-f]+: 57fe 08fc c\.ueq\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 08fc c\.ueq\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 48fc c\.ueq\.ps \$fcc2,\$f30,\$f31
+[ 0-9a-f]+: 57fe c8fc c\.ueq\.ps \$fcc6,\$f30,\$f31
+[ 0-9a-f]+: 5420 053c c\.olt\.d \$f0,\$f1
+[ 0-9a-f]+: 57fe 053c c\.olt\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 053c c\.olt\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 253c c\.olt\.d \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e53c c\.olt\.d \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 013c c\.olt\.s \$f0,\$f1
+[ 0-9a-f]+: 57fe 013c c\.olt\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 013c c\.olt\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 213c c\.olt\.s \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e13c c\.olt\.s \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 093c c\.olt\.ps \$f0,\$f1
+[ 0-9a-f]+: 57fe 093c c\.olt\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 093c c\.olt\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 493c c\.olt\.ps \$fcc2,\$f30,\$f31
+[ 0-9a-f]+: 57fe c93c c\.olt\.ps \$fcc6,\$f30,\$f31
+[ 0-9a-f]+: 5420 057c c\.ult\.d \$f0,\$f1
+[ 0-9a-f]+: 57fe 057c c\.ult\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 057c c\.ult\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 257c c\.ult\.d \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e57c c\.ult\.d \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 017c c\.ult\.s \$f0,\$f1
+[ 0-9a-f]+: 57fe 017c c\.ult\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 017c c\.ult\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 217c c\.ult\.s \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e17c c\.ult\.s \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 097c c\.ult\.ps \$f0,\$f1
+[ 0-9a-f]+: 57fe 097c c\.ult\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 097c c\.ult\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 497c c\.ult\.ps \$fcc2,\$f30,\$f31
+[ 0-9a-f]+: 57fe c97c c\.ult\.ps \$fcc6,\$f30,\$f31
+[ 0-9a-f]+: 5420 05bc c\.ole\.d \$f0,\$f1
+[ 0-9a-f]+: 57fe 05bc c\.ole\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 05bc c\.ole\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 25bc c\.ole\.d \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e5bc c\.ole\.d \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 01bc c\.ole\.s \$f0,\$f1
+[ 0-9a-f]+: 57fe 01bc c\.ole\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 01bc c\.ole\.s \$f30,\$f31
+[ 0-9a-f]+: 57fe 21bc c\.ole\.s \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e1bc c\.ole\.s \$fcc7,\$f30,\$f31
+[ 0-9a-f]+: 5420 09bc c\.ole\.ps \$f0,\$f1
+[ 0-9a-f]+: 57fe 09bc c\.ole\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 09bc c\.ole\.ps \$f30,\$f31
+[ 0-9a-f]+: 57fe 49bc c\.ole\.ps \$fcc2,\$f30,\$f31
+[ 0-9a-f]+: 57fe c9bc c\.ole\.ps \$fcc6,\$f30,\$f31
+[ 0-9a-f]+: 5420 05fc c\.ule\.d \$f0,\$f1
+[ 0-9a-f]+: 57fe 05fc c\.ule\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 05fc c\.ule\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 25fc c\.ule\.d \$fcc1,\$f30,\$f31
+[ 0-9a-f]+: 57fe e5fc c\.ule\.d \$fcc7,\$f30,\$f31
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+[ 0-9a-f]+: 54b3 183b ctc1 a1,\$19
+[ 0-9a-f]+: 54b4 183b ctc1 a1,\$20
+[ 0-9a-f]+: 54b5 183b ctc1 a1,\$21
+[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
+[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
+[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
+[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
+[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
+[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0
+[ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1
+[ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2
+[ 0-9a-f]+: 00a3 dd3c ctc2 a1,\$3
+[ 0-9a-f]+: 00a4 dd3c ctc2 a1,\$4
+[ 0-9a-f]+: 00a5 dd3c ctc2 a1,\$5
+[ 0-9a-f]+: 00a6 dd3c ctc2 a1,\$6
+[ 0-9a-f]+: 00a7 dd3c ctc2 a1,\$7
+[ 0-9a-f]+: 00a8 dd3c ctc2 a1,\$8
+[ 0-9a-f]+: 00a9 dd3c ctc2 a1,\$9
+[ 0-9a-f]+: 00aa dd3c ctc2 a1,\$10
+[ 0-9a-f]+: 00ab dd3c ctc2 a1,\$11
+[ 0-9a-f]+: 00ac dd3c ctc2 a1,\$12
+[ 0-9a-f]+: 00ad dd3c ctc2 a1,\$13
+[ 0-9a-f]+: 00ae dd3c ctc2 a1,\$14
+[ 0-9a-f]+: 00af dd3c ctc2 a1,\$15
+[ 0-9a-f]+: 00b0 dd3c ctc2 a1,\$16
+[ 0-9a-f]+: 00b1 dd3c ctc2 a1,\$17
+[ 0-9a-f]+: 00b2 dd3c ctc2 a1,\$18
+[ 0-9a-f]+: 00b3 dd3c ctc2 a1,\$19
+[ 0-9a-f]+: 00b4 dd3c ctc2 a1,\$20
+[ 0-9a-f]+: 00b5 dd3c ctc2 a1,\$21
+[ 0-9a-f]+: 00b6 dd3c ctc2 a1,\$22
+[ 0-9a-f]+: 00b7 dd3c ctc2 a1,\$23
+[ 0-9a-f]+: 00b8 dd3c ctc2 a1,\$24
+[ 0-9a-f]+: 00b9 dd3c ctc2 a1,\$25
+[ 0-9a-f]+: 00ba dd3c ctc2 a1,\$26
+[ 0-9a-f]+: 00bb dd3c ctc2 a1,\$27
+[ 0-9a-f]+: 00bc dd3c ctc2 a1,\$28
+[ 0-9a-f]+: 00bd dd3c ctc2 a1,\$29
+[ 0-9a-f]+: 00be dd3c ctc2 a1,\$30
+[ 0-9a-f]+: 00bf dd3c ctc2 a1,\$31
+[ 0-9a-f]+: 5401 537b cvt\.d\.l \$f0,\$f1
+[ 0-9a-f]+: 57df 537b cvt\.d\.l \$f30,\$f31
+[ 0-9a-f]+: 5442 537b cvt\.d\.l \$f2,\$f2
+[ 0-9a-f]+: 5401 137b cvt\.d\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 137b cvt\.d\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 137b cvt\.d\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 337b cvt\.d\.w \$f0,\$f1
+[ 0-9a-f]+: 57df 337b cvt\.d\.w \$f30,\$f31
+[ 0-9a-f]+: 5442 337b cvt\.d\.w \$f2,\$f2
+[ 0-9a-f]+: 5401 013b cvt\.l\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 013b cvt\.l\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 013b cvt\.l\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 413b cvt\.l\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 413b cvt\.l\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 413b cvt\.l\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 5b7b cvt\.s\.l \$f0,\$f1
+[ 0-9a-f]+: 57df 5b7b cvt\.s\.l \$f30,\$f31
+[ 0-9a-f]+: 5442 5b7b cvt\.s\.l \$f2,\$f2
+[ 0-9a-f]+: 5401 1b7b cvt\.s\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 1b7b cvt\.s\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 1b7b cvt\.s\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 3b7b cvt\.s\.w \$f0,\$f1
+[ 0-9a-f]+: 57df 3b7b cvt\.s\.w \$f30,\$f31
+[ 0-9a-f]+: 5442 3b7b cvt\.s\.w \$f2,\$f2
+[ 0-9a-f]+: 5401 213b cvt\.s\.pl \$f0,\$f1
+[ 0-9a-f]+: 57df 213b cvt\.s\.pl \$f30,\$f31
+[ 0-9a-f]+: 5442 213b cvt\.s\.pl \$f2,\$f2
+[ 0-9a-f]+: 5401 293b cvt\.s\.pu \$f0,\$f1
+[ 0-9a-f]+: 57df 293b cvt\.s\.pu \$f30,\$f31
+[ 0-9a-f]+: 5442 293b cvt\.s\.pu \$f2,\$f2
+[ 0-9a-f]+: 5401 093b cvt\.w\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 093b cvt\.w\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 093b cvt\.w\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 493b cvt\.w\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 493b cvt\.w\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 493b cvt\.w\.d \$f2,\$f2
+[ 0-9a-f]+: 5441 0180 cvt\.ps\.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e980 cvt\.ps\.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57fd e980 cvt\.ps\.s \$f29,\$f29,\$f31
+[ 0-9a-f]+: 57fd e980 cvt\.ps\.s \$f29,\$f29,\$f31
+[ 0-9a-f]+: 5441 01f0 div\.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e9f0 div\.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e9f0 div\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e9f0 div\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 00f0 div\.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e8f0 div\.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e8f0 div\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e8f0 div\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5401 433b floor\.l\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 433b floor\.l\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 433b floor\.l\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 033b floor\.l\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 033b floor\.l\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 033b floor\.l\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 4b3b floor\.w\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 4b3b floor\.w\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 4b3b floor\.w\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 0b3b floor\.w\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 0b3b floor\.w\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 0b3b floor\.w\.s \$f2,\$f2
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 ffff ldc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0001 ldc1 \$f3,1\(at\)
+[ 0-9a-f]+: bc64 8001 ldc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 ffff ldc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 5678 ldc1 \$f3,22136\(at\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 ffff ldc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0001 ldc1 \$f3,1\(at\)
+[ 0-9a-f]+: bc64 8001 ldc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 ffff ldc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 5678 ldc1 \$f3,22136\(at\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 5400 00c8 ldxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 00c8 ldxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 00c8 ldxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 00c8 ldxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 00c8 ldxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 08c8 ldxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 10c8 ldxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f8c8 ldxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 5400 0148 luxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 0148 luxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 0148 luxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 0148 luxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 0148 luxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 0948 luxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 1148 luxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f948 luxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 5400 0048 lwxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 0048 lwxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 0048 lwxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 0048 lwxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 0048 lwxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 0848 lwxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 1048 lwxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f848 lwxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 5462 0049 madd\.d \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e749 madd\.d \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0041 madd\.s \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e741 madd\.s \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0051 madd\.ps \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e751 madd\.ps \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 54a0 203b mfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 203b mfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 203b mfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 203b mfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 203b mfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 203b mfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 203b mfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 203b mfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 203b mfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 203b mfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 203b mfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 203b mfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 203b mfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 203b mfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 203b mfc1 a1,\$f14
+[ 0-9a-f]+: 54af 203b mfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 203b mfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 203b mfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 203b mfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 203b mfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 203b mfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 203b mfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 203b mfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 203b mfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 203b mfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 203b mfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 203b mfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 203b mfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 203b mfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 203b mfc1 a1,\$f29
+[ 0-9a-f]+: 54be 203b mfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 203b mfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 203b mfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 203b mfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 203b mfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 203b mfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 203b mfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 203b mfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 203b mfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 203b mfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 203b mfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 203b mfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 203b mfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 203b mfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 203b mfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 203b mfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 203b mfc1 a1,\$f14
+[ 0-9a-f]+: 54af 203b mfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 203b mfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 203b mfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 203b mfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 203b mfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 203b mfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 203b mfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 203b mfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 203b mfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 203b mfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 203b mfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 203b mfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 203b mfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 203b mfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 203b mfc1 a1,\$f29
+[ 0-9a-f]+: 54be 203b mfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 203b mfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 303b mfhc1 a1,\$f0
+[ 0-9a-f]+: 54a1 303b mfhc1 a1,\$f1
+[ 0-9a-f]+: 54a2 303b mfhc1 a1,\$f2
+[ 0-9a-f]+: 54a3 303b mfhc1 a1,\$f3
+[ 0-9a-f]+: 54a4 303b mfhc1 a1,\$f4
+[ 0-9a-f]+: 54a5 303b mfhc1 a1,\$f5
+[ 0-9a-f]+: 54a6 303b mfhc1 a1,\$f6
+[ 0-9a-f]+: 54a7 303b mfhc1 a1,\$f7
+[ 0-9a-f]+: 54a8 303b mfhc1 a1,\$f8
+[ 0-9a-f]+: 54a9 303b mfhc1 a1,\$f9
+[ 0-9a-f]+: 54aa 303b mfhc1 a1,\$f10
+[ 0-9a-f]+: 54ab 303b mfhc1 a1,\$f11
+[ 0-9a-f]+: 54ac 303b mfhc1 a1,\$f12
+[ 0-9a-f]+: 54ad 303b mfhc1 a1,\$f13
+[ 0-9a-f]+: 54ae 303b mfhc1 a1,\$f14
+[ 0-9a-f]+: 54af 303b mfhc1 a1,\$f15
+[ 0-9a-f]+: 54b0 303b mfhc1 a1,\$f16
+[ 0-9a-f]+: 54b1 303b mfhc1 a1,\$f17
+[ 0-9a-f]+: 54b2 303b mfhc1 a1,\$f18
+[ 0-9a-f]+: 54b3 303b mfhc1 a1,\$f19
+[ 0-9a-f]+: 54b4 303b mfhc1 a1,\$f20
+[ 0-9a-f]+: 54b5 303b mfhc1 a1,\$f21
+[ 0-9a-f]+: 54b6 303b mfhc1 a1,\$f22
+[ 0-9a-f]+: 54b7 303b mfhc1 a1,\$f23
+[ 0-9a-f]+: 54b8 303b mfhc1 a1,\$f24
+[ 0-9a-f]+: 54b9 303b mfhc1 a1,\$f25
+[ 0-9a-f]+: 54ba 303b mfhc1 a1,\$f26
+[ 0-9a-f]+: 54bb 303b mfhc1 a1,\$f27
+[ 0-9a-f]+: 54bc 303b mfhc1 a1,\$f28
+[ 0-9a-f]+: 54bd 303b mfhc1 a1,\$f29
+[ 0-9a-f]+: 54be 303b mfhc1 a1,\$f30
+[ 0-9a-f]+: 54bf 303b mfhc1 a1,\$f31
+[ 0-9a-f]+: 54a0 303b mfhc1 a1,\$f0
+[ 0-9a-f]+: 54a1 303b mfhc1 a1,\$f1
+[ 0-9a-f]+: 54a2 303b mfhc1 a1,\$f2
+[ 0-9a-f]+: 54a3 303b mfhc1 a1,\$f3
+[ 0-9a-f]+: 54a4 303b mfhc1 a1,\$f4
+[ 0-9a-f]+: 54a5 303b mfhc1 a1,\$f5
+[ 0-9a-f]+: 54a6 303b mfhc1 a1,\$f6
+[ 0-9a-f]+: 54a7 303b mfhc1 a1,\$f7
+[ 0-9a-f]+: 54a8 303b mfhc1 a1,\$f8
+[ 0-9a-f]+: 54a9 303b mfhc1 a1,\$f9
+[ 0-9a-f]+: 54aa 303b mfhc1 a1,\$f10
+[ 0-9a-f]+: 54ab 303b mfhc1 a1,\$f11
+[ 0-9a-f]+: 54ac 303b mfhc1 a1,\$f12
+[ 0-9a-f]+: 54ad 303b mfhc1 a1,\$f13
+[ 0-9a-f]+: 54ae 303b mfhc1 a1,\$f14
+[ 0-9a-f]+: 54af 303b mfhc1 a1,\$f15
+[ 0-9a-f]+: 54b0 303b mfhc1 a1,\$f16
+[ 0-9a-f]+: 54b1 303b mfhc1 a1,\$f17
+[ 0-9a-f]+: 54b2 303b mfhc1 a1,\$f18
+[ 0-9a-f]+: 54b3 303b mfhc1 a1,\$f19
+[ 0-9a-f]+: 54b4 303b mfhc1 a1,\$f20
+[ 0-9a-f]+: 54b5 303b mfhc1 a1,\$f21
+[ 0-9a-f]+: 54b6 303b mfhc1 a1,\$f22
+[ 0-9a-f]+: 54b7 303b mfhc1 a1,\$f23
+[ 0-9a-f]+: 54b8 303b mfhc1 a1,\$f24
+[ 0-9a-f]+: 54b9 303b mfhc1 a1,\$f25
+[ 0-9a-f]+: 54ba 303b mfhc1 a1,\$f26
+[ 0-9a-f]+: 54bb 303b mfhc1 a1,\$f27
+[ 0-9a-f]+: 54bc 303b mfhc1 a1,\$f28
+[ 0-9a-f]+: 54bd 303b mfhc1 a1,\$f29
+[ 0-9a-f]+: 54be 303b mfhc1 a1,\$f30
+[ 0-9a-f]+: 54bf 303b mfhc1 a1,\$f31
+[ 0-9a-f]+: 5401 207b mov\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 207b mov\.d \$f30,\$f31
+[ 0-9a-f]+: 5401 007b mov\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 007b mov\.s \$f30,\$f31
+[ 0-9a-f]+: 5401 407b mov\.ps \$f0,\$f1
+[ 0-9a-f]+: 57df 407b mov\.ps \$f30,\$f31
+[ 0-9a-f]+: 5443 0220 movf\.d \$f2,\$f3,\$fcc0
+[ 0-9a-f]+: 5443 2220 movf\.d \$f2,\$f3,\$fcc1
+[ 0-9a-f]+: 5443 4220 movf\.d \$f2,\$f3,\$fcc2
+[ 0-9a-f]+: 5443 6220 movf\.d \$f2,\$f3,\$fcc3
+[ 0-9a-f]+: 5443 8220 movf\.d \$f2,\$f3,\$fcc4
+[ 0-9a-f]+: 5443 a220 movf\.d \$f2,\$f3,\$fcc5
+[ 0-9a-f]+: 5443 c220 movf\.d \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 5443 e220 movf\.d \$f2,\$f3,\$fcc7
+[ 0-9a-f]+: 57df e220 movf\.d \$f30,\$f31,\$fcc7
+[ 0-9a-f]+: 5443 0020 movf\.s \$f2,\$f3,\$fcc0
+[ 0-9a-f]+: 5443 2020 movf\.s \$f2,\$f3,\$fcc1
+[ 0-9a-f]+: 5443 4020 movf\.s \$f2,\$f3,\$fcc2
+[ 0-9a-f]+: 5443 6020 movf\.s \$f2,\$f3,\$fcc3
+[ 0-9a-f]+: 5443 8020 movf\.s \$f2,\$f3,\$fcc4
+[ 0-9a-f]+: 5443 a020 movf\.s \$f2,\$f3,\$fcc5
+[ 0-9a-f]+: 5443 c020 movf\.s \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 5443 e020 movf\.s \$f2,\$f3,\$fcc7
+[ 0-9a-f]+: 57df e020 movf\.s \$f30,\$f31,\$fcc7
+[ 0-9a-f]+: 5443 0420 movf\.ps \$f2,\$f3,\$fcc0
+[ 0-9a-f]+: 5443 4420 movf\.ps \$f2,\$f3,\$fcc2
+[ 0-9a-f]+: 5443 8420 movf\.ps \$f2,\$f3,\$fcc4
+[ 0-9a-f]+: 5443 c420 movf\.ps \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 5443 c420 movf\.ps \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 57df c420 movf\.ps \$f30,\$f31,\$fcc6
+[ 0-9a-f]+: 5403 1138 movn\.d \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1138 movn\.d \$f2,\$f3,ra
+[ 0-9a-f]+: 5403 1038 movn\.s \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1038 movn\.s \$f2,\$f3,ra
+[ 0-9a-f]+: 5403 1238 movn\.ps \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1238 movn\.ps \$f2,\$f3,ra
+[ 0-9a-f]+: 5443 0460 movt\.ps \$f2,\$f3,\$fcc0
+[ 0-9a-f]+: 5443 4460 movt\.ps \$f2,\$f3,\$fcc2
+[ 0-9a-f]+: 5443 8460 movt\.ps \$f2,\$f3,\$fcc4
+[ 0-9a-f]+: 5443 c460 movt\.ps \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 5443 c460 movt\.ps \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 57df c460 movt\.ps \$f30,\$f31,\$fcc6
+[ 0-9a-f]+: 5403 1178 movz\.d \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1178 movz\.d \$f2,\$f3,ra
+[ 0-9a-f]+: 5403 1078 movz\.s \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1078 movz\.s \$f2,\$f3,ra
+[ 0-9a-f]+: 5403 1278 movz\.ps \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1278 movz\.ps \$f2,\$f3,ra
+[ 0-9a-f]+: 5462 0069 msub\.d \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e769 msub\.d \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0061 msub\.s \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e761 msub\.s \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0071 msub\.ps \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e771 msub\.ps \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 54a0 283b mtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 283b mtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 283b mtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 283b mtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 283b mtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 283b mtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 283b mtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 283b mtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 283b mtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 283b mtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 283b mtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 283b mtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 283b mtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 283b mtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 283b mtc1 a1,\$f14
+[ 0-9a-f]+: 54af 283b mtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 283b mtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 283b mtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 283b mtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 283b mtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 283b mtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 283b mtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 283b mtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 283b mtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 283b mtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 283b mtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 283b mtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 283b mtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 283b mtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 283b mtc1 a1,\$f29
+[ 0-9a-f]+: 54be 283b mtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 283b mtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 283b mtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 283b mtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 283b mtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 283b mtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 283b mtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 283b mtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 283b mtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 283b mtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 283b mtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 283b mtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 283b mtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 283b mtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 283b mtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 283b mtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 283b mtc1 a1,\$f14
+[ 0-9a-f]+: 54af 283b mtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 283b mtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 283b mtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 283b mtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 283b mtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 283b mtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 283b mtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 283b mtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 283b mtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 283b mtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 283b mtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 283b mtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 283b mtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 283b mtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 283b mtc1 a1,\$f29
+[ 0-9a-f]+: 54be 283b mtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 283b mtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 383b mthc1 a1,\$f0
+[ 0-9a-f]+: 54a1 383b mthc1 a1,\$f1
+[ 0-9a-f]+: 54a2 383b mthc1 a1,\$f2
+[ 0-9a-f]+: 54a3 383b mthc1 a1,\$f3
+[ 0-9a-f]+: 54a4 383b mthc1 a1,\$f4
+[ 0-9a-f]+: 54a5 383b mthc1 a1,\$f5
+[ 0-9a-f]+: 54a6 383b mthc1 a1,\$f6
+[ 0-9a-f]+: 54a7 383b mthc1 a1,\$f7
+[ 0-9a-f]+: 54a8 383b mthc1 a1,\$f8
+[ 0-9a-f]+: 54a9 383b mthc1 a1,\$f9
+[ 0-9a-f]+: 54aa 383b mthc1 a1,\$f10
+[ 0-9a-f]+: 54ab 383b mthc1 a1,\$f11
+[ 0-9a-f]+: 54ac 383b mthc1 a1,\$f12
+[ 0-9a-f]+: 54ad 383b mthc1 a1,\$f13
+[ 0-9a-f]+: 54ae 383b mthc1 a1,\$f14
+[ 0-9a-f]+: 54af 383b mthc1 a1,\$f15
+[ 0-9a-f]+: 54b0 383b mthc1 a1,\$f16
+[ 0-9a-f]+: 54b1 383b mthc1 a1,\$f17
+[ 0-9a-f]+: 54b2 383b mthc1 a1,\$f18
+[ 0-9a-f]+: 54b3 383b mthc1 a1,\$f19
+[ 0-9a-f]+: 54b4 383b mthc1 a1,\$f20
+[ 0-9a-f]+: 54b5 383b mthc1 a1,\$f21
+[ 0-9a-f]+: 54b6 383b mthc1 a1,\$f22
+[ 0-9a-f]+: 54b7 383b mthc1 a1,\$f23
+[ 0-9a-f]+: 54b8 383b mthc1 a1,\$f24
+[ 0-9a-f]+: 54b9 383b mthc1 a1,\$f25
+[ 0-9a-f]+: 54ba 383b mthc1 a1,\$f26
+[ 0-9a-f]+: 54bb 383b mthc1 a1,\$f27
+[ 0-9a-f]+: 54bc 383b mthc1 a1,\$f28
+[ 0-9a-f]+: 54bd 383b mthc1 a1,\$f29
+[ 0-9a-f]+: 54be 383b mthc1 a1,\$f30
+[ 0-9a-f]+: 54bf 383b mthc1 a1,\$f31
+[ 0-9a-f]+: 54a0 383b mthc1 a1,\$f0
+[ 0-9a-f]+: 54a1 383b mthc1 a1,\$f1
+[ 0-9a-f]+: 54a2 383b mthc1 a1,\$f2
+[ 0-9a-f]+: 54a3 383b mthc1 a1,\$f3
+[ 0-9a-f]+: 54a4 383b mthc1 a1,\$f4
+[ 0-9a-f]+: 54a5 383b mthc1 a1,\$f5
+[ 0-9a-f]+: 54a6 383b mthc1 a1,\$f6
+[ 0-9a-f]+: 54a7 383b mthc1 a1,\$f7
+[ 0-9a-f]+: 54a8 383b mthc1 a1,\$f8
+[ 0-9a-f]+: 54a9 383b mthc1 a1,\$f9
+[ 0-9a-f]+: 54aa 383b mthc1 a1,\$f10
+[ 0-9a-f]+: 54ab 383b mthc1 a1,\$f11
+[ 0-9a-f]+: 54ac 383b mthc1 a1,\$f12
+[ 0-9a-f]+: 54ad 383b mthc1 a1,\$f13
+[ 0-9a-f]+: 54ae 383b mthc1 a1,\$f14
+[ 0-9a-f]+: 54af 383b mthc1 a1,\$f15
+[ 0-9a-f]+: 54b0 383b mthc1 a1,\$f16
+[ 0-9a-f]+: 54b1 383b mthc1 a1,\$f17
+[ 0-9a-f]+: 54b2 383b mthc1 a1,\$f18
+[ 0-9a-f]+: 54b3 383b mthc1 a1,\$f19
+[ 0-9a-f]+: 54b4 383b mthc1 a1,\$f20
+[ 0-9a-f]+: 54b5 383b mthc1 a1,\$f21
+[ 0-9a-f]+: 54b6 383b mthc1 a1,\$f22
+[ 0-9a-f]+: 54b7 383b mthc1 a1,\$f23
+[ 0-9a-f]+: 54b8 383b mthc1 a1,\$f24
+[ 0-9a-f]+: 54b9 383b mthc1 a1,\$f25
+[ 0-9a-f]+: 54ba 383b mthc1 a1,\$f26
+[ 0-9a-f]+: 54bb 383b mthc1 a1,\$f27
+[ 0-9a-f]+: 54bc 383b mthc1 a1,\$f28
+[ 0-9a-f]+: 54bd 383b mthc1 a1,\$f29
+[ 0-9a-f]+: 54be 383b mthc1 a1,\$f30
+[ 0-9a-f]+: 54bf 383b mthc1 a1,\$f31
+[ 0-9a-f]+: 5441 00b0 mul\.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e8b0 mul\.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e8b0 mul\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e8b0 mul\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 01b0 mul\.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e9b0 mul\.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e9b0 mul\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e9b0 mul\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 02b0 mul\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe eab0 mul\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd eab0 mul\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd eab0 mul\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5401 0b7b neg\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 0b7b neg\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 0b7b neg\.s \$f2,\$f2
+[ 0-9a-f]+: 5442 0b7b neg\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 2b7b neg\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 2b7b neg\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 2b7b neg\.d \$f2,\$f2
+[ 0-9a-f]+: 5442 2b7b neg\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 4b7b neg\.ps \$f0,\$f1
+[ 0-9a-f]+: 57df 4b7b neg\.ps \$f30,\$f31
+[ 0-9a-f]+: 5442 4b7b neg\.ps \$f2,\$f2
+[ 0-9a-f]+: 5442 4b7b neg\.ps \$f2,\$f2
+[ 0-9a-f]+: 5462 004a nmadd\.d \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e74a nmadd\.d \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0042 nmadd\.s \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e742 nmadd\.s \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0052 nmadd\.ps \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e752 nmadd\.ps \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 006a nmsub\.d \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e76a nmsub\.d \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0062 nmsub\.s \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e762 nmsub\.s \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0072 nmsub\.ps \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e772 nmsub\.ps \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5441 0080 pll\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e880 pll\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e880 pll\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e880 pll\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 00c0 plu\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e8c0 plu\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e8c0 plu\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e8c0 plu\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0100 pul\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e900 pul\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e900 pul\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e900 pul\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0140 puu\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e940 puu\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e940 puu\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e940 puu\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5401 123b recip\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 123b recip\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 123b recip\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 523b recip\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 523b recip\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 523b recip\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 333b round\.l\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 333b round\.l\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 333b round\.l\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 733b round\.l\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 733b round\.l\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 733b round\.l\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 3b3b round\.w\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 3b3b round\.w\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 3b3b round\.w\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 7b3b round\.w\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 7b3b round\.w\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 7b3b round\.w\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 023b rsqrt\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 023b rsqrt\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 023b rsqrt\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 423b rsqrt\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 423b rsqrt\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 423b rsqrt\.d \$f2,\$f2
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 ffff sdc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0001 sdc1 \$f3,1\(at\)
+[ 0-9a-f]+: b864 8001 sdc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 ffff sdc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 5678 sdc1 \$f3,22136\(at\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 ffff sdc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0001 sdc1 \$f3,1\(at\)
+[ 0-9a-f]+: b864 8001 sdc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 ffff sdc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 5678 sdc1 \$f3,22136\(at\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 5400 0108 sdxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 0108 sdxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 0108 sdxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 0108 sdxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 0108 sdxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 0908 sdxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 1108 sdxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f908 sdxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 5401 0a3b sqrt\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 0a3b sqrt\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 0a3b sqrt\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 4a3b sqrt\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 4a3b sqrt\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 4a3b sqrt\.d \$f2,\$f2
+[ 0-9a-f]+: 5441 0070 sub\.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e870 sub\.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e870 sub\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e870 sub\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0170 sub\.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e970 sub\.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e970 sub\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e970 sub\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0270 sub\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe ea70 sub\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd ea70 sub\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd ea70 sub\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5400 0188 suxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 0188 suxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 0188 suxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 0188 suxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 0188 suxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 0988 suxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 1188 suxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f988 suxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 5400 0048 lwxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 0048 lwxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 0048 lwxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 0048 lwxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 0048 lwxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 0848 lwxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 1048 lwxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f848 lwxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 5401 233b trunc\.l\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 233b trunc\.l\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 233b trunc\.l\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 633b trunc\.l\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 633b trunc\.l\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 633b trunc\.l\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 2b3b trunc\.w\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 2b3b trunc\.w\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 2b3b trunc\.w\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 6b3b trunc\.w\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 6b3b trunc\.w\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 6b3b trunc\.w\.d \$f2,\$f2
+[ 0-9a-f]+: 5443 017b movf v0,v1,\$fcc0
+[ 0-9a-f]+: 57df 017b movf s8,ra,\$fcc0
+[ 0-9a-f]+: 57df 217b movf s8,ra,\$fcc1
+[ 0-9a-f]+: 57df 417b movf s8,ra,\$fcc2
+[ 0-9a-f]+: 57df 617b movf s8,ra,\$fcc3
+[ 0-9a-f]+: 57df 817b movf s8,ra,\$fcc4
+[ 0-9a-f]+: 57df a17b movf s8,ra,\$fcc5
+[ 0-9a-f]+: 57df c17b movf s8,ra,\$fcc6
+[ 0-9a-f]+: 57df e17b movf s8,ra,\$fcc7
+[ 0-9a-f]+: 5443 097b movt v0,v1,\$fcc0
+[ 0-9a-f]+: 57df 097b movt s8,ra,\$fcc0
+[ 0-9a-f]+: 57df 297b movt s8,ra,\$fcc1
+[ 0-9a-f]+: 57df 497b movt s8,ra,\$fcc2
+[ 0-9a-f]+: 57df 697b movt s8,ra,\$fcc3
+[ 0-9a-f]+: 57df 897b movt s8,ra,\$fcc4
+[ 0-9a-f]+: 57df a97b movt s8,ra,\$fcc5
+[ 0-9a-f]+: 57df c97b movt s8,ra,\$fcc6
+[ 0-9a-f]+: 57df e97b movt s8,ra,\$fcc7
+[ 0-9a-f]+: 43a4 fffe bc1t \$fcc1,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4388 fffe bc1f \$fcc2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0107 3150 addu a2,a3,t0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 438c fffe bc1f \$fcc3,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 43b0 fffe bc1t \$fcc4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0107 3150 addu a2,a3,t0
+
+[0-9a-f]+ <test_mips64>:
+[ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <test_mips64>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c43 move v0,v1
+[ 0-9a-f]+: 5860 1190 dneg v0,v1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 5840 1190 dneg v0,v0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 5840 1190 dneg v0,v0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 5883 1110 dadd v0,v1,a0
+[ 0-9a-f]+: 5bfe e910 dadd sp,s8,ra
+[ 0-9a-f]+: 5862 1110 dadd v0,v0,v1
+[ 0-9a-f]+: 5862 1110 dadd v0,v0,v1
+[ 0-9a-f]+: 5843 001c daddi v0,v1,0
+[ 0-9a-f]+: 5843 005c daddi v0,v1,1
+[ 0-9a-f]+: 5843 801c daddi v0,v1,-512
+[ 0-9a-f]+: 5843 7fdc daddi v0,v1,511
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5821 8000 dsll at,at,0x10
+[ 0-9a-f]+: 5021 8765 ori at,at,0x8765
+[ 0-9a-f]+: 5821 8000 dsll at,at,0x10
+[ 0-9a-f]+: 5021 4321 ori at,at,0x4321
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 5843 001c daddi v0,v1,0
+[ 0-9a-f]+: 5843 005c daddi v0,v1,1
+[ 0-9a-f]+: 5843 801c daddi v0,v1,-512
+[ 0-9a-f]+: 5843 7fdc daddi v0,v1,511
+[ 0-9a-f]+: 5842 7fdc daddi v0,v0,511
+[ 0-9a-f]+: 5842 7fdc daddi v0,v0,511
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 5c43 0000 daddiu v0,v1,0
+[ 0-9a-f]+: 5c43 8000 daddiu v0,v1,-32768
+[ 0-9a-f]+: 5c43 7fff daddiu v0,v1,32767
+[ 0-9a-f]+: 5c42 7fff daddiu v0,v0,32767
+[ 0-9a-f]+: 5c42 7fff daddiu v0,v0,32767
+[ 0-9a-f]+: 5883 1150 daddu v0,v1,a0
+[ 0-9a-f]+: 5bfe e950 daddu sp,s8,ra
+[ 0-9a-f]+: 5862 1150 daddu v0,v0,v1
+[ 0-9a-f]+: 5862 1150 daddu v0,v0,v1
+[ 0-9a-f]+: 5803 1150 move v0,v1
+[ 0-9a-f]+: 5c43 0000 daddiu v0,v1,0
+[ 0-9a-f]+: 5c43 0001 daddiu v0,v1,1
+[ 0-9a-f]+: 5c43 7fff daddiu v0,v1,32767
+[ 0-9a-f]+: 5c43 8000 daddiu v0,v1,-32768
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 5823 1150 daddu v0,v1,at
+[ 0-9a-f]+: 5843 4b3c dclo v0,v1
+[ 0-9a-f]+: 5862 4b3c dclo v1,v0
+[ 0-9a-f]+: 5843 5b3c dclz v0,v1
+[ 0-9a-f]+: 5862 5b3c dclz v1,v0
+[ 0-9a-f]+: 5862 ab3c ddiv zero,v0,v1
+[ 0-9a-f]+: 5bfe ab3c ddiv zero,s8,ra
+[ 0-9a-f]+: 5860 ab3c ddiv zero,zero,v1
+[ 0-9a-f]+: 5be0 ab3c ddiv zero,zero,ra
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0004 703c teq a0,zero,0x7
+[ 0-9a-f]+: 5883 ab3c ddiv zero,v1,a0
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b424 fffe bne a0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 5821 f808 dsll32 at,at,0x1f
+[ 0-9a-f]+: 0023 603c teq v1,at,0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 5880 1990 dneg v1,a0
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 5824 ab3c ddiv zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 5862 bb3c ddivu zero,v0,v1
+[ 0-9a-f]+: 5bfe bb3c ddivu zero,s8,ra
+[ 0-9a-f]+: 5860 bb3c ddivu zero,zero,v1
+[ 0-9a-f]+: 5be0 bb3c ddivu zero,zero,ra
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 5803 bb3c ddivu zero,v1,zero
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0004 703c teq a0,zero,0x7
+[ 0-9a-f]+: 5883 bb3c ddivu zero,v1,a0
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 5824 bb3c ddivu zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 5824 bb3c ddivu zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 5843 07ec dext v0,v1,0x1f,0x1
+[ 0-9a-f]+: 5843 f82c dext v0,v1,0x0,0x20
+[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa
+[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa
+[ 0-9a-f]+: 5843 ffcc dins v0,v1,0x1f,0x1
+[ 0-9a-f]+: 5843 f80c dins v0,v1,0x0,0x20
+[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa
+[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa
+[ 0-9a-f]+: 41a2 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 41a2 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 3040 7fff li v0,32767
+[ 0-9a-f]+: 5040 ffff li v0,0xffff
+[ 0-9a-f]+: 41a2 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5678 ori v0,v0,0x5678
+[ 0-9a-f]+: 5840 00fc dmfc0 v0,c0_index
+[ 0-9a-f]+: 5841 00fc dmfc0 v0,c0_random
+[ 0-9a-f]+: 5842 00fc dmfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5843 00fc dmfc0 v0,c0_entrylo1
+[ 0-9a-f]+: 5844 00fc dmfc0 v0,c0_context
+[ 0-9a-f]+: 5845 00fc dmfc0 v0,c0_pagemask
+[ 0-9a-f]+: 5846 00fc dmfc0 v0,c0_wired
+[ 0-9a-f]+: 5847 00fc dmfc0 v0,c0_hwrena
+[ 0-9a-f]+: 5848 00fc dmfc0 v0,c0_badvaddr
+[ 0-9a-f]+: 5849 00fc dmfc0 v0,c0_count
+[ 0-9a-f]+: 584a 00fc dmfc0 v0,c0_entryhi
+[ 0-9a-f]+: 584b 00fc dmfc0 v0,c0_compare
+[ 0-9a-f]+: 584c 00fc dmfc0 v0,c0_status
+[ 0-9a-f]+: 584d 00fc dmfc0 v0,c0_cause
+[ 0-9a-f]+: 584e 00fc dmfc0 v0,c0_epc
+[ 0-9a-f]+: 584f 00fc dmfc0 v0,c0_prid
+[ 0-9a-f]+: 5850 00fc dmfc0 v0,c0_config
+[ 0-9a-f]+: 5851 00fc dmfc0 v0,c0_lladdr
+[ 0-9a-f]+: 5852 00fc dmfc0 v0,c0_watchlo
+[ 0-9a-f]+: 5853 00fc dmfc0 v0,c0_watchhi
+[ 0-9a-f]+: 5854 00fc dmfc0 v0,c0_xcontext
+[ 0-9a-f]+: 5855 00fc dmfc0 v0,\$21
+[ 0-9a-f]+: 5856 00fc dmfc0 v0,\$22
+[ 0-9a-f]+: 5857 00fc dmfc0 v0,c0_debug
+[ 0-9a-f]+: 5858 00fc dmfc0 v0,c0_depc
+[ 0-9a-f]+: 5859 00fc dmfc0 v0,c0_perfcnt
+[ 0-9a-f]+: 585a 00fc dmfc0 v0,c0_errctl
+[ 0-9a-f]+: 585b 00fc dmfc0 v0,c0_cacheerr
+[ 0-9a-f]+: 585c 00fc dmfc0 v0,c0_taglo
+[ 0-9a-f]+: 585d 00fc dmfc0 v0,c0_taghi
+[ 0-9a-f]+: 585e 00fc dmfc0 v0,c0_errorepc
+[ 0-9a-f]+: 585f 00fc dmfc0 v0,c0_desave
+[ 0-9a-f]+: 5840 00fc dmfc0 v0,c0_index
+[ 0-9a-f]+: 5840 08fc dmfc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 5840 10fc dmfc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 5840 18fc dmfc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 5840 20fc dmfc0 v0,\$0,4
+[ 0-9a-f]+: 5840 28fc dmfc0 v0,\$0,5
+[ 0-9a-f]+: 5840 30fc dmfc0 v0,\$0,6
+[ 0-9a-f]+: 5840 38fc dmfc0 v0,\$0,7
+[ 0-9a-f]+: 5841 00fc dmfc0 v0,c0_random
+[ 0-9a-f]+: 5841 08fc dmfc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 5841 10fc dmfc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 5841 18fc dmfc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 5841 20fc dmfc0 v0,c0_yqmask
+[ 0-9a-f]+: 5841 28fc dmfc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 5841 30fc dmfc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 5841 38fc dmfc0 v0,\$1,7
+[ 0-9a-f]+: 5842 00fc dmfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5842 08fc dmfc0 v0,c0_tcstatus
+[ 0-9a-f]+: 5842 10fc dmfc0 v0,c0_tcbind
+[ 0-9a-f]+: 5842 18fc dmfc0 v0,c0_tcrestart
+[ 0-9a-f]+: 5842 20fc dmfc0 v0,c0_tchalt
+[ 0-9a-f]+: 5842 28fc dmfc0 v0,c0_tccontext
+[ 0-9a-f]+: 5842 30fc dmfc0 v0,c0_tcschedule
+[ 0-9a-f]+: 5842 38fc dmfc0 v0,c0_tcschefback
+[ 0-9a-f]+: 5840 02fc dmtc0 v0,c0_index
+[ 0-9a-f]+: 5841 02fc dmtc0 v0,c0_random
+[ 0-9a-f]+: 5842 02fc dmtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5843 02fc dmtc0 v0,c0_entrylo1
+[ 0-9a-f]+: 5844 02fc dmtc0 v0,c0_context
+[ 0-9a-f]+: 5845 02fc dmtc0 v0,c0_pagemask
+[ 0-9a-f]+: 5846 02fc dmtc0 v0,c0_wired
+[ 0-9a-f]+: 5847 02fc dmtc0 v0,c0_hwrena
+[ 0-9a-f]+: 5848 02fc dmtc0 v0,c0_badvaddr
+[ 0-9a-f]+: 5849 02fc dmtc0 v0,c0_count
+[ 0-9a-f]+: 584a 02fc dmtc0 v0,c0_entryhi
+[ 0-9a-f]+: 584b 02fc dmtc0 v0,c0_compare
+[ 0-9a-f]+: 584c 02fc dmtc0 v0,c0_status
+[ 0-9a-f]+: 584d 02fc dmtc0 v0,c0_cause
+[ 0-9a-f]+: 584e 02fc dmtc0 v0,c0_epc
+[ 0-9a-f]+: 584f 02fc dmtc0 v0,c0_prid
+[ 0-9a-f]+: 5850 02fc dmtc0 v0,c0_config
+[ 0-9a-f]+: 5851 02fc dmtc0 v0,c0_lladdr
+[ 0-9a-f]+: 5852 02fc dmtc0 v0,c0_watchlo
+[ 0-9a-f]+: 5853 02fc dmtc0 v0,c0_watchhi
+[ 0-9a-f]+: 5854 02fc dmtc0 v0,c0_xcontext
+[ 0-9a-f]+: 5855 02fc dmtc0 v0,\$21
+[ 0-9a-f]+: 5856 02fc dmtc0 v0,\$22
+[ 0-9a-f]+: 5857 02fc dmtc0 v0,c0_debug
+[ 0-9a-f]+: 5858 02fc dmtc0 v0,c0_depc
+[ 0-9a-f]+: 5859 02fc dmtc0 v0,c0_perfcnt
+[ 0-9a-f]+: 585a 02fc dmtc0 v0,c0_errctl
+[ 0-9a-f]+: 585b 02fc dmtc0 v0,c0_cacheerr
+[ 0-9a-f]+: 585c 02fc dmtc0 v0,c0_taglo
+[ 0-9a-f]+: 585d 02fc dmtc0 v0,c0_taghi
+[ 0-9a-f]+: 585e 02fc dmtc0 v0,c0_errorepc
+[ 0-9a-f]+: 585f 02fc dmtc0 v0,c0_desave
+[ 0-9a-f]+: 5840 02fc dmtc0 v0,c0_index
+[ 0-9a-f]+: 5840 0afc dmtc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 5840 12fc dmtc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 5840 1afc dmtc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 5840 22fc dmtc0 v0,\$0,4
+[ 0-9a-f]+: 5840 2afc dmtc0 v0,\$0,5
+[ 0-9a-f]+: 5840 32fc dmtc0 v0,\$0,6
+[ 0-9a-f]+: 5840 3afc dmtc0 v0,\$0,7
+[ 0-9a-f]+: 5841 02fc dmtc0 v0,c0_random
+[ 0-9a-f]+: 5841 0afc dmtc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 5841 12fc dmtc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 5841 1afc dmtc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 5841 22fc dmtc0 v0,c0_yqmask
+[ 0-9a-f]+: 5841 2afc dmtc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 5841 32fc dmtc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 5841 3afc dmtc0 v0,\$1,7
+[ 0-9a-f]+: 5842 02fc dmtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5842 0afc dmtc0 v0,c0_tcstatus
+[ 0-9a-f]+: 5842 12fc dmtc0 v0,c0_tcbind
+[ 0-9a-f]+: 5842 1afc dmtc0 v0,c0_tcrestart
+[ 0-9a-f]+: 5842 22fc dmtc0 v0,c0_tchalt
+[ 0-9a-f]+: 5842 2afc dmtc0 v0,c0_tccontext
+[ 0-9a-f]+: 5842 32fc dmtc0 v0,c0_tcschedule
+[ 0-9a-f]+: 5842 3afc dmtc0 v0,c0_tcschefback
+[ 0-9a-f]+: 54a0 243b dmfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 243b dmfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 243b dmfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 243b dmfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 243b dmfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 243b dmfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 243b dmfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 243b dmfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 243b dmfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 243b dmfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 243b dmfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 243b dmfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 243b dmfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 243b dmfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 243b dmfc1 a1,\$f14
+[ 0-9a-f]+: 54af 243b dmfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 243b dmfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 243b dmfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 243b dmfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 243b dmfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 243b dmfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 243b dmfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 243b dmfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 243b dmfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 243b dmfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 243b dmfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 243b dmfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 243b dmfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 243b dmfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
+[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 243b dmfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 243b dmfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 243b dmfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 243b dmfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 243b dmfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 243b dmfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 243b dmfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 243b dmfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 243b dmfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 243b dmfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 243b dmfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 243b dmfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 243b dmfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 243b dmfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 243b dmfc1 a1,\$f14
+[ 0-9a-f]+: 54af 243b dmfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 243b dmfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 243b dmfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 243b dmfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 243b dmfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 243b dmfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 243b dmfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 243b dmfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 243b dmfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 243b dmfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 243b dmfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 243b dmfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 243b dmfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 243b dmfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
+[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31
+[ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0
+[ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1
+[ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2
+[ 0-9a-f]+: 0043 6d3c dmfc2 v0,\$3
+[ 0-9a-f]+: 0044 6d3c dmfc2 v0,\$4
+[ 0-9a-f]+: 0045 6d3c dmfc2 v0,\$5
+[ 0-9a-f]+: 0046 6d3c dmfc2 v0,\$6
+[ 0-9a-f]+: 0047 6d3c dmfc2 v0,\$7
+[ 0-9a-f]+: 0048 6d3c dmfc2 v0,\$8
+[ 0-9a-f]+: 0049 6d3c dmfc2 v0,\$9
+[ 0-9a-f]+: 004a 6d3c dmfc2 v0,\$10
+[ 0-9a-f]+: 004b 6d3c dmfc2 v0,\$11
+[ 0-9a-f]+: 004c 6d3c dmfc2 v0,\$12
+[ 0-9a-f]+: 004d 6d3c dmfc2 v0,\$13
+[ 0-9a-f]+: 004e 6d3c dmfc2 v0,\$14
+[ 0-9a-f]+: 004f 6d3c dmfc2 v0,\$15
+[ 0-9a-f]+: 0050 6d3c dmfc2 v0,\$16
+[ 0-9a-f]+: 0051 6d3c dmfc2 v0,\$17
+[ 0-9a-f]+: 0052 6d3c dmfc2 v0,\$18
+[ 0-9a-f]+: 0053 6d3c dmfc2 v0,\$19
+[ 0-9a-f]+: 0054 6d3c dmfc2 v0,\$20
+[ 0-9a-f]+: 0055 6d3c dmfc2 v0,\$21
+[ 0-9a-f]+: 0056 6d3c dmfc2 v0,\$22
+[ 0-9a-f]+: 0057 6d3c dmfc2 v0,\$23
+[ 0-9a-f]+: 0058 6d3c dmfc2 v0,\$24
+[ 0-9a-f]+: 0059 6d3c dmfc2 v0,\$25
+[ 0-9a-f]+: 005a 6d3c dmfc2 v0,\$26
+[ 0-9a-f]+: 005b 6d3c dmfc2 v0,\$27
+[ 0-9a-f]+: 005c 6d3c dmfc2 v0,\$28
+[ 0-9a-f]+: 005d 6d3c dmfc2 v0,\$29
+[ 0-9a-f]+: 005e 6d3c dmfc2 v0,\$30
+[ 0-9a-f]+: 005f 6d3c dmfc2 v0,\$31
+[ 0-9a-f]+: 0040 7d3c dmtc2 v0,\$0
+[ 0-9a-f]+: 0041 7d3c dmtc2 v0,\$1
+[ 0-9a-f]+: 0042 7d3c dmtc2 v0,\$2
+[ 0-9a-f]+: 0043 7d3c dmtc2 v0,\$3
+[ 0-9a-f]+: 0044 7d3c dmtc2 v0,\$4
+[ 0-9a-f]+: 0045 7d3c dmtc2 v0,\$5
+[ 0-9a-f]+: 0046 7d3c dmtc2 v0,\$6
+[ 0-9a-f]+: 0047 7d3c dmtc2 v0,\$7
+[ 0-9a-f]+: 0048 7d3c dmtc2 v0,\$8
+[ 0-9a-f]+: 0049 7d3c dmtc2 v0,\$9
+[ 0-9a-f]+: 004a 7d3c dmtc2 v0,\$10
+[ 0-9a-f]+: 004b 7d3c dmtc2 v0,\$11
+[ 0-9a-f]+: 004c 7d3c dmtc2 v0,\$12
+[ 0-9a-f]+: 004d 7d3c dmtc2 v0,\$13
+[ 0-9a-f]+: 004e 7d3c dmtc2 v0,\$14
+[ 0-9a-f]+: 004f 7d3c dmtc2 v0,\$15
+[ 0-9a-f]+: 0050 7d3c dmtc2 v0,\$16
+[ 0-9a-f]+: 0051 7d3c dmtc2 v0,\$17
+[ 0-9a-f]+: 0052 7d3c dmtc2 v0,\$18
+[ 0-9a-f]+: 0053 7d3c dmtc2 v0,\$19
+[ 0-9a-f]+: 0054 7d3c dmtc2 v0,\$20
+[ 0-9a-f]+: 0055 7d3c dmtc2 v0,\$21
+[ 0-9a-f]+: 0056 7d3c dmtc2 v0,\$22
+[ 0-9a-f]+: 0057 7d3c dmtc2 v0,\$23
+[ 0-9a-f]+: 0058 7d3c dmtc2 v0,\$24
+[ 0-9a-f]+: 0059 7d3c dmtc2 v0,\$25
+[ 0-9a-f]+: 005a 7d3c dmtc2 v0,\$26
+[ 0-9a-f]+: 005b 7d3c dmtc2 v0,\$27
+[ 0-9a-f]+: 005c 7d3c dmtc2 v0,\$28
+[ 0-9a-f]+: 005d 7d3c dmtc2 v0,\$29
+[ 0-9a-f]+: 005e 7d3c dmtc2 v0,\$30
+[ 0-9a-f]+: 005f 7d3c dmtc2 v0,\$31
+[ 0-9a-f]+: 5862 8b3c dmult v0,v1
+[ 0-9a-f]+: 5862 9b3c dmultu v0,v1
+[ 0-9a-f]+: 5883 9b3c dmultu v1,a0
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 8b3c dmult v1,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 5883 8b3c dmult v1,a0
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 5842 f888 dsra32 v0,v0,0x1f
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 0022 6c3c tne v0,at,0x6
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 3020 0004 li at,4
+[ 0-9a-f]+: 5823 8b3c dmult v1,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 5842 f888 dsra32 v0,v0,0x1f
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 0022 6c3c tne v0,at,0x6
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 5883 9b3c dmultu v1,a0
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0001 6c3c tne at,zero,0x6
+[ 0-9a-f]+: 3020 0004 li at,4
+[ 0-9a-f]+: 5823 9b3c dmultu v1,at
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0001 6c3c tne at,zero,0x6
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 5824 ab3c ddiv zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 5862 ab3c ddiv zero,v0,v1
+[ 0-9a-f]+: 5bfe ab3c ddiv zero,s8,ra
+[ 0-9a-f]+: 0003 703c teq v1,zero,0x7
+[ 0-9a-f]+: 5860 ab3c ddiv zero,zero,v1
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b423 fffe bne v1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 5821 f808 dsll32 at,at,0x1f
+[ 0-9a-f]+: 0020 603c teq zero,at,0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 001f 703c teq ra,zero,0x7
+[ 0-9a-f]+: 5be0 ab3c ddiv zero,zero,ra
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b43f fffe bne ra,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 5821 f808 dsll32 at,at,0x1f
+[ 0-9a-f]+: 0020 603c teq zero,at,0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 5824 ab3c ddiv zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 5862 bb3c ddivu zero,v0,v1
+[ 0-9a-f]+: 5bfe bb3c ddivu zero,s8,ra
+[ 0-9a-f]+: 0003 703c teq v1,zero,0x7
+[ 0-9a-f]+: 5860 bb3c ddivu zero,zero,v1
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 001f 703c teq ra,zero,0x7
+[ 0-9a-f]+: 5be0 bb3c ddivu zero,zero,ra
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 0000 703c teq zero,zero,0x7
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 5824 bb3c ddivu zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 5824 bb3c ddivu zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 5880 11d0 dnegu v0,a0
+[ 0-9a-f]+: 5862 10d0 drorv v0,v1,v0
+[ 0-9a-f]+: 5880 09d0 dnegu at,a0
+[ 0-9a-f]+: 5841 10d0 drorv v0,v0,at
+[ 0-9a-f]+: 5843 e0c8 dror32 v0,v1,0x1c
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c0 dror v0,v1,0x4
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5880 11d0 dnegu v0,a0
+[ 0-9a-f]+: 5862 10d0 drorv v0,v1,v0
+[ 0-9a-f]+: 5880 09d0 dnegu at,a0
+[ 0-9a-f]+: 5841 10d0 drorv v0,v0,at
+[ 0-9a-f]+: 5843 e0c8 dror32 v0,v1,0x1c
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c0 dror v0,v1,0x4
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5843 7b3c dsbh v0,v1
+[ 0-9a-f]+: 5842 7b3c dsbh v0,v0
+[ 0-9a-f]+: 5842 7b3c dsbh v0,v0
+[ 0-9a-f]+: 5843 fb3c dshd v0,v1
+[ 0-9a-f]+: 5842 fb3c dshd v0,v0
+[ 0-9a-f]+: 5842 fb3c dshd v0,v0
+[ 0-9a-f]+: 5864 1010 dsllv v0,v1,a0
+[ 0-9a-f]+: 5843 f808 dsll32 v0,v1,0x1f
+[ 0-9a-f]+: 5864 1010 dsllv v0,v1,a0
+[ 0-9a-f]+: 5843 f808 dsll32 v0,v1,0x1f
+[ 0-9a-f]+: 5843 f800 dsll v0,v1,0x1f
+[ 0-9a-f]+: 5864 1090 dsrav v0,v1,a0
+[ 0-9a-f]+: 5843 2088 dsra32 v0,v1,0x4
+[ 0-9a-f]+: 5864 1090 dsrav v0,v1,a0
+[ 0-9a-f]+: 5843 2088 dsra32 v0,v1,0x4
+[ 0-9a-f]+: 5843 2080 dsra v0,v1,0x4
+[ 0-9a-f]+: 5864 1050 dsrlv v0,v1,a0
+[ 0-9a-f]+: 5843 f848 dsrl32 v0,v1,0x1f
+[ 0-9a-f]+: 5864 1050 dsrlv v0,v1,a0
+[ 0-9a-f]+: 5843 2048 dsrl32 v0,v1,0x4
+[ 0-9a-f]+: 5843 2040 dsrl v0,v1,0x4
+[ 0-9a-f]+: 5883 1190 dsub v0,v1,a0
+[ 0-9a-f]+: 5bfe e990 dsub sp,s8,ra
+[ 0-9a-f]+: 5862 1190 dsub v0,v0,v1
+[ 0-9a-f]+: 5862 1190 dsub v0,v0,v1
+[ 0-9a-f]+: 5883 11d0 dsubu v0,v1,a0
+[ 0-9a-f]+: 5bfe e9d0 dsubu sp,s8,ra
+[ 0-9a-f]+: 5862 11d0 dsubu v0,v0,v1
+[ 0-9a-f]+: 5862 11d0 dsubu v0,v0,v1
+[ 0-9a-f]+: 5c43 edcc daddiu v0,v1,-4660
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 11d0 dsubu v0,v1,at
+[ 0-9a-f]+: 5843 001c daddi v0,v1,0
+[ 0-9a-f]+: 5843 ffdc daddi v0,v1,-1
+[ 0-9a-f]+: 5843 801c daddi v0,v1,-512
+[ 0-9a-f]+: 5843 7fdc daddi v0,v1,511
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 5823 1190 dsub v0,v1,at
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 5823 1190 dsub v0,v1,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 5823 1190 dsub v0,v1,at
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 1190 dsub v0,v1,at
+[ 0-9a-f]+: 41a1 8888 lui at,0x8888
+[ 0-9a-f]+: 5021 1111 ori at,at,0x1111
+[ 0-9a-f]+: 5821 8000 dsll at,at,0x10
+[ 0-9a-f]+: 5021 1234 ori at,at,0x1234
+[ 0-9a-f]+: 5821 8000 dsll at,at,0x10
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 1190 dsub v0,v1,at
+[ 0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ 0-9a-f]+: dc40 0004 ld v0,4\(zero\)
+[ 0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ 0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ 0-9a-f]+: dc40 0004 ld v0,4\(zero\)
+[ 0-9a-f]+: dc43 0004 ld v0,4\(v1\)
+[ 0-9a-f]+: dc43 8000 ld v0,-32768\(v1\)
+[ 0-9a-f]+: dc43 7fff ld v0,32767\(v1\)
+[ 0-9a-f]+: 6040 4000 ldl v0,0\(zero\)
+[ 0-9a-f]+: 6040 4004 ldl v0,4\(zero\)
+[ 0-9a-f]+: 6040 4000 ldl v0,0\(zero\)
+[ 0-9a-f]+: 6040 4000 ldl v0,0\(zero\)
+[ 0-9a-f]+: 6040 4004 ldl v0,4\(zero\)
+[ 0-9a-f]+: 6043 4004 ldl v0,4\(v1\)
+[ 0-9a-f]+: 6043 4e00 ldl v0,-512\(v1\)
+[ 0-9a-f]+: 6043 41ff ldl v0,511\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 4000 ldl v0,0\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 4678 ldl v0,1656\(at\)
+[ 0-9a-f]+: 6040 5000 ldr v0,0\(zero\)
+[ 0-9a-f]+: 6040 5004 ldr v0,4\(zero\)
+[ 0-9a-f]+: 6040 5000 ldr v0,0\(zero\)
+[ 0-9a-f]+: 6040 5000 ldr v0,0\(zero\)
+[ 0-9a-f]+: 6040 5004 ldr v0,4\(zero\)
+[ 0-9a-f]+: 6043 5004 ldr v0,4\(v1\)
+[ 0-9a-f]+: 6043 5e00 ldr v0,-512\(v1\)
+[ 0-9a-f]+: 6043 51ff ldr v0,511\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 5000 ldr v0,0\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 5678 ldr v0,1656\(at\)
+[ 0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ 0-9a-f]+: 6040 7004 lld v0,4\(zero\)
+[ 0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ 0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ 0-9a-f]+: 6040 7004 lld v0,4\(zero\)
+[ 0-9a-f]+: 6043 7004 lld v0,4\(v1\)
+[ 0-9a-f]+: 6043 7e00 lld v0,-512\(v1\)
+[ 0-9a-f]+: 6043 71ff lld v0,511\(v1\)
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ 0-9a-f]+: 6042 7000 lld v0,0\(v0\)
+[ 0-9a-f]+: 41a2 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5000 ori v0,v0,0x5000
+[ 0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ 0-9a-f]+: 6042 7678 lld v0,1656\(v0\)
+[ 0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ 0-9a-f]+: 6040 e004 lwu v0,4\(zero\)
+[ 0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ 0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ 0-9a-f]+: 6040 e004 lwu v0,4\(zero\)
+[ 0-9a-f]+: 6043 e004 lwu v0,4\(v1\)
+[ 0-9a-f]+: 6043 ee00 lwu v0,-512\(v1\)
+[ 0-9a-f]+: 6043 e1ff lwu v0,511\(v1\)
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ 0-9a-f]+: 6042 e000 lwu v0,0\(v0\)
+[ 0-9a-f]+: 41a2 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5000 ori v0,v0,0x5000
+[ 0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ 0-9a-f]+: 6042 e678 lwu v0,1656\(v0\)
+[ 0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ 0-9a-f]+: 6040 f004 scd v0,4\(zero\)
+[ 0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ 0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ 0-9a-f]+: 6040 f004 scd v0,4\(zero\)
+[ 0-9a-f]+: 6043 f004 scd v0,4\(v1\)
+[ 0-9a-f]+: 6043 fe00 scd v0,-512\(v1\)
+[ 0-9a-f]+: 6043 f1ff scd v0,511\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 f000 scd v0,0\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 f678 scd v0,1656\(at\)
+[ 0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ 0-9a-f]+: d840 0004 sd v0,4\(zero\)
+[ 0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ 0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ 0-9a-f]+: d840 0004 sd v0,4\(zero\)
+[ 0-9a-f]+: d843 0004 sd v0,4\(v1\)
+[ 0-9a-f]+: d843 8000 sd v0,-32768\(v1\)
+[ 0-9a-f]+: d843 7fff sd v0,32767\(v1\)
+[ 0-9a-f]+: 6040 c000 sdl v0,0\(zero\)
+[ 0-9a-f]+: 6040 c004 sdl v0,4\(zero\)
+[ 0-9a-f]+: 6040 c000 sdl v0,0\(zero\)
+[ 0-9a-f]+: 6040 c000 sdl v0,0\(zero\)
+[ 0-9a-f]+: 6040 c004 sdl v0,4\(zero\)
+[ 0-9a-f]+: 6043 c004 sdl v0,4\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 c000 sdl v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 cfff sdl v0,-1\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 c678 sdl v0,1656\(at\)
+[ 0-9a-f]+: 6040 d000 sdr v0,0\(zero\)
+[ 0-9a-f]+: 6040 d004 sdr v0,4\(zero\)
+[ 0-9a-f]+: 6040 d000 sdr v0,0\(zero\)
+[ 0-9a-f]+: 6040 d000 sdr v0,0\(zero\)
+[ 0-9a-f]+: 6040 d004 sdr v0,4\(zero\)
+[ 0-9a-f]+: 6043 d004 sdr v0,4\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 d000 sdr v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 dfff sdr v0,-1\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 d678 sdr v0,1656\(at\)
+[ 0-9a-f]+: 2020 7000 ldm s0,0\(zero\)
+[ 0-9a-f]+: 2020 7004 ldm s0,4\(zero\)
+[ 0-9a-f]+: 2025 7000 ldm s0,0\(a1\)
+[ 0-9a-f]+: 2025 77ff ldm s0,2047\(a1\)
+[ 0-9a-f]+: 2045 77ff ldm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 77ff ldm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 77ff ldm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 77ff ldm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 77ff ldm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 77ff ldm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 77ff ldm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 77ff ldm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 77ff ldm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 7000 ldm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 7000 ldm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 7000 ldm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 7000 ldm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 7000 ldm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 7000 ldm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 7000 ldm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 7000 ldm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 7000 ldm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ 0-9a-f]+: 2020 7000 ldm s0,0\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ 0-9a-f]+: 203d 7000 ldm s0,0\(sp\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 7678 ldm s0,1656\(at\)
+[ 0-9a-f]+: 2040 4000 ldp v0,0\(zero\)
+[ 0-9a-f]+: 2040 4004 ldp v0,4\(zero\)
+[ 0-9a-f]+: 205d 4000 ldp v0,0\(sp\)
+[ 0-9a-f]+: 205d 4000 ldp v0,0\(sp\)
+[ 0-9a-f]+: 2043 4800 ldp v0,-2048\(v1\)
+[ 0-9a-f]+: 2043 47ff ldp v0,2047\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 4000 ldp v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 4fff ldp v0,-1\(at\)
+[ 0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 4fff ldp v0,-1\(at\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
+[ 0-9a-f]+: 5060 8000 li v1,0x8000
+[ 0-9a-f]+: 2043 4fff ldp v0,-1\(v1\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 2043 4fff ldp v0,-1\(v1\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 5063 5000 ori v1,v1,0x5000
+[ 0-9a-f]+: 2043 4678 ldp v0,1656\(v1\)
+[ 0-9a-f]+: 2020 f000 sdm s0,0\(zero\)
+[ 0-9a-f]+: 2020 f004 sdm s0,4\(zero\)
+[ 0-9a-f]+: 2025 f000 sdm s0,0\(a1\)
+[ 0-9a-f]+: 2025 f7ff sdm s0,2047\(a1\)
+[ 0-9a-f]+: 2045 f7ff sdm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 f7ff sdm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 f7ff sdm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 f7ff sdm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 f7ff sdm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 f7ff sdm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 f7ff sdm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 f7ff sdm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 f7ff sdm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 f000 sdm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 f000 sdm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 f000 sdm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 f000 sdm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 f000 sdm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 f000 sdm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 f000 sdm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 f000 sdm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 f000 sdm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ 0-9a-f]+: 2020 f000 sdm s0,0\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ 0-9a-f]+: 203d f000 sdm s0,0\(sp\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 f678 sdm s0,1656\(at\)
+[ 0-9a-f]+: 2040 c000 sdp v0,0\(zero\)
+[ 0-9a-f]+: 2040 c004 sdp v0,4\(zero\)
+[ 0-9a-f]+: 205d c000 sdp v0,0\(sp\)
+[ 0-9a-f]+: 205d c000 sdp v0,0\(sp\)
+[ 0-9a-f]+: 2043 c800 sdp v0,-2048\(v1\)
+[ 0-9a-f]+: 2043 c7ff sdp v0,2047\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ 0-9a-f]+: 2043 c000 sdp v0,0\(v1\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 2041 c678 sdp v0,1656\(at\)
+[ 0-9a-f]+: 6060 4000 ldl v1,0\(zero\)
+[ 0-9a-f]+: 6060 5007 ldr v1,7\(zero\)
+[ 0-9a-f]+: 6060 4000 ldl v1,0\(zero\)
+[ 0-9a-f]+: 6060 5007 ldr v1,7\(zero\)
+[ 0-9a-f]+: 6060 4004 ldl v1,4\(zero\)
+[ 0-9a-f]+: 6060 500b ldr v1,11\(zero\)
+[ 0-9a-f]+: 6060 4004 ldl v1,4\(zero\)
+[ 0-9a-f]+: 6060 500b ldr v1,11\(zero\)
+[ 0-9a-f]+: 3020 07ff li at,2047
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 6060 4800 ldl v1,-2048\(zero\)
+[ 0-9a-f]+: 6060 5807 ldr v1,-2041\(zero\)
+[ 0-9a-f]+: 3020 0800 li at,2048
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 f7ff li at,-2049
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 7ff1 li at,32753
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 6064 4000 ldl v1,0\(a0\)
+[ 0-9a-f]+: 6064 5007 ldr v1,7\(a0\)
+[ 0-9a-f]+: 6064 4004 ldl v1,4\(a0\)
+[ 0-9a-f]+: 6064 500b ldr v1,11\(a0\)
+[ 0-9a-f]+: 3024 07ff addiu at,a0,2047
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 6064 4800 ldl v1,-2048\(a0\)
+[ 0-9a-f]+: 6064 5807 ldr v1,-2041\(a0\)
+[ 0-9a-f]+: 3024 0800 addiu at,a0,2048
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3024 f7ff addiu at,a0,-2049
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3024 7ff1 addiu at,a0,32753
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 6060 c000 sdl v1,0\(zero\)
+[ 0-9a-f]+: 6060 d007 sdr v1,7\(zero\)
+[ 0-9a-f]+: 6060 c000 sdl v1,0\(zero\)
+[ 0-9a-f]+: 6060 d007 sdr v1,7\(zero\)
+[ 0-9a-f]+: 6060 c004 sdl v1,4\(zero\)
+[ 0-9a-f]+: 6060 d00b sdr v1,11\(zero\)
+[ 0-9a-f]+: 6060 c004 sdl v1,4\(zero\)
+[ 0-9a-f]+: 6060 d00b sdr v1,11\(zero\)
+[ 0-9a-f]+: 3020 07ff li at,2047
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 6060 c800 sdl v1,-2048\(zero\)
+[ 0-9a-f]+: 6060 d807 sdr v1,-2041\(zero\)
+[ 0-9a-f]+: 3020 0800 li at,2048
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 f7ff li at,-2049
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 7ff1 li at,32753
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 6064 c000 sdl v1,0\(a0\)
+[ 0-9a-f]+: 6064 d007 sdr v1,7\(a0\)
+[ 0-9a-f]+: 6064 c004 sdl v1,4\(a0\)
+[ 0-9a-f]+: 6064 d00b sdr v1,11\(a0\)
+[ 0-9a-f]+: 3024 07ff addiu at,a0,2047
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 6064 c800 sdl v1,-2048\(a0\)
+[ 0-9a-f]+: 6064 d807 sdr v1,-2041\(a0\)
+[ 0-9a-f]+: 3024 0800 addiu at,a0,2048
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3024 f7ff addiu at,a0,-2049
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3024 7ff1 addiu at,a0,32753
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 4000 ldl s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 5000 ldr s0,0\(at\)
+[ 0-9a-f]+: 3203 0000 addiu s0,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6210 7000 lld s0,0\(s0\)
+[ 0-9a-f]+: 3203 0000 addiu s0,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6210 e000 lwu s0,0\(s0\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 f000 scd s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 c000 sdl s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 d000 sdr s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 3223 0000 addiu s1,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2211 4000 ldp s0,0\(s1\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 c000 sdp s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 2000 ldc2 \$16,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 a000 sdc2 \$16,0\(at\)
+
+[0-9a-f]+ <test_delay_slot>:
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <test_delay_slot>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4063 fffe bgezal v1,[0-9a-f]+ <test_delay_slot\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4023 fffe bltzal v1,[0-9a-f]+ <test_delay_slot\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4263 fffe bgezals v1,[0-9a-f]+ <test_delay_slot\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4223 fffe bltzals v1,[0-9a-f]+ <test_delay_slot\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: f400 0000 jal [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test_delay_slot
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: f000 0000 jalx [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test_delay_slot
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c2 jalr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e2 0f3c jalr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4582 jr v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0002 0f3c jr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e2 1f3c jalr\.hb v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0002 1f3c jr\.hb v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 7400 0000 jals [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test_delay_slot
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 45e2 jalrs v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 03e2 4f3c jalrs v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0002 4f3c jrs v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 03e2 5f3c jalrs\.hb v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0002 5f3c jrs\.hb v0
+[ 0-9a-f]+: 0c00 nop
+
+[0-9a-f]+ <test_spec102>:
+[ 0-9a-f]+: 6540 lw v0,-256\(gp\)
+[ 0-9a-f]+: 65c0 lw v1,-256\(gp\)
+[ 0-9a-f]+: 6640 lw a0,-256\(gp\)
+[ 0-9a-f]+: 66c0 lw a1,-256\(gp\)
+[ 0-9a-f]+: 6740 lw a2,-256\(gp\)
+[ 0-9a-f]+: 67c0 lw a3,-256\(gp\)
+[ 0-9a-f]+: 6440 lw s0,-256\(gp\)
+[ 0-9a-f]+: 64c0 lw s1,-256\(gp\)
+[ 0-9a-f]+: 64c1 lw s1,-252\(gp\)
+[ 0-9a-f]+: 64ff lw s1,-4\(gp\)
+[ 0-9a-f]+: 6480 lw s1,0\(gp\)
+[ 0-9a-f]+: 6481 lw s1,4\(gp\)
+[ 0-9a-f]+: 64be lw s1,248\(gp\)
+[ 0-9a-f]+: 64bf lw s1,252\(gp\)
+[ 0-9a-f]+: fe3c 0100 lw s1,256\(gp\)
+[ 0-9a-f]+: fe3c fefc lw s1,-260\(gp\)
+[ 0-9a-f]+: fe3c 0001 lw s1,1\(gp\)
+[ 0-9a-f]+: fe3c 0002 lw s1,2\(gp\)
+[ 0-9a-f]+: fe3c 0003 lw s1,3\(gp\)
+[ 0-9a-f]+: fe3c ffff lw s1,-1\(gp\)
+[ 0-9a-f]+: fe3c fffe lw s1,-2\(gp\)
+[ 0-9a-f]+: fe3c fffd lw s1,-3\(gp\)
+[ 0-9a-f]+: fe3b 0000 lw s1,0\(k1\)
+[ 0-9a-f]+: 7900 0000 addiu v0,\$pc,0
+[ 0-9a-f]+: 7980 0000 addiu v1,\$pc,0
+[ 0-9a-f]+: 7a00 0000 addiu a0,\$pc,0
+[ 0-9a-f]+: 7a80 0000 addiu a1,\$pc,0
+[ 0-9a-f]+: 7b00 0000 addiu a2,\$pc,0
+[ 0-9a-f]+: 7b80 0000 addiu a3,\$pc,0
+[ 0-9a-f]+: 7800 0000 addiu s0,\$pc,0
+[ 0-9a-f]+: 7880 0000 addiu s1,\$pc,0
+[ 0-9a-f]+: 78bf ffff addiu s1,\$pc,16777212
+[ 0-9a-f]+: 78c0 0000 addiu s1,\$pc,-16777216
+[ 0-9a-f]+: 7900 0000 addiu v0,\$pc,0
+[ 0-9a-f]+: 7980 0000 addiu v1,\$pc,0
+[ 0-9a-f]+: 7a00 0000 addiu a0,\$pc,0
+[ 0-9a-f]+: 7a80 0000 addiu a1,\$pc,0
+[ 0-9a-f]+: 7b00 0000 addiu a2,\$pc,0
+[ 0-9a-f]+: 7b80 0000 addiu a3,\$pc,0
+[ 0-9a-f]+: 7800 0000 addiu s0,\$pc,0
+[ 0-9a-f]+: 7880 0000 addiu s1,\$pc,0
+[ 0-9a-f]+: 78bf ffff addiu s1,\$pc,16777212
+[ 0-9a-f]+: 78c0 0000 addiu s1,\$pc,-16777216
+
+[0-9a-f]+ <test_spec107>:
+[ 0-9a-f]+: 8400 movep a1,a2,zero,zero
+[ 0-9a-f]+: 8480 movep a1,a3,zero,zero
+[ 0-9a-f]+: 8500 movep a2,a3,zero,zero
+[ 0-9a-f]+: 8580 movep a0,s5,zero,zero
+[ 0-9a-f]+: 8600 movep a0,s6,zero,zero
+[ 0-9a-f]+: 8680 movep a0,a1,zero,zero
+[ 0-9a-f]+: 8700 movep a0,a2,zero,zero
+[ 0-9a-f]+: 8780 movep a0,a3,zero,zero
+[ 0-9a-f]+: 8782 movep a0,a3,s1,zero
+[ 0-9a-f]+: 8784 movep a0,a3,v0,zero
+[ 0-9a-f]+: 8786 movep a0,a3,v1,zero
+[ 0-9a-f]+: 8788 movep a0,a3,s0,zero
+[ 0-9a-f]+: 878a movep a0,a3,s2,zero
+[ 0-9a-f]+: 878c movep a0,a3,s3,zero
+[ 0-9a-f]+: 878e movep a0,a3,s4,zero
+[ 0-9a-f]+: 879e movep a0,a3,s4,s1
+[ 0-9a-f]+: 87ae movep a0,a3,s4,v0
+[ 0-9a-f]+: 87be movep a0,a3,s4,v1
+[ 0-9a-f]+: 87ce movep a0,a3,s4,s0
+[ 0-9a-f]+: 87de movep a0,a3,s4,s2
+[ 0-9a-f]+: 87ee movep a0,a3,s4,s3
+[ 0-9a-f]+: 87fe movep a0,a3,s4,s4
+[ 0-9a-f]+: 4260 fffe bals [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4262 fffe bgezals v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4222 fffe bltzals v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4062 fffe bgezal v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4022 fffe bltzal v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0000 0000 nop
+#pass
--- /dev/null
+#objdump: -dr --show-raw-insn
+#name: microMIPS for MIPS32r2
+#as: -mips32r2 -32 -mfp64 -EB
+#stderr: micromips.l
+#source: micromips.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <test>:
+[ 0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+[ 0-9a-f]+: 6000 27ff pref 0x0,2047\(zero\)
+[ 0-9a-f]+: 6000 2800 pref 0x0,-2048\(zero\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 6001 2800 pref 0x0,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 6001 27ff pref 0x0,2047\(at\)
+[ 0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+[ 0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+[ 0-9a-f]+: 6020 2000 pref 0x1,0\(zero\)
+[ 0-9a-f]+: 6040 2000 pref 0x2,0\(zero\)
+[ 0-9a-f]+: 6060 2000 pref 0x3,0\(zero\)
+[ 0-9a-f]+: 6080 2000 pref 0x4,0\(zero\)
+[ 0-9a-f]+: 60a0 2000 pref 0x5,0\(zero\)
+[ 0-9a-f]+: 60c0 2000 pref 0x6,0\(zero\)
+[ 0-9a-f]+: 60e0 2000 pref 0x7,0\(zero\)
+[ 0-9a-f]+: 60e0 21ff pref 0x7,511\(zero\)
+[ 0-9a-f]+: 60e0 2e00 pref 0x7,-512\(zero\)
+[ 0-9a-f]+: 63e0 27ff pref 0x1f,2047\(zero\)
+[ 0-9a-f]+: 63e0 2800 pref 0x1f,-2048\(zero\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 63e1 2800 pref 0x1f,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 63e1 27ff pref 0x1f,2047\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 2fff pref 0x3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+[ 0-9a-f]+: 63e2 27ff pref 0x1f,2047\(v0\)
+[ 0-9a-f]+: 63e2 2800 pref 0x1f,-2048\(v0\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 63e1 2800 pref 0x1f,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 63e1 27ff pref 0x1f,2047\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 6061 2fff pref 0x3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0000 0800 ssnop
+[ 0-9a-f]+: 0000 1800 ehb
+[ 0-9a-f]+: 0000 2800 pause
+[ 0-9a-f]+: ed7f li v0,-1
+[ 0-9a-f]+: edff li v1,-1
+[ 0-9a-f]+: ee7f li a0,-1
+[ 0-9a-f]+: eeff li a1,-1
+[ 0-9a-f]+: ef7f li a2,-1
+[ 0-9a-f]+: efff li a3,-1
+[ 0-9a-f]+: ec7f li s0,-1
+[ 0-9a-f]+: ecff li s1,-1
+[ 0-9a-f]+: ec80 li s1,0
+[ 0-9a-f]+: ecfd li s1,125
+[ 0-9a-f]+: ecfe li s1,126
+[ 0-9a-f]+: 3220 007f li s1,127
+[ 0-9a-f]+: 3040 0000 li v0,0
+[ 0-9a-f]+: 3040 0001 li v0,1
+[ 0-9a-f]+: 3040 7fff li v0,32767
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 5040 ffff li v0,0xffff
+[ 0-9a-f]+: 41a2 0001 lui v0,0x1
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 3040 8001 li v0,-32767
+[ 0-9a-f]+: 3040 ffff li v0,-1
+[ 0-9a-f]+: 41a2 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5678 ori v0,v0,0x5678
+[ 0-9a-f]+: 0c16 move zero,s6
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0c76 move v1,s6
+[ 0-9a-f]+: 0c96 move a0,s6
+[ 0-9a-f]+: 0cb6 move a1,s6
+[ 0-9a-f]+: 0cd6 move a2,s6
+[ 0-9a-f]+: 0cf6 move a3,s6
+[ 0-9a-f]+: 0d16 move t0,s6
+[ 0-9a-f]+: 0d36 move t1,s6
+[ 0-9a-f]+: 0d56 move t2,s6
+[ 0-9a-f]+: 0fd6 move s8,s6
+[ 0-9a-f]+: 0ff6 move ra,s6
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0c02 move zero,v0
+[ 0-9a-f]+: 0c03 move zero,v1
+[ 0-9a-f]+: 0c04 move zero,a0
+[ 0-9a-f]+: 0c05 move zero,a1
+[ 0-9a-f]+: 0c06 move zero,a2
+[ 0-9a-f]+: 0c07 move zero,a3
+[ 0-9a-f]+: 0c08 move zero,t0
+[ 0-9a-f]+: 0c09 move zero,t1
+[ 0-9a-f]+: 0c0a move zero,t2
+[ 0-9a-f]+: 0c1e move zero,s8
+[ 0-9a-f]+: 0c1f move zero,ra
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 0016 1150 move v0,s6
+[ 0-9a-f]+: 0002 b150 move s6,v0
+[ 0-9a-f]+: cfff b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: cfff b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: cfff b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: cfff b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: cfff b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: cfff b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c43 move v0,v1
+[ 0-9a-f]+: 0060 1190 neg v0,v1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4044 fffe bgez a0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c44 move v0,a0
+[ 0-9a-f]+: 0080 1190 neg v0,a0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0083 1110 add v0,v1,a0
+[ 0-9a-f]+: 03fe e910 add sp,s8,ra
+[ 0-9a-f]+: 0082 1110 add v0,v0,a0
+[ 0-9a-f]+: 0082 1110 add v0,v0,a0
+[ 0-9a-f]+: 1042 0000 addi v0,v0,0
+[ 0-9a-f]+: 1042 0001 addi v0,v0,1
+[ 0-9a-f]+: 1042 7fff addi v0,v0,32767
+[ 0-9a-f]+: 1042 8000 addi v0,v0,-32768
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 1110 add v0,v0,at
+[ 0-9a-f]+: 1064 8000 addi v1,a0,-32768
+[ 0-9a-f]+: 1064 0000 addi v1,a0,0
+[ 0-9a-f]+: 1064 7fff addi v1,a0,32767
+[ 0-9a-f]+: 1064 ffff addi v1,a0,-1
+[ 0-9a-f]+: 1063 ffff addi v1,v1,-1
+[ 0-9a-f]+: 1063 ffff addi v1,v1,-1
+[ 0-9a-f]+: 4c10 addiu zero,zero,-8
+[ 0-9a-f]+: 4c50 addiu v0,v0,-8
+[ 0-9a-f]+: 4c70 addiu v1,v1,-8
+[ 0-9a-f]+: 4c90 addiu a0,a0,-8
+[ 0-9a-f]+: 4cb0 addiu a1,a1,-8
+[ 0-9a-f]+: 4cd0 addiu a2,a2,-8
+[ 0-9a-f]+: 4cf0 addiu a3,a3,-8
+[ 0-9a-f]+: 4d10 addiu t0,t0,-8
+[ 0-9a-f]+: 4d30 addiu t1,t1,-8
+[ 0-9a-f]+: 4d50 addiu t2,t2,-8
+[ 0-9a-f]+: 4fd0 addiu s8,s8,-8
+[ 0-9a-f]+: 4ff0 addiu ra,ra,-8
+[ 0-9a-f]+: 4ff2 addiu ra,ra,-7
+[ 0-9a-f]+: 4fe0 addiu ra,ra,0
+[ 0-9a-f]+: 4fe2 addiu ra,ra,1
+[ 0-9a-f]+: 4fec addiu ra,ra,6
+[ 0-9a-f]+: 4fee addiu ra,ra,7
+[ 0-9a-f]+: 33ff 0008 addiu ra,ra,8
+[ 0-9a-f]+: 4ffd addiu sp,sp,-1032
+[ 0-9a-f]+: 4fff addiu sp,sp,-1028
+[ 0-9a-f]+: 4e01 addiu sp,sp,-1024
+[ 0-9a-f]+: 4dff addiu sp,sp,1020
+[ 0-9a-f]+: 4c01 addiu sp,sp,1024
+[ 0-9a-f]+: 4c03 addiu sp,sp,1028
+[ 0-9a-f]+: 4c03 addiu sp,sp,1028
+[ 0-9a-f]+: 33bd 0408 addiu sp,sp,1032
+[ 0-9a-f]+: 6d2e addiu v0,v0,-1
+[ 0-9a-f]+: 6d3e addiu v0,v1,-1
+[ 0-9a-f]+: 6d4e addiu v0,a0,-1
+[ 0-9a-f]+: 6d5e addiu v0,a1,-1
+[ 0-9a-f]+: 6d6e addiu v0,a2,-1
+[ 0-9a-f]+: 6d7e addiu v0,a3,-1
+[ 0-9a-f]+: 6d0e addiu v0,s0,-1
+[ 0-9a-f]+: 6d1e addiu v0,s1,-1
+[ 0-9a-f]+: 6d10 addiu v0,s1,1
+[ 0-9a-f]+: 6d12 addiu v0,s1,4
+[ 0-9a-f]+: 6d14 addiu v0,s1,8
+[ 0-9a-f]+: 6d16 addiu v0,s1,12
+[ 0-9a-f]+: 6d18 addiu v0,s1,16
+[ 0-9a-f]+: 6d1a addiu v0,s1,20
+[ 0-9a-f]+: 6d1c addiu v0,s1,24
+[ 0-9a-f]+: 6d9c addiu v1,s1,24
+[ 0-9a-f]+: 6e1c addiu a0,s1,24
+[ 0-9a-f]+: 6e9c addiu a1,s1,24
+[ 0-9a-f]+: 6f1c addiu a2,s1,24
+[ 0-9a-f]+: 6f9c addiu a3,s1,24
+[ 0-9a-f]+: 6c1c addiu s0,s1,24
+[ 0-9a-f]+: 6c9c addiu s1,s1,24
+[ 0-9a-f]+: 0c5d move v0,sp
+[ 0-9a-f]+: 6d03 addiu v0,sp,4
+[ 0-9a-f]+: 6d7d addiu v0,sp,248
+[ 0-9a-f]+: 6d7f addiu v0,sp,252
+[ 0-9a-f]+: 305d 0100 addiu v0,sp,256
+[ 0-9a-f]+: 6d7f addiu v0,sp,252
+[ 0-9a-f]+: 6dff addiu v1,sp,252
+[ 0-9a-f]+: 6e7f addiu a0,sp,252
+[ 0-9a-f]+: 6eff addiu a1,sp,252
+[ 0-9a-f]+: 6f7f addiu a2,sp,252
+[ 0-9a-f]+: 6fff addiu a3,sp,252
+[ 0-9a-f]+: 6c7f addiu s0,sp,252
+[ 0-9a-f]+: 6cff addiu s1,sp,252
+[ 0-9a-f]+: 3064 8000 addiu v1,a0,-32768
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 3064 7fff addiu v1,a0,32767
+[ 0-9a-f]+: 3064 ffff addiu v1,a0,-1
+[ 0-9a-f]+: 3063 ffff addiu v1,v1,-1
+[ 0-9a-f]+: 3063 ffff addiu v1,v1,-1
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 0526 addu v0,v1,v0
+[ 0-9a-f]+: 0536 addu v0,v1,v1
+[ 0-9a-f]+: 0546 addu v0,v1,a0
+[ 0-9a-f]+: 0556 addu v0,v1,a1
+[ 0-9a-f]+: 0566 addu v0,v1,a2
+[ 0-9a-f]+: 0576 addu v0,v1,a3
+[ 0-9a-f]+: 0506 addu v0,v1,s0
+[ 0-9a-f]+: 0516 addu v0,v1,s1
+[ 0-9a-f]+: 0514 addu v0,v0,s1
+[ 0-9a-f]+: 0516 addu v0,v1,s1
+[ 0-9a-f]+: 0518 addu v0,a0,s1
+[ 0-9a-f]+: 051a addu v0,a1,s1
+[ 0-9a-f]+: 051c addu v0,a2,s1
+[ 0-9a-f]+: 051e addu v0,a3,s1
+[ 0-9a-f]+: 0510 addu v0,s0,s1
+[ 0-9a-f]+: 0512 addu v0,s1,s1
+[ 0-9a-f]+: 0514 addu v0,v0,s1
+[ 0-9a-f]+: 0594 addu v1,v0,s1
+[ 0-9a-f]+: 0614 addu a0,v0,s1
+[ 0-9a-f]+: 0694 addu a1,v0,s1
+[ 0-9a-f]+: 0714 addu a2,v0,s1
+[ 0-9a-f]+: 0794 addu a3,v0,s1
+[ 0-9a-f]+: 0414 addu s0,v0,s1
+[ 0-9a-f]+: 0494 addu s1,v0,s1
+[ 0-9a-f]+: 07ae addu a3,a3,v0
+[ 0-9a-f]+: 07ae addu a3,a3,v0
+[ 0-9a-f]+: 07f4 addu a3,v0,a3
+[ 0-9a-f]+: 03fe e950 addu sp,s8,ra
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ 0-9a-f]+: 3042 0001 addiu v0,v0,1
+[ 0-9a-f]+: 3042 7fff addiu v0,v0,32767
+[ 0-9a-f]+: 3042 8000 addiu v0,v0,-32768
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 1150 addu v0,v0,at
+[ 0-9a-f]+: 4492 and v0,v0,v0
+[ 0-9a-f]+: 4493 and v0,v0,v1
+[ 0-9a-f]+: 4494 and v0,v0,a0
+[ 0-9a-f]+: 4495 and v0,v0,a1
+[ 0-9a-f]+: 4496 and v0,v0,a2
+[ 0-9a-f]+: 4497 and v0,v0,a3
+[ 0-9a-f]+: 4490 and v0,v0,s0
+[ 0-9a-f]+: 4491 and v0,v0,s1
+[ 0-9a-f]+: 449a and v1,v1,v0
+[ 0-9a-f]+: 44a2 and a0,a0,v0
+[ 0-9a-f]+: 44aa and a1,a1,v0
+[ 0-9a-f]+: 44b2 and a2,a2,v0
+[ 0-9a-f]+: 44ba and a3,a3,v0
+[ 0-9a-f]+: 4482 and s0,s0,v0
+[ 0-9a-f]+: 448a and s1,s1,v0
+[ 0-9a-f]+: 4493 and v0,v0,v1
+[ 0-9a-f]+: 4493 and v0,v0,v1
+[ 0-9a-f]+: 4493 and v0,v0,v1
+[ 0-9a-f]+: 4493 and v0,v0,v1
+[ 0-9a-f]+: 0062 1250 and v0,v0,v1
+[ 0-9a-f]+: 2d21 andi v0,v0,0x1
+[ 0-9a-f]+: 2d22 andi v0,v0,0x2
+[ 0-9a-f]+: 2d23 andi v0,v0,0x3
+[ 0-9a-f]+: 2d24 andi v0,v0,0x4
+[ 0-9a-f]+: 2d25 andi v0,v0,0x7
+[ 0-9a-f]+: 2d26 andi v0,v0,0x8
+[ 0-9a-f]+: 2d27 andi v0,v0,0xf
+[ 0-9a-f]+: 2d28 andi v0,v0,0x10
+[ 0-9a-f]+: 2d29 andi v0,v0,0x1f
+[ 0-9a-f]+: 2d2a andi v0,v0,0x20
+[ 0-9a-f]+: 2d2b andi v0,v0,0x3f
+[ 0-9a-f]+: 2d2c andi v0,v0,0x40
+[ 0-9a-f]+: 2d20 andi v0,v0,0x80
+[ 0-9a-f]+: 2d2d andi v0,v0,0xff
+[ 0-9a-f]+: 2d2e andi v0,v0,0x8000
+[ 0-9a-f]+: 2d2f andi v0,v0,0xffff
+[ 0-9a-f]+: 2d3f andi v0,v1,0xffff
+[ 0-9a-f]+: 2d4f andi v0,a0,0xffff
+[ 0-9a-f]+: 2d5f andi v0,a1,0xffff
+[ 0-9a-f]+: 2d6f andi v0,a2,0xffff
+[ 0-9a-f]+: 2d7f andi v0,a3,0xffff
+[ 0-9a-f]+: 2d0f andi v0,s0,0xffff
+[ 0-9a-f]+: 2d1f andi v0,s1,0xffff
+[ 0-9a-f]+: 2d9f andi v1,s1,0xffff
+[ 0-9a-f]+: 2e1f andi a0,s1,0xffff
+[ 0-9a-f]+: 2e9f andi a1,s1,0xffff
+[ 0-9a-f]+: 2f1f andi a2,s1,0xffff
+[ 0-9a-f]+: 2f9f andi a3,s1,0xffff
+[ 0-9a-f]+: 2c1f andi s0,s1,0xffff
+[ 0-9a-f]+: 2c9f andi s1,s1,0xffff
+[ 0-9a-f]+: 2fff andi a3,a3,0xffff
+[ 0-9a-f]+: 2fff andi a3,a3,0xffff
+[ 0-9a-f]+: 2fff andi a3,a3,0xffff
+[ 0-9a-f]+: d0e7 ffff andi a3,a3,0xffff
+[ 0-9a-f]+: 0083 1250 and v0,v1,a0
+[ 0-9a-f]+: 0082 1250 and v0,v0,a0
+[ 0-9a-f]+: 0082 1250 and v0,v0,a0
+[ 0-9a-f]+: d043 0000 andi v0,v1,0x0
+[ 0-9a-f]+: d043 ffff andi v0,v1,0xffff
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1250 and v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0023 1250 and v0,v1,at
+[ 0-9a-f]+: 4280 fffe bc2f [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4280 fffe bc2f [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4284 fffe bc2f \$cc1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4288 fffe bc2f \$cc2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 428c fffe bc2f \$cc3,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4290 fffe bc2f \$cc4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4294 fffe bc2f \$cc5,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4298 fffe bc2f \$cc6,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 429c fffe bc2f \$cc7,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42a0 fffe bc2t [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42a0 fffe bc2t [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42a4 fffe bc2t \$cc1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42a8 fffe bc2t \$cc2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42ac fffe bc2t \$cc3,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42b0 fffe bc2t \$cc4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42b4 fffe bc2t \$cc5,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42b8 fffe bc2t \$cc6,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42bc fffe bc2t \$cc7,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 42a4 fffe bc2t \$cc1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4288 fffe bc2f \$cc2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0107 3150 addu a2,a3,t0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 428c fffe bc2f \$cc3,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 42b0 fffe bc2t \$cc4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0107 3150 addu a2,a3,t0
+
+[0-9a-f]+ <test2>:
+[ 0-9a-f]+: 8d7f beqz v0,[0-9a-f]+ <test2>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8e7f beqz a0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8eff beqz a1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8f7f beqz a2,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8fff beqz a3,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8c7f beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8cff beqz s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8d7f beqz v0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8e7f beqz a0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8eff beqz a1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8f7f beqz a2,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8fff beqz a3,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8c7f beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8cff beqz s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8d7f beqz v0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8e7f beqz a0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8eff beqz a1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8f7f beqz a2,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8fff beqz a3,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8c7f beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8cff beqz s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8c7f beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9410 fffe beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 8cff beqz s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9411 fffe beqz s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 40f1 fffe beqzc s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 9410 fffe beqz s0,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: 9430 fffe beq s0,at,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 9430 fffe beq s0,at,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 9430 fffe beq s0,at,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: b630 fffe bne s0,s1,[0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <test2\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b630 fffe bne s0,s1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b410 fffe bnez s0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b410 fffe bnez s0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b630 fffe bne s0,s1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b630 fffe bne s0,s1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b410 fffe bnez s0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b410 fffe bnez s0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: b430 fffe bne s0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03a4 1950 addu v1,a0,sp
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9630 fffe beq s0,s1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9411 fffe beqz s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ad7f bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ae7f bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: aeff bnez a1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: af7f bnez a2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: afff bnez a3,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ac7f bnez s0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: acff bnez s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ad7f bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ae7f bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: aeff bnez a1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: af7f bnez a2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: afff bnez a3,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ac7f bnez s0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: acff bnez s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ad7f bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: adff bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ae7f bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: aeff bnez a1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: af7f bnez a2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: afff bnez a3,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ac7f bnez s0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: acff bnez s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: ac7f bnez s0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: b410 fffe bnez s0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: b411 fffe bnez s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: b411 fffe bnez s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0c00 nop
+
+[0-9a-f]+ <test3>:
+[ 0-9a-f]+: 40b1 fffe bnezc s1,[0-9a-f]+ <test3>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 4680 break
+[ 0-9a-f]+: 4680 break
+[ 0-9a-f]+: 4681 break 0x1
+[ 0-9a-f]+: 4682 break 0x2
+[ 0-9a-f]+: 4683 break 0x3
+[ 0-9a-f]+: 4684 break 0x4
+[ 0-9a-f]+: 4685 break 0x5
+[ 0-9a-f]+: 4686 break 0x6
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 4688 break 0x8
+[ 0-9a-f]+: 4689 break 0x9
+[ 0-9a-f]+: 468a break 0xa
+[ 0-9a-f]+: 468b break 0xb
+[ 0-9a-f]+: 468c break 0xc
+[ 0-9a-f]+: 468d break 0xd
+[ 0-9a-f]+: 468e break 0xe
+[ 0-9a-f]+: 468f break 0xf
+[ 0-9a-f]+: 003f 0007 break 0x3f
+[ 0-9a-f]+: 0040 0007 break 0x40
+[ 0-9a-f]+: 03ff 0007 break 0x3ff
+[ 0-9a-f]+: 03ff ffc7 break 0x3ff,0x3ff
+[ 0-9a-f]+: 0000 0007 break
+[ 0-9a-f]+: 0000 0007 break
+[ 0-9a-f]+: 0001 0007 break 0x1
+[ 0-9a-f]+: 0002 0007 break 0x2
+[ 0-9a-f]+: 000f 0007 break 0xf
+[ 0-9a-f]+: 003f 0007 break 0x3f
+[ 0-9a-f]+: 0040 0007 break 0x40
+[ 0-9a-f]+: 03ff 0007 break 0x3ff
+[ 0-9a-f]+: 03ff ffc7 break 0x3ff,0x3ff
+[ 0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+[ 0-9a-f]+: 2000 6800 cache 0x0,-2048\(zero\)
+[ 0-9a-f]+: 2000 67ff cache 0x0,2047\(zero\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 2001 67ff cache 0x0,2047\(at\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 2001 6800 cache 0x0,-2048\(at\)
+[ 0-9a-f]+: 2002 6000 cache 0x0,0\(v0\)
+[ 0-9a-f]+: 2002 6800 cache 0x0,-2048\(v0\)
+[ 0-9a-f]+: 2002 67ff cache 0x0,2047\(v0\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 2001 67ff cache 0x0,2047\(at\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 0041 0950 addu at,at,v0
+[ 0-9a-f]+: 2001 6800 cache 0x0,-2048\(at\)
+[ 0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+[ 0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+[ 0-9a-f]+: 2020 6000 cache 0x1,0\(zero\)
+[ 0-9a-f]+: 2040 6000 cache 0x2,0\(zero\)
+[ 0-9a-f]+: 2060 6000 cache 0x3,0\(zero\)
+[ 0-9a-f]+: 2080 6000 cache 0x4,0\(zero\)
+[ 0-9a-f]+: 20a0 6000 cache 0x5,0\(zero\)
+[ 0-9a-f]+: 20c0 6000 cache 0x6,0\(zero\)
+[ 0-9a-f]+: 23e0 6000 cache 0x1f,0\(zero\)
+[ 0-9a-f]+: 23e0 67ff cache 0x1f,2047\(zero\)
+[ 0-9a-f]+: 23e0 6800 cache 0x1f,-2048\(zero\)
+[ 0-9a-f]+: 2000 67ff cache 0x0,2047\(zero\)
+[ 0-9a-f]+: 2000 6800 cache 0x0,-2048\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6800 cache 0x1f,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 67ff cache 0x1f,2047\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 23e3 6fff cache 0x1f,-1\(v1\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6fff cache 0x1f,-1\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 23e1 6800 cache 0x1f,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 23e1 67ff cache 0x1f,2047\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 23e0 6fff cache 0x1f,-1\(zero\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 23e1 6fff cache 0x1f,-1\(at\)
+[ 0-9a-f]+: 0043 4b3c clo v0,v1
+[ 0-9a-f]+: 0062 4b3c clo v1,v0
+[ 0-9a-f]+: 0043 5b3c clz v0,v1
+[ 0-9a-f]+: 0062 5b3c clz v1,v0
+[ 0-9a-f]+: 0000 e37c deret
+[ 0-9a-f]+: 0000 477c di
+[ 0-9a-f]+: 0000 477c di
+[ 0-9a-f]+: 0002 477c di v0
+[ 0-9a-f]+: 0003 477c di v1
+[ 0-9a-f]+: 001e 477c di s8
+[ 0-9a-f]+: 001f 477c di ra
+[ 0-9a-f]+: 0062 ab3c div zero,v0,v1
+[ 0-9a-f]+: 03fe ab3c div zero,s8,ra
+[ 0-9a-f]+: 0060 ab3c div zero,zero,v1
+[ 0-9a-f]+: 03e0 ab3c div zero,zero,ra
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: b404 fffe bnez a0,[0-9a-f]+ <test3\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0083 ab3c div zero,v1,a0
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b424 fffe bne a0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: b423 fffe bne v1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 0080 1990 neg v1,a0
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 0024 ab3c div zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 0062 bb3c divu zero,v0,v1
+[ 0-9a-f]+: 03fe bb3c divu zero,s8,ra
+[ 0-9a-f]+: 0060 bb3c divu zero,zero,v1
+[ 0-9a-f]+: 03e0 bb3c divu zero,zero,ra
+[ 0-9a-f]+: b400 fffe bnez zero,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0003 bb3c divu zero,v1,zero
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: b404 fffe bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0083 bb3c divu zero,v1,a0
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0024 bb3c divu zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 0024 bb3c divu zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 0000 577c ei
+[ 0-9a-f]+: 0000 577c ei
+[ 0-9a-f]+: 0002 577c ei v0
+[ 0-9a-f]+: 0003 577c ei v1
+[ 0-9a-f]+: 001e 577c ei s8
+[ 0-9a-f]+: 001f 577c ei ra
+[ 0-9a-f]+: 0000 f37c eret
+[ 0-9a-f]+: 0043 716c ext v0,v1,0x5,0xf
+[ 0-9a-f]+: 0043 f82c ext v0,v1,0x0,0x20
+[ 0-9a-f]+: 0043 07ec ext v0,v1,0x1f,0x1
+[ 0-9a-f]+: 03fe 07ec ext ra,s8,0x1f,0x1
+[ 0-9a-f]+: 0043 994c ins v0,v1,0x5,0xf
+[ 0-9a-f]+: 0043 f80c ins v0,v1,0x0,0x20
+[ 0-9a-f]+: 0043 ffcc ins v0,v1,0x1f,0x1
+[ 0-9a-f]+: 03fe ffcc ins ra,s8,0x1f,0x1
+[ 0-9a-f]+: 4580 jr zero
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4582 jr v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4583 jr v1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4584 jr a0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4585 jr a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4586 jr a2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4587 jr a3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4588 jr t0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 459e jr s8
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 459f jr ra
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0000 0f3c jr zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0002 0f3c jr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0003 0f3c jr v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0004 0f3c jr a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0005 0f3c jr a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0006 0f3c jr a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0007 0f3c jr a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0008 0f3c jr t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 001e 0f3c jr s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 001f 0f3c jr ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45a0 jrc zero
+[ 0-9a-f]+: 45a2 jrc v0
+[ 0-9a-f]+: 45a3 jrc v1
+[ 0-9a-f]+: 45a4 jrc a0
+[ 0-9a-f]+: 45a5 jrc a1
+[ 0-9a-f]+: 45a6 jrc a2
+[ 0-9a-f]+: 45a7 jrc a3
+[ 0-9a-f]+: 45a8 jrc t0
+[ 0-9a-f]+: 45be jrc s8
+[ 0-9a-f]+: 45bf jrc ra
+[ 0-9a-f]+: 0000 1f3c jr\.hb zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0002 1f3c jr\.hb v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0003 1f3c jr\.hb v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0004 1f3c jr\.hb a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0005 1f3c jr\.hb a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0006 1f3c jr\.hb a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0007 1f3c jr\.hb a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0008 1f3c jr\.hb t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 001e 1f3c jr\.hb s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 001f 1f3c jr\.hb ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4580 jr zero
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4582 jr v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4583 jr v1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4584 jr a0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4585 jr a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4586 jr a2
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4587 jr a3
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4588 jr t0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 459e jr s8
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 459f jr ra
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 45c0 jalr zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c2 jalr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c3 jalr v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c4 jalr a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c5 jalr a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c6 jalr a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c7 jalr a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c8 jalr t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45de jalr s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e0 0f3c jalr zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e2 0f3c jalr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e3 0f3c jalr v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e4 0f3c jalr a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e5 0f3c jalr a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e6 0f3c jalr a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e7 0f3c jalr a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e8 0f3c jalr t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03fe 0f3c jalr s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c0 jalr zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c2 jalr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c3 jalr v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c4 jalr a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c5 jalr a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c6 jalr a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c7 jalr a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c8 jalr t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45de jalr s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03df 0f3c jalr s8,ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0040 0f3c jalr v0,zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0062 0f3c jalr v1,v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0043 0f3c jalr v0,v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0044 0f3c jalr v0,a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0045 0f3c jalr v0,a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0046 0f3c jalr v0,a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0047 0f3c jalr v0,a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0048 0f3c jalr v0,t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 005e 0f3c jalr v0,s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 005f 0f3c jalr v0,ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e0 1f3c jalr\.hb zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e2 1f3c jalr\.hb v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e3 1f3c jalr\.hb v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e4 1f3c jalr\.hb a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e5 1f3c jalr\.hb a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e6 1f3c jalr\.hb a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e7 1f3c jalr\.hb a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e8 1f3c jalr\.hb t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03fe 1f3c jalr\.hb s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e0 1f3c jalr\.hb zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e2 1f3c jalr\.hb v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e3 1f3c jalr\.hb v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e4 1f3c jalr\.hb a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e5 1f3c jalr\.hb a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e6 1f3c jalr\.hb a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e7 1f3c jalr\.hb a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e8 1f3c jalr\.hb t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03fe 1f3c jalr\.hb s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03df 1f3c jalr\.hb s8,ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0040 1f3c jalr\.hb v0,zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0062 1f3c jalr\.hb v1,v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0043 1f3c jalr\.hb v0,v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0044 1f3c jalr\.hb v0,a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0045 1f3c jalr\.hb v0,a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0046 1f3c jalr\.hb v0,a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0047 1f3c jalr\.hb v0,a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0048 1f3c jalr\.hb v0,t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 005e 1f3c jalr\.hb v0,s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 005f 1f3c jalr\.hb v0,ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0043 0f3c jalr v0,v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03df 0f3c jalr s8,ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c3 jalr v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45df jalr ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: f400 0000 jal [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: f400 0000 jal [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: f000 0000 jalx [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: f000 0000 jalx [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 41a2 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 41a2 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 1c60 0000 lb v1,0\(zero\)
+[ 0-9a-f]+: 1c60 0004 lb v1,4\(zero\)
+[ 0-9a-f]+: 1c60 0000 lb v1,0\(zero\)
+[ 0-9a-f]+: 1c60 0004 lb v1,4\(zero\)
+[ 0-9a-f]+: 1c60 7fff lb v1,32767\(zero\)
+[ 0-9a-f]+: 1c60 8000 lb v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 1c63 ffff lb v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c60 8000 lb v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 1c63 0001 lb v1,1\(v1\)
+[ 0-9a-f]+: 1c60 8001 lb v1,-32767\(zero\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c60 ffff lb v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 1c63 5678 lb v1,22136\(v1\)
+[ 0-9a-f]+: 1c64 0000 lb v1,0\(a0\)
+[ 0-9a-f]+: 1c64 0000 lb v1,0\(a0\)
+[ 0-9a-f]+: 1c64 0004 lb v1,4\(a0\)
+[ 0-9a-f]+: 1c64 7fff lb v1,32767\(a0\)
+[ 0-9a-f]+: 1c64 8000 lb v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 ffff lb v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c64 8000 lb v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 0001 lb v1,1\(v1\)
+[ 0-9a-f]+: 1c64 8001 lb v1,-32767\(a0\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c64 ffff lb v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 5678 lb v1,22136\(v1\)
+[ 0-9a-f]+: 093f lbu v0,-1\(v1\)
+[ 0-9a-f]+: 0930 lbu v0,0\(v1\)
+[ 0-9a-f]+: 0930 lbu v0,0\(v1\)
+[ 0-9a-f]+: 0931 lbu v0,1\(v1\)
+[ 0-9a-f]+: 0932 lbu v0,2\(v1\)
+[ 0-9a-f]+: 0933 lbu v0,3\(v1\)
+[ 0-9a-f]+: 0934 lbu v0,4\(v1\)
+[ 0-9a-f]+: 0935 lbu v0,5\(v1\)
+[ 0-9a-f]+: 0936 lbu v0,6\(v1\)
+[ 0-9a-f]+: 0937 lbu v0,7\(v1\)
+[ 0-9a-f]+: 0938 lbu v0,8\(v1\)
+[ 0-9a-f]+: 0939 lbu v0,9\(v1\)
+[ 0-9a-f]+: 093a lbu v0,10\(v1\)
+[ 0-9a-f]+: 093b lbu v0,11\(v1\)
+[ 0-9a-f]+: 093c lbu v0,12\(v1\)
+[ 0-9a-f]+: 093d lbu v0,13\(v1\)
+[ 0-9a-f]+: 093e lbu v0,14\(v1\)
+[ 0-9a-f]+: 092e lbu v0,14\(v0\)
+[ 0-9a-f]+: 094e lbu v0,14\(a0\)
+[ 0-9a-f]+: 095e lbu v0,14\(a1\)
+[ 0-9a-f]+: 096e lbu v0,14\(a2\)
+[ 0-9a-f]+: 097e lbu v0,14\(a3\)
+[ 0-9a-f]+: 090e lbu v0,14\(s0\)
+[ 0-9a-f]+: 091e lbu v0,14\(s1\)
+[ 0-9a-f]+: 099e lbu v1,14\(s1\)
+[ 0-9a-f]+: 0a1e lbu a0,14\(s1\)
+[ 0-9a-f]+: 0a9e lbu a1,14\(s1\)
+[ 0-9a-f]+: 0b1e lbu a2,14\(s1\)
+[ 0-9a-f]+: 0b9e lbu a3,14\(s1\)
+[ 0-9a-f]+: 081e lbu s0,14\(s1\)
+[ 0-9a-f]+: 089e lbu s1,14\(s1\)
+[ 0-9a-f]+: 1460 0000 lbu v1,0\(zero\)
+[ 0-9a-f]+: 1460 0004 lbu v1,4\(zero\)
+[ 0-9a-f]+: 1460 0000 lbu v1,0\(zero\)
+[ 0-9a-f]+: 1460 0004 lbu v1,4\(zero\)
+[ 0-9a-f]+: 1460 7fff lbu v1,32767\(zero\)
+[ 0-9a-f]+: 1460 8000 lbu v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 1463 ffff lbu v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1460 8000 lbu v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 1463 0001 lbu v1,1\(v1\)
+[ 0-9a-f]+: 1460 8001 lbu v1,-32767\(zero\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1460 ffff lbu v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 1463 5678 lbu v1,22136\(v1\)
+[ 0-9a-f]+: 09c0 lbu v1,0\(a0\)
+[ 0-9a-f]+: 09c0 lbu v1,0\(a0\)
+[ 0-9a-f]+: 09c4 lbu v1,4\(a0\)
+[ 0-9a-f]+: 1464 7fff lbu v1,32767\(a0\)
+[ 0-9a-f]+: 1464 8000 lbu v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 ffff lbu v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1464 8000 lbu v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 0001 lbu v1,1\(v1\)
+[ 0-9a-f]+: 1464 8001 lbu v1,-32767\(a0\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1464 ffff lbu v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 5678 lbu v1,22136\(v1\)
+[ 0-9a-f]+: 3c60 0000 lh v1,0\(zero\)
+[ 0-9a-f]+: 3c60 0004 lh v1,4\(zero\)
+[ 0-9a-f]+: 3c60 0000 lh v1,0\(zero\)
+[ 0-9a-f]+: 3c60 0004 lh v1,4\(zero\)
+[ 0-9a-f]+: 3c60 7fff lh v1,32767\(zero\)
+[ 0-9a-f]+: 3c60 8000 lh v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 3c63 ffff lh v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c60 8000 lh v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 3c63 0001 lh v1,1\(v1\)
+[ 0-9a-f]+: 3c60 8001 lh v1,-32767\(zero\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c60 ffff lh v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 3c63 5678 lh v1,22136\(v1\)
+[ 0-9a-f]+: 3c64 0000 lh v1,0\(a0\)
+[ 0-9a-f]+: 3c64 0000 lh v1,0\(a0\)
+[ 0-9a-f]+: 3c64 0004 lh v1,4\(a0\)
+[ 0-9a-f]+: 3c64 7fff lh v1,32767\(a0\)
+[ 0-9a-f]+: 3c64 8000 lh v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 ffff lh v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c64 8000 lh v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 0001 lh v1,1\(v1\)
+[ 0-9a-f]+: 3c64 8001 lh v1,-32767\(a0\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c64 ffff lh v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 5678 lh v1,22136\(v1\)
+[ 0-9a-f]+: 2930 lhu v0,0\(v1\)
+[ 0-9a-f]+: 2930 lhu v0,0\(v1\)
+[ 0-9a-f]+: 2931 lhu v0,2\(v1\)
+[ 0-9a-f]+: 2932 lhu v0,4\(v1\)
+[ 0-9a-f]+: 2933 lhu v0,6\(v1\)
+[ 0-9a-f]+: 2934 lhu v0,8\(v1\)
+[ 0-9a-f]+: 2935 lhu v0,10\(v1\)
+[ 0-9a-f]+: 2936 lhu v0,12\(v1\)
+[ 0-9a-f]+: 2937 lhu v0,14\(v1\)
+[ 0-9a-f]+: 2938 lhu v0,16\(v1\)
+[ 0-9a-f]+: 2939 lhu v0,18\(v1\)
+[ 0-9a-f]+: 293a lhu v0,20\(v1\)
+[ 0-9a-f]+: 293b lhu v0,22\(v1\)
+[ 0-9a-f]+: 293c lhu v0,24\(v1\)
+[ 0-9a-f]+: 293d lhu v0,26\(v1\)
+[ 0-9a-f]+: 293e lhu v0,28\(v1\)
+[ 0-9a-f]+: 293f lhu v0,30\(v1\)
+[ 0-9a-f]+: 294f lhu v0,30\(a0\)
+[ 0-9a-f]+: 295f lhu v0,30\(a1\)
+[ 0-9a-f]+: 296f lhu v0,30\(a2\)
+[ 0-9a-f]+: 297f lhu v0,30\(a3\)
+[ 0-9a-f]+: 292f lhu v0,30\(v0\)
+[ 0-9a-f]+: 290f lhu v0,30\(s0\)
+[ 0-9a-f]+: 291f lhu v0,30\(s1\)
+[ 0-9a-f]+: 299f lhu v1,30\(s1\)
+[ 0-9a-f]+: 2a1f lhu a0,30\(s1\)
+[ 0-9a-f]+: 2a9f lhu a1,30\(s1\)
+[ 0-9a-f]+: 2b1f lhu a2,30\(s1\)
+[ 0-9a-f]+: 2b9f lhu a3,30\(s1\)
+[ 0-9a-f]+: 281f lhu s0,30\(s1\)
+[ 0-9a-f]+: 289f lhu s1,30\(s1\)
+[ 0-9a-f]+: 3460 0000 lhu v1,0\(zero\)
+[ 0-9a-f]+: 3460 0004 lhu v1,4\(zero\)
+[ 0-9a-f]+: 3460 0000 lhu v1,0\(zero\)
+[ 0-9a-f]+: 3460 0004 lhu v1,4\(zero\)
+[ 0-9a-f]+: 3460 7fff lhu v1,32767\(zero\)
+[ 0-9a-f]+: 3460 8000 lhu v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 3463 ffff lhu v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3460 8000 lhu v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 3463 0001 lhu v1,1\(v1\)
+[ 0-9a-f]+: 3460 8001 lhu v1,-32767\(zero\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3460 ffff lhu v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 3463 5678 lhu v1,22136\(v1\)
+[ 0-9a-f]+: 29c0 lhu v1,0\(a0\)
+[ 0-9a-f]+: 29c0 lhu v1,0\(a0\)
+[ 0-9a-f]+: 29c2 lhu v1,4\(a0\)
+[ 0-9a-f]+: 3464 7fff lhu v1,32767\(a0\)
+[ 0-9a-f]+: 3464 8000 lhu v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 ffff lhu v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3464 8000 lhu v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 0001 lhu v1,1\(v1\)
+[ 0-9a-f]+: 3464 8001 lhu v1,-32767\(a0\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3464 ffff lhu v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 5678 lhu v1,22136\(v1\)
+[ 0-9a-f]+: 6060 3000 ll v1,0\(zero\)
+[ 0-9a-f]+: 6060 3000 ll v1,0\(zero\)
+[ 0-9a-f]+: 6060 3004 ll v1,4\(zero\)
+[ 0-9a-f]+: 6060 3004 ll v1,4\(zero\)
+[ 0-9a-f]+: 5060 8000 li v1,0x8000
+[ 0-9a-f]+: 6063 3fff ll v1,-1\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 6063 3fff ll v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 6060 3fff ll v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 5063 5000 ori v1,v1,0x5000
+[ 0-9a-f]+: 6063 3678 ll v1,1656\(v1\)
+[ 0-9a-f]+: 6064 3000 ll v1,0\(a0\)
+[ 0-9a-f]+: 6064 3000 ll v1,0\(a0\)
+[ 0-9a-f]+: 6064 3004 ll v1,4\(a0\)
+[ 0-9a-f]+: 5060 8000 li v1,0x8000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3fff ll v1,-1\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3fff ll v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 6064 3fff ll v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 5063 5000 ori v1,v1,0x5000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3678 ll v1,1656\(v1\)
+[ 0-9a-f]+: 41a3 0000 lui v1,0x0
+[ 0-9a-f]+: 41a3 7fff lui v1,0x7fff
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 6940 lw v0,0\(a0\)
+[ 0-9a-f]+: 6940 lw v0,0\(a0\)
+[ 0-9a-f]+: 6941 lw v0,4\(a0\)
+[ 0-9a-f]+: 6942 lw v0,8\(a0\)
+[ 0-9a-f]+: 6943 lw v0,12\(a0\)
+[ 0-9a-f]+: 6944 lw v0,16\(a0\)
+[ 0-9a-f]+: 6945 lw v0,20\(a0\)
+[ 0-9a-f]+: 6946 lw v0,24\(a0\)
+[ 0-9a-f]+: 6947 lw v0,28\(a0\)
+[ 0-9a-f]+: 6948 lw v0,32\(a0\)
+[ 0-9a-f]+: 6949 lw v0,36\(a0\)
+[ 0-9a-f]+: 694a lw v0,40\(a0\)
+[ 0-9a-f]+: 694b lw v0,44\(a0\)
+[ 0-9a-f]+: 694c lw v0,48\(a0\)
+[ 0-9a-f]+: 694d lw v0,52\(a0\)
+[ 0-9a-f]+: 694e lw v0,56\(a0\)
+[ 0-9a-f]+: 694f lw v0,60\(a0\)
+[ 0-9a-f]+: 695f lw v0,60\(a1\)
+[ 0-9a-f]+: 696f lw v0,60\(a2\)
+[ 0-9a-f]+: 697f lw v0,60\(a3\)
+[ 0-9a-f]+: 692f lw v0,60\(v0\)
+[ 0-9a-f]+: 693f lw v0,60\(v1\)
+[ 0-9a-f]+: 690f lw v0,60\(s0\)
+[ 0-9a-f]+: 691f lw v0,60\(s1\)
+[ 0-9a-f]+: 699f lw v1,60\(s1\)
+[ 0-9a-f]+: 6a1f lw a0,60\(s1\)
+[ 0-9a-f]+: 6a9f lw a1,60\(s1\)
+[ 0-9a-f]+: 6b1f lw a2,60\(s1\)
+[ 0-9a-f]+: 6b9f lw a3,60\(s1\)
+[ 0-9a-f]+: 681f lw s0,60\(s1\)
+[ 0-9a-f]+: 689f lw s1,60\(s1\)
+[ 0-9a-f]+: 4880 lw a0,0\(sp\)
+[ 0-9a-f]+: 4880 lw a0,0\(sp\)
+[ 0-9a-f]+: 4881 lw a0,4\(sp\)
+[ 0-9a-f]+: 4882 lw a0,8\(sp\)
+[ 0-9a-f]+: 4883 lw a0,12\(sp\)
+[ 0-9a-f]+: 4884 lw a0,16\(sp\)
+[ 0-9a-f]+: 4885 lw a0,20\(sp\)
+[ 0-9a-f]+: 489f lw a0,124\(sp\)
+[ 0-9a-f]+: 485f lw v0,124\(sp\)
+[ 0-9a-f]+: 485f lw v0,124\(sp\)
+[ 0-9a-f]+: 487f lw v1,124\(sp\)
+[ 0-9a-f]+: 489f lw a0,124\(sp\)
+[ 0-9a-f]+: 48bf lw a1,124\(sp\)
+[ 0-9a-f]+: 48df lw a2,124\(sp\)
+[ 0-9a-f]+: 48ff lw a3,124\(sp\)
+[ 0-9a-f]+: 491f lw t0,124\(sp\)
+[ 0-9a-f]+: 493f lw t1,124\(sp\)
+[ 0-9a-f]+: 495f lw t2,124\(sp\)
+[ 0-9a-f]+: 4bdf lw s8,124\(sp\)
+[ 0-9a-f]+: 4bff lw ra,124\(sp\)
+[ 0-9a-f]+: fc9d 01f8 lw a0,504\(sp\)
+[ 0-9a-f]+: fc9d 01fc lw a0,508\(sp\)
+[ 0-9a-f]+: fe1d 01fc lw s0,508\(sp\)
+[ 0-9a-f]+: fe3d 01fc lw s1,508\(sp\)
+[ 0-9a-f]+: fe5d 01fc lw s2,508\(sp\)
+[ 0-9a-f]+: fe7d 01fc lw s3,508\(sp\)
+[ 0-9a-f]+: fe9d 01fc lw s4,508\(sp\)
+[ 0-9a-f]+: febd 01fc lw s5,508\(sp\)
+[ 0-9a-f]+: fffd 01fc lw ra,508\(sp\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc60 7fff lw v1,32767\(zero\)
+[ 0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: fc63 ffff lw v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: fc63 0001 lw v1,1\(v1\)
+[ 0-9a-f]+: fc60 8001 lw v1,-32767\(zero\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc60 ffff lw v1,-1\(zero\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: fc63 5678 lw v1,22136\(v1\)
+[ 0-9a-f]+: 69c0 lw v1,0\(a0\)
+[ 0-9a-f]+: 69c0 lw v1,0\(a0\)
+[ 0-9a-f]+: 69c1 lw v1,4\(a0\)
+[ 0-9a-f]+: fc64 7fff lw v1,32767\(a0\)
+[ 0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 ffff lw v1,-1\(v1\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ 0-9a-f]+: 41a3 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 0001 lw v1,1\(v1\)
+[ 0-9a-f]+: fc64 8001 lw v1,-32767\(a0\)
+[ 0-9a-f]+: 41a3 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc64 ffff lw v1,-1\(a0\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 5678 lw v1,22136\(v1\)
+[ 0-9a-f]+: 450c lwm s0,ra,48\(sp\)
+[ 0-9a-f]+: 451c lwm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 451c lwm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 452c lwm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 452c lwm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 453c lwm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 453c lwm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 4500 lwm s0,ra,0\(sp\)
+[ 0-9a-f]+: 4500 lwm s0,ra,0\(sp\)
+[ 0-9a-f]+: 4501 lwm s0,ra,4\(sp\)
+[ 0-9a-f]+: 4502 lwm s0,ra,8\(sp\)
+[ 0-9a-f]+: 4503 lwm s0,ra,12\(sp\)
+[ 0-9a-f]+: 4504 lwm s0,ra,16\(sp\)
+[ 0-9a-f]+: 4505 lwm s0,ra,20\(sp\)
+[ 0-9a-f]+: 4506 lwm s0,ra,24\(sp\)
+[ 0-9a-f]+: 4507 lwm s0,ra,28\(sp\)
+[ 0-9a-f]+: 4508 lwm s0,ra,32\(sp\)
+[ 0-9a-f]+: 4509 lwm s0,ra,36\(sp\)
+[ 0-9a-f]+: 450a lwm s0,ra,40\(sp\)
+[ 0-9a-f]+: 450b lwm s0,ra,44\(sp\)
+[ 0-9a-f]+: 450c lwm s0,ra,48\(sp\)
+[ 0-9a-f]+: 450d lwm s0,ra,52\(sp\)
+[ 0-9a-f]+: 450e lwm s0,ra,56\(sp\)
+[ 0-9a-f]+: 450f lwm s0,ra,60\(sp\)
+[ 0-9a-f]+: 2020 5000 lwm s0,0\(zero\)
+[ 0-9a-f]+: 2020 5004 lwm s0,4\(zero\)
+[ 0-9a-f]+: 2025 5000 lwm s0,0\(a1\)
+[ 0-9a-f]+: 2025 57ff lwm s0,2047\(a1\)
+[ 0-9a-f]+: 2045 57ff lwm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 57ff lwm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 57ff lwm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 57ff lwm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 57ff lwm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 57ff lwm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 57ff lwm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 57ff lwm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 57ff lwm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 5000 lwm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 5000 lwm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 5000 lwm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 5000 lwm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 5000 lwm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 5000 lwm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 5000 lwm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 5000 lwm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 5000 lwm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+[ 0-9a-f]+: 2020 5000 lwm s0,0\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+[ 0-9a-f]+: 203d 5000 lwm s0,0\(sp\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+[ 0-9a-f]+: 2040 1000 lwp v0,0\(zero\)
+[ 0-9a-f]+: 2040 1004 lwp v0,4\(zero\)
+[ 0-9a-f]+: 205d 1000 lwp v0,0\(sp\)
+[ 0-9a-f]+: 205d 1000 lwp v0,0\(sp\)
+[ 0-9a-f]+: 2043 1800 lwp v0,-2048\(v1\)
+[ 0-9a-f]+: 2043 17ff lwp v0,2047\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 1000 lwp v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 1fff lwp v0,-1\(at\)
+[ 0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 1fff lwp v0,-1\(at\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
+[ 0-9a-f]+: 5060 8000 li v1,0x8000
+[ 0-9a-f]+: 2043 1fff lwp v0,-1\(v1\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 2043 1fff lwp v0,-1\(v1\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 07ff lwl v1,2047\(zero\)
+[ 0-9a-f]+: 6060 0800 lwl v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6060 0fff lwl v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 0678 lwl v1,1656\(at\)
+[ 0-9a-f]+: 6064 0000 lwl v1,0\(a0\)
+[ 0-9a-f]+: 6064 0000 lwl v1,0\(a0\)
+[ 0-9a-f]+: 6064 07ff lwl v1,2047\(a0\)
+[ 0-9a-f]+: 6064 0800 lwl v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6064 0fff lwl v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0678 lwl v1,1656\(at\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 07ff lwl v1,2047\(zero\)
+[ 0-9a-f]+: 6060 0800 lwl v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6060 0fff lwl v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 0678 lwl v1,1656\(at\)
+[ 0-9a-f]+: 6064 0000 lwl v1,0\(a0\)
+[ 0-9a-f]+: 6064 0000 lwl v1,0\(a0\)
+[ 0-9a-f]+: 6064 07ff lwl v1,2047\(a0\)
+[ 0-9a-f]+: 6064 0800 lwl v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0fff lwl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0001 lwl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6064 0fff lwl v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0678 lwl v1,1656\(at\)
+[ 0-9a-f]+: 6060 1004 lwr v1,4\(zero\)
+[ 0-9a-f]+: 6060 1004 lwr v1,4\(zero\)
+[ 0-9a-f]+: 6060 1000 lwr v1,0\(zero\)
+[ 0-9a-f]+: 6060 1000 lwr v1,0\(zero\)
+[ 0-9a-f]+: 6060 17ff lwr v1,2047\(zero\)
+[ 0-9a-f]+: 6060 1800 lwr v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 6060 1fff lwr v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 1678 lwr v1,1656\(at\)
+[ 0-9a-f]+: 6064 1000 lwr v1,0\(a0\)
+[ 0-9a-f]+: 6064 1000 lwr v1,0\(a0\)
+[ 0-9a-f]+: 6064 17ff lwr v1,2047\(a0\)
+[ 0-9a-f]+: 6064 1800 lwr v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 6064 1fff lwr v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1678 lwr v1,1656\(at\)
+[ 0-9a-f]+: 6060 1004 lwr v1,4\(zero\)
+[ 0-9a-f]+: 6060 1004 lwr v1,4\(zero\)
+[ 0-9a-f]+: 6060 1000 lwr v1,0\(zero\)
+[ 0-9a-f]+: 6060 1000 lwr v1,0\(zero\)
+[ 0-9a-f]+: 6060 17ff lwr v1,2047\(zero\)
+[ 0-9a-f]+: 6060 1800 lwr v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 6060 1fff lwr v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 1678 lwr v1,1656\(at\)
+[ 0-9a-f]+: 6064 1000 lwr v1,0\(a0\)
+[ 0-9a-f]+: 6064 1000 lwr v1,0\(a0\)
+[ 0-9a-f]+: 6064 17ff lwr v1,2047\(a0\)
+[ 0-9a-f]+: 6064 1800 lwr v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1fff lwr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1001 lwr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1000 lwr v1,0\(at\)
+[ 0-9a-f]+: 6064 1fff lwr v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 1678 lwr v1,1656\(at\)
+[ 0-9a-f]+: 0085 1918 lwxs v1,a0\(a1\)
+[ 0-9a-f]+: 00a4 cb3c madd a0,a1
+[ 0-9a-f]+: 00a4 db3c maddu a0,a1
+[ 0-9a-f]+: 0040 00fc mfc0 v0,c0_index
+[ 0-9a-f]+: 0041 00fc mfc0 v0,c0_random
+[ 0-9a-f]+: 0042 00fc mfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0043 00fc mfc0 v0,c0_entrylo1
+[ 0-9a-f]+: 0044 00fc mfc0 v0,c0_context
+[ 0-9a-f]+: 0045 00fc mfc0 v0,c0_pagemask
+[ 0-9a-f]+: 0046 00fc mfc0 v0,c0_wired
+[ 0-9a-f]+: 0047 00fc mfc0 v0,c0_hwrena
+[ 0-9a-f]+: 0048 00fc mfc0 v0,c0_badvaddr
+[ 0-9a-f]+: 0049 00fc mfc0 v0,c0_count
+[ 0-9a-f]+: 004a 00fc mfc0 v0,c0_entryhi
+[ 0-9a-f]+: 004b 00fc mfc0 v0,c0_compare
+[ 0-9a-f]+: 004c 00fc mfc0 v0,c0_status
+[ 0-9a-f]+: 004d 00fc mfc0 v0,c0_cause
+[ 0-9a-f]+: 004e 00fc mfc0 v0,c0_epc
+[ 0-9a-f]+: 004f 00fc mfc0 v0,c0_prid
+[ 0-9a-f]+: 0050 00fc mfc0 v0,c0_config
+[ 0-9a-f]+: 0051 00fc mfc0 v0,c0_lladdr
+[ 0-9a-f]+: 0052 00fc mfc0 v0,c0_watchlo
+[ 0-9a-f]+: 0053 00fc mfc0 v0,c0_watchhi
+[ 0-9a-f]+: 0054 00fc mfc0 v0,c0_xcontext
+[ 0-9a-f]+: 0055 00fc mfc0 v0,\$21
+[ 0-9a-f]+: 0056 00fc mfc0 v0,\$22
+[ 0-9a-f]+: 0057 00fc mfc0 v0,c0_debug
+[ 0-9a-f]+: 0058 00fc mfc0 v0,c0_depc
+[ 0-9a-f]+: 0059 00fc mfc0 v0,c0_perfcnt
+[ 0-9a-f]+: 005a 00fc mfc0 v0,c0_errctl
+[ 0-9a-f]+: 005b 00fc mfc0 v0,c0_cacheerr
+[ 0-9a-f]+: 005c 00fc mfc0 v0,c0_taglo
+[ 0-9a-f]+: 005d 00fc mfc0 v0,c0_taghi
+[ 0-9a-f]+: 005e 00fc mfc0 v0,c0_errorepc
+[ 0-9a-f]+: 005f 00fc mfc0 v0,c0_desave
+[ 0-9a-f]+: 0040 00fc mfc0 v0,c0_index
+[ 0-9a-f]+: 0040 08fc mfc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 0040 10fc mfc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 0040 18fc mfc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 0040 20fc mfc0 v0,\$0,4
+[ 0-9a-f]+: 0040 28fc mfc0 v0,\$0,5
+[ 0-9a-f]+: 0040 30fc mfc0 v0,\$0,6
+[ 0-9a-f]+: 0040 38fc mfc0 v0,\$0,7
+[ 0-9a-f]+: 0041 00fc mfc0 v0,c0_random
+[ 0-9a-f]+: 0041 08fc mfc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 0041 10fc mfc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 0041 18fc mfc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 0041 20fc mfc0 v0,c0_yqmask
+[ 0-9a-f]+: 0041 28fc mfc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 0041 30fc mfc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 0041 38fc mfc0 v0,\$1,7
+[ 0-9a-f]+: 0042 00fc mfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0042 08fc mfc0 v0,c0_tcstatus
+[ 0-9a-f]+: 0042 10fc mfc0 v0,c0_tcbind
+[ 0-9a-f]+: 0042 18fc mfc0 v0,c0_tcrestart
+[ 0-9a-f]+: 0042 20fc mfc0 v0,c0_tchalt
+[ 0-9a-f]+: 0042 28fc mfc0 v0,c0_tccontext
+[ 0-9a-f]+: 0042 30fc mfc0 v0,c0_tcschedule
+[ 0-9a-f]+: 0042 38fc mfc0 v0,c0_tcschefback
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 4602 mfhi v0
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 4604 mfhi a0
+[ 0-9a-f]+: 461d mfhi sp
+[ 0-9a-f]+: 461e mfhi s8
+[ 0-9a-f]+: 461f mfhi ra
+[ 0-9a-f]+: 0000 0d7c mfhi zero
+[ 0-9a-f]+: 0002 0d7c mfhi v0
+[ 0-9a-f]+: 0003 0d7c mfhi v1
+[ 0-9a-f]+: 0004 0d7c mfhi a0
+[ 0-9a-f]+: 001d 0d7c mfhi sp
+[ 0-9a-f]+: 001e 0d7c mfhi s8
+[ 0-9a-f]+: 001f 0d7c mfhi ra
+[ 0-9a-f]+: 4640 mflo zero
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 4644 mflo a0
+[ 0-9a-f]+: 465d mflo sp
+[ 0-9a-f]+: 465e mflo s8
+[ 0-9a-f]+: 465f mflo ra
+[ 0-9a-f]+: 0000 1d7c mflo zero
+[ 0-9a-f]+: 0002 1d7c mflo v0
+[ 0-9a-f]+: 0003 1d7c mflo v1
+[ 0-9a-f]+: 0004 1d7c mflo a0
+[ 0-9a-f]+: 001d 1d7c mflo sp
+[ 0-9a-f]+: 001e 1d7c mflo s8
+[ 0-9a-f]+: 001f 1d7c mflo ra
+[ 0-9a-f]+: 0062 1018 movn v0,v0,v1
+[ 0-9a-f]+: 0062 1018 movn v0,v0,v1
+[ 0-9a-f]+: 0083 1018 movn v0,v1,a0
+[ 0-9a-f]+: 0062 1058 movz v0,v0,v1
+[ 0-9a-f]+: 0062 1058 movz v0,v0,v1
+[ 0-9a-f]+: 0083 1058 movz v0,v1,a0
+[ 0-9a-f]+: 00a4 eb3c msub a0,a1
+[ 0-9a-f]+: 00a4 fb3c msubu a0,a1
+[ 0-9a-f]+: 0040 02fc mtc0 v0,c0_index
+[ 0-9a-f]+: 0041 02fc mtc0 v0,c0_random
+[ 0-9a-f]+: 0042 02fc mtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0043 02fc mtc0 v0,c0_entrylo1
+[ 0-9a-f]+: 0044 02fc mtc0 v0,c0_context
+[ 0-9a-f]+: 0045 02fc mtc0 v0,c0_pagemask
+[ 0-9a-f]+: 0046 02fc mtc0 v0,c0_wired
+[ 0-9a-f]+: 0047 02fc mtc0 v0,c0_hwrena
+[ 0-9a-f]+: 0048 02fc mtc0 v0,c0_badvaddr
+[ 0-9a-f]+: 0049 02fc mtc0 v0,c0_count
+[ 0-9a-f]+: 004a 02fc mtc0 v0,c0_entryhi
+[ 0-9a-f]+: 004b 02fc mtc0 v0,c0_compare
+[ 0-9a-f]+: 004c 02fc mtc0 v0,c0_status
+[ 0-9a-f]+: 004d 02fc mtc0 v0,c0_cause
+[ 0-9a-f]+: 004e 02fc mtc0 v0,c0_epc
+[ 0-9a-f]+: 004f 02fc mtc0 v0,c0_prid
+[ 0-9a-f]+: 0050 02fc mtc0 v0,c0_config
+[ 0-9a-f]+: 0051 02fc mtc0 v0,c0_lladdr
+[ 0-9a-f]+: 0052 02fc mtc0 v0,c0_watchlo
+[ 0-9a-f]+: 0053 02fc mtc0 v0,c0_watchhi
+[ 0-9a-f]+: 0054 02fc mtc0 v0,c0_xcontext
+[ 0-9a-f]+: 0055 02fc mtc0 v0,\$21
+[ 0-9a-f]+: 0056 02fc mtc0 v0,\$22
+[ 0-9a-f]+: 0057 02fc mtc0 v0,c0_debug
+[ 0-9a-f]+: 0058 02fc mtc0 v0,c0_depc
+[ 0-9a-f]+: 0059 02fc mtc0 v0,c0_perfcnt
+[ 0-9a-f]+: 005a 02fc mtc0 v0,c0_errctl
+[ 0-9a-f]+: 005b 02fc mtc0 v0,c0_cacheerr
+[ 0-9a-f]+: 005c 02fc mtc0 v0,c0_taglo
+[ 0-9a-f]+: 005d 02fc mtc0 v0,c0_taghi
+[ 0-9a-f]+: 005e 02fc mtc0 v0,c0_errorepc
+[ 0-9a-f]+: 005f 02fc mtc0 v0,c0_desave
+[ 0-9a-f]+: 0040 02fc mtc0 v0,c0_index
+[ 0-9a-f]+: 0040 0afc mtc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 0040 12fc mtc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 0040 1afc mtc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 0040 22fc mtc0 v0,\$0,4
+[ 0-9a-f]+: 0040 2afc mtc0 v0,\$0,5
+[ 0-9a-f]+: 0040 32fc mtc0 v0,\$0,6
+[ 0-9a-f]+: 0040 3afc mtc0 v0,\$0,7
+[ 0-9a-f]+: 0041 02fc mtc0 v0,c0_random
+[ 0-9a-f]+: 0041 0afc mtc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 0041 12fc mtc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 0041 1afc mtc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 0041 22fc mtc0 v0,c0_yqmask
+[ 0-9a-f]+: 0041 2afc mtc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 0041 32fc mtc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 0041 3afc mtc0 v0,\$1,7
+[ 0-9a-f]+: 0042 02fc mtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0042 0afc mtc0 v0,c0_tcstatus
+[ 0-9a-f]+: 0042 12fc mtc0 v0,c0_tcbind
+[ 0-9a-f]+: 0042 1afc mtc0 v0,c0_tcrestart
+[ 0-9a-f]+: 0042 22fc mtc0 v0,c0_tchalt
+[ 0-9a-f]+: 0042 2afc mtc0 v0,c0_tccontext
+[ 0-9a-f]+: 0042 32fc mtc0 v0,c0_tcschedule
+[ 0-9a-f]+: 0042 3afc mtc0 v0,c0_tcschefback
+[ 0-9a-f]+: 0000 2d7c mthi zero
+[ 0-9a-f]+: 0002 2d7c mthi v0
+[ 0-9a-f]+: 0003 2d7c mthi v1
+[ 0-9a-f]+: 0004 2d7c mthi a0
+[ 0-9a-f]+: 001d 2d7c mthi sp
+[ 0-9a-f]+: 001e 2d7c mthi s8
+[ 0-9a-f]+: 001f 2d7c mthi ra
+[ 0-9a-f]+: 0000 3d7c mtlo zero
+[ 0-9a-f]+: 0002 3d7c mtlo v0
+[ 0-9a-f]+: 0003 3d7c mtlo v1
+[ 0-9a-f]+: 0004 3d7c mtlo a0
+[ 0-9a-f]+: 001d 3d7c mtlo sp
+[ 0-9a-f]+: 001e 3d7c mtlo s8
+[ 0-9a-f]+: 001f 3d7c mtlo ra
+[ 0-9a-f]+: 0083 1210 mul v0,v1,a0
+[ 0-9a-f]+: 03fe ea10 mul sp,s8,ra
+[ 0-9a-f]+: 0082 1210 mul v0,v0,a0
+[ 0-9a-f]+: 0082 1210 mul v0,v0,a0
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0022 8b3c mult v0,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 0022 8b3c mult v0,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0022 8b3c mult v0,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 8b3c mult v0,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 8b3c mult v0,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0083 8b3c mult v1,a0
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 9422 fffe beq v0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 3020 0004 li at,4
+[ 0-9a-f]+: 0023 8b3c mult v1,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 9422 fffe beq v0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 0083 9b3c multu v1,a0
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 0004 li at,4
+[ 0-9a-f]+: 0023 9b3c multu v1,at
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0062 8b3c mult v0,v1
+[ 0-9a-f]+: 0062 9b3c multu v0,v1
+[ 0-9a-f]+: 0060 1190 neg v0,v1
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+[ 0-9a-f]+: 0060 11d0 negu v0,v1
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0060 11d0 negu v0,v1
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 4412 not v0,v0
+[ 0-9a-f]+: 4412 not v0,v0
+[ 0-9a-f]+: 4413 not v0,v1
+[ 0-9a-f]+: 4414 not v0,a0
+[ 0-9a-f]+: 4415 not v0,a1
+[ 0-9a-f]+: 4416 not v0,a2
+[ 0-9a-f]+: 4417 not v0,a3
+[ 0-9a-f]+: 4410 not v0,s0
+[ 0-9a-f]+: 4411 not v0,s1
+[ 0-9a-f]+: 4419 not v1,s1
+[ 0-9a-f]+: 4421 not a0,s1
+[ 0-9a-f]+: 4429 not a1,s1
+[ 0-9a-f]+: 4431 not a2,s1
+[ 0-9a-f]+: 4439 not a3,s1
+[ 0-9a-f]+: 4401 not s0,s1
+[ 0-9a-f]+: 4409 not s1,s1
+[ 0-9a-f]+: 4417 not v0,a3
+[ 0-9a-f]+: 4417 not v0,a3
+[ 0-9a-f]+: 0083 12d0 nor v0,v1,a0
+[ 0-9a-f]+: 03fe ead0 nor sp,s8,ra
+[ 0-9a-f]+: 0082 12d0 nor v0,v0,a0
+[ 0-9a-f]+: 0082 12d0 nor v0,v0,a0
+[ 0-9a-f]+: 5043 8000 ori v0,v1,0x8000
+[ 0-9a-f]+: 0002 12d0 not v0,v0
+[ 0-9a-f]+: 5043 ffff ori v0,v1,0xffff
+[ 0-9a-f]+: 0002 12d0 not v0,v0
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 0c56 move v0,s6
+[ 0-9a-f]+: 0ec2 move s6,v0
+[ 0-9a-f]+: 44d2 or v0,v0,v0
+[ 0-9a-f]+: 44d3 or v0,v0,v1
+[ 0-9a-f]+: 44d4 or v0,v0,a0
+[ 0-9a-f]+: 44d5 or v0,v0,a1
+[ 0-9a-f]+: 44d6 or v0,v0,a2
+[ 0-9a-f]+: 44d7 or v0,v0,a3
+[ 0-9a-f]+: 44d0 or v0,v0,s0
+[ 0-9a-f]+: 44d1 or v0,v0,s1
+[ 0-9a-f]+: 44da or v1,v1,v0
+[ 0-9a-f]+: 44e2 or a0,a0,v0
+[ 0-9a-f]+: 44ea or a1,a1,v0
+[ 0-9a-f]+: 44f2 or a2,a2,v0
+[ 0-9a-f]+: 44fa or a3,a3,v0
+[ 0-9a-f]+: 44c2 or s0,s0,v0
+[ 0-9a-f]+: 44ca or s1,s1,v0
+[ 0-9a-f]+: 44d2 or v0,v0,v0
+[ 0-9a-f]+: 44d3 or v0,v0,v1
+[ 0-9a-f]+: 44d3 or v0,v0,v1
+[ 0-9a-f]+: 0083 1290 or v0,v1,a0
+[ 0-9a-f]+: 03fe ea90 or sp,s8,ra
+[ 0-9a-f]+: 0082 1290 or v0,v0,a0
+[ 0-9a-f]+: 0082 1290 or v0,v0,a0
+[ 0-9a-f]+: 5043 8000 ori v0,v1,0x8000
+[ 0-9a-f]+: 5043 ffff ori v0,v1,0xffff
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1290 or v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0023 1290 or v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1290 or v0,v1,at
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 5064 7fff ori v1,a0,0x7fff
+[ 0-9a-f]+: 5064 ffff ori v1,a0,0xffff
+[ 0-9a-f]+: 5063 ffff ori v1,v1,0xffff
+[ 0-9a-f]+: 5063 ffff ori v1,v1,0xffff
+[ 0-9a-f]+: 0040 6b3c rdhwr v0,hwr_cpunum
+[ 0-9a-f]+: 0041 6b3c rdhwr v0,hwr_synci_step
+[ 0-9a-f]+: 0042 6b3c rdhwr v0,hwr_cc
+[ 0-9a-f]+: 0043 6b3c rdhwr v0,hwr_ccres
+[ 0-9a-f]+: 0044 6b3c rdhwr v0,\$4
+[ 0-9a-f]+: 0045 6b3c rdhwr v0,\$5
+[ 0-9a-f]+: 0046 6b3c rdhwr v0,\$6
+[ 0-9a-f]+: 0047 6b3c rdhwr v0,\$7
+[ 0-9a-f]+: 0048 6b3c rdhwr v0,\$8
+[ 0-9a-f]+: 0049 6b3c rdhwr v0,\$9
+[ 0-9a-f]+: 004a 6b3c rdhwr v0,\$10
+[ 0-9a-f]+: 0043 e17c rdpgpr v0,v1
+[ 0-9a-f]+: 0042 e17c rdpgpr v0,v0
+[ 0-9a-f]+: 0042 e17c rdpgpr v0,v0
+[ 0-9a-f]+: 0062 ab3c div zero,v0,v1
+[ 0-9a-f]+: 03fe ab3c div zero,s8,ra
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0060 ab3c div zero,zero,v1
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b423 fffe bne v1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: b420 fffe bne zero,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: b41f fffe bnez ra,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03e0 ab3c div zero,zero,ra
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b43f fffe bne ra,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: b420 fffe bne zero,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: b404 fffe bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0083 ab3c div zero,v1,a0
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b424 fffe bne a0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: b423 fffe bne v1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4602 mfhi v0
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 0024 ab3c div zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 0062 bb3c divu zero,v0,v1
+[ 0-9a-f]+: 03fe bb3c divu zero,s8,ra
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0060 bb3c divu zero,zero,v1
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: b41f fffe bnez ra,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 03e0 bb3c divu zero,zero,ra
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: b400 fffe bnez zero,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0003 bb3c divu zero,v1,zero
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4602 mfhi v0
+[ 0-9a-f]+: b404 fffe bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0083 bb3c divu zero,v1,a0
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4602 mfhi v0
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0024 bb3c divu zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 0024 bb3c divu zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 0080 11d0 negu v0,a0
+[ 0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ 0-9a-f]+: 0080 09d0 negu at,a0
+[ 0-9a-f]+: 0041 10d0 rorv v0,v0,at
+[ 0-9a-f]+: 0060 11d0 negu v0,v1
+[ 0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ 0-9a-f]+: 0043 00c0 ror v0,v1,0x0
+[ 0-9a-f]+: 0043 f8c0 ror v0,v1,0x1f
+[ 0-9a-f]+: 0043 08c0 ror v0,v1,0x1
+[ 0-9a-f]+: 0042 08c0 ror v0,v0,0x1
+[ 0-9a-f]+: 0042 08c0 ror v0,v0,0x1
+[ 0-9a-f]+: 0043 00c0 ror v0,v1,0x0
+[ 0-9a-f]+: 0043 08c0 ror v0,v1,0x1
+[ 0-9a-f]+: 0043 f8c0 ror v0,v1,0x1f
+[ 0-9a-f]+: 0042 f8c0 ror v0,v0,0x1f
+[ 0-9a-f]+: 0042 f8c0 ror v0,v0,0x1f
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 8830 sb zero,0\(v1\)
+[ 0-9a-f]+: 8830 sb zero,0\(v1\)
+[ 0-9a-f]+: 8831 sb zero,1\(v1\)
+[ 0-9a-f]+: 8832 sb zero,2\(v1\)
+[ 0-9a-f]+: 8833 sb zero,3\(v1\)
+[ 0-9a-f]+: 8834 sb zero,4\(v1\)
+[ 0-9a-f]+: 8835 sb zero,5\(v1\)
+[ 0-9a-f]+: 8836 sb zero,6\(v1\)
+[ 0-9a-f]+: 8837 sb zero,7\(v1\)
+[ 0-9a-f]+: 8838 sb zero,8\(v1\)
+[ 0-9a-f]+: 8839 sb zero,9\(v1\)
+[ 0-9a-f]+: 883a sb zero,10\(v1\)
+[ 0-9a-f]+: 883b sb zero,11\(v1\)
+[ 0-9a-f]+: 883c sb zero,12\(v1\)
+[ 0-9a-f]+: 883d sb zero,13\(v1\)
+[ 0-9a-f]+: 883e sb zero,14\(v1\)
+[ 0-9a-f]+: 883f sb zero,15\(v1\)
+[ 0-9a-f]+: 893f sb v0,15\(v1\)
+[ 0-9a-f]+: 89bf sb v1,15\(v1\)
+[ 0-9a-f]+: 8a3f sb a0,15\(v1\)
+[ 0-9a-f]+: 8abf sb a1,15\(v1\)
+[ 0-9a-f]+: 8b3f sb a2,15\(v1\)
+[ 0-9a-f]+: 8bbf sb a3,15\(v1\)
+[ 0-9a-f]+: 88bf sb s1,15\(v1\)
+[ 0-9a-f]+: 88cf sb s1,15\(a0\)
+[ 0-9a-f]+: 88df sb s1,15\(a1\)
+[ 0-9a-f]+: 88ef sb s1,15\(a2\)
+[ 0-9a-f]+: 88ff sb s1,15\(a3\)
+[ 0-9a-f]+: 88af sb s1,15\(v0\)
+[ 0-9a-f]+: 888f sb s1,15\(s0\)
+[ 0-9a-f]+: 889f sb s1,15\(s1\)
+[ 0-9a-f]+: 1860 0004 sb v1,4\(zero\)
+[ 0-9a-f]+: 1860 0004 sb v1,4\(zero\)
+[ 0-9a-f]+: 1860 7fff sb v1,32767\(zero\)
+[ 0-9a-f]+: 1860 8000 sb v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 1861 ffff sb v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1860 8000 sb v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 1860 8001 sb v1,-32767\(zero\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1860 ffff sb v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 1861 5678 sb v1,22136\(at\)
+[ 0-9a-f]+: 1864 0000 sb v1,0\(a0\)
+[ 0-9a-f]+: 1864 0000 sb v1,0\(a0\)
+[ 0-9a-f]+: 1864 7fff sb v1,32767\(a0\)
+[ 0-9a-f]+: 1864 8000 sb v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 ffff sb v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1864 8000 sb v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 1864 8001 sb v1,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1864 ffff sb v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 5678 sb v1,22136\(at\)
+[ 0-9a-f]+: 6060 b004 sc v1,4\(zero\)
+[ 0-9a-f]+: 6060 b004 sc v1,4\(zero\)
+[ 0-9a-f]+: 6060 b7ff sc v1,2047\(zero\)
+[ 0-9a-f]+: 6060 b800 sc v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 bfff sc v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 bfff sc v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 6060 bfff sc v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 b678 sc v1,1656\(at\)
+[ 0-9a-f]+: 6064 b000 sc v1,0\(a0\)
+[ 0-9a-f]+: 6064 b000 sc v1,0\(a0\)
+[ 0-9a-f]+: 6064 b7ff sc v1,2047\(a0\)
+[ 0-9a-f]+: 6064 b800 sc v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 bfff sc v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 bfff sc v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 6064 bfff sc v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b678 sc v1,1656\(at\)
+[ 0-9a-f]+: 46c0 sdbbp
+[ 0-9a-f]+: 46c0 sdbbp
+[ 0-9a-f]+: 46c1 sdbbp 0x1
+[ 0-9a-f]+: 46c2 sdbbp 0x2
+[ 0-9a-f]+: 46c3 sdbbp 0x3
+[ 0-9a-f]+: 46c4 sdbbp 0x4
+[ 0-9a-f]+: 46c5 sdbbp 0x5
+[ 0-9a-f]+: 46c6 sdbbp 0x6
+[ 0-9a-f]+: 46c7 sdbbp 0x7
+[ 0-9a-f]+: 46c8 sdbbp 0x8
+[ 0-9a-f]+: 46c9 sdbbp 0x9
+[ 0-9a-f]+: 46ca sdbbp 0xa
+[ 0-9a-f]+: 46cb sdbbp 0xb
+[ 0-9a-f]+: 46cc sdbbp 0xc
+[ 0-9a-f]+: 46cd sdbbp 0xd
+[ 0-9a-f]+: 46ce sdbbp 0xe
+[ 0-9a-f]+: 46cf sdbbp 0xf
+[ 0-9a-f]+: 0000 db7c sdbbp
+[ 0-9a-f]+: 0000 db7c sdbbp
+[ 0-9a-f]+: 0001 db7c sdbbp 0x1
+[ 0-9a-f]+: 0002 db7c sdbbp 0x2
+[ 0-9a-f]+: 00ff db7c sdbbp 0xff
+[ 0-9a-f]+: 0043 2b3c seb v0,v1
+[ 0-9a-f]+: 0042 2b3c seb v0,v0
+[ 0-9a-f]+: 0042 2b3c seb v0,v0
+[ 0-9a-f]+: 0043 3b3c seh v0,v1
+[ 0-9a-f]+: 0042 3b3c seh v0,v0
+[ 0-9a-f]+: 0042 3b3c seh v0,v0
+[ 0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: b043 0001 sltiu v0,v1,1
+[ 0-9a-f]+: b044 0001 sltiu v0,a0,1
+[ 0-9a-f]+: b043 0001 sltiu v0,v1,1
+[ 0-9a-f]+: 7043 0001 xori v0,v1,0x1
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: 3043 0001 addiu v0,v1,1
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: 0083 1350 slt v0,v1,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 8000 slti v0,v1,-32768
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 7fff slti v0,v1,32767
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0083 1390 sltu v0,v1,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 8000 sltiu v0,v1,-32768
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 7fff sltiu v0,v1,32767
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0064 1350 slt v0,a0,v1
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 0064 1390 sltu v0,a0,v1
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: a930 sh v0,0\(v1\)
+[ 0-9a-f]+: a930 sh v0,0\(v1\)
+[ 0-9a-f]+: a931 sh v0,2\(v1\)
+[ 0-9a-f]+: a932 sh v0,4\(v1\)
+[ 0-9a-f]+: a933 sh v0,6\(v1\)
+[ 0-9a-f]+: a934 sh v0,8\(v1\)
+[ 0-9a-f]+: a935 sh v0,10\(v1\)
+[ 0-9a-f]+: a936 sh v0,12\(v1\)
+[ 0-9a-f]+: a937 sh v0,14\(v1\)
+[ 0-9a-f]+: a938 sh v0,16\(v1\)
+[ 0-9a-f]+: a939 sh v0,18\(v1\)
+[ 0-9a-f]+: a93a sh v0,20\(v1\)
+[ 0-9a-f]+: a93b sh v0,22\(v1\)
+[ 0-9a-f]+: a93c sh v0,24\(v1\)
+[ 0-9a-f]+: a93d sh v0,26\(v1\)
+[ 0-9a-f]+: a93e sh v0,28\(v1\)
+[ 0-9a-f]+: a93f sh v0,30\(v1\)
+[ 0-9a-f]+: a94f sh v0,30\(a0\)
+[ 0-9a-f]+: a95f sh v0,30\(a1\)
+[ 0-9a-f]+: a96f sh v0,30\(a2\)
+[ 0-9a-f]+: a97f sh v0,30\(a3\)
+[ 0-9a-f]+: a92f sh v0,30\(v0\)
+[ 0-9a-f]+: a90f sh v0,30\(s0\)
+[ 0-9a-f]+: a91f sh v0,30\(s1\)
+[ 0-9a-f]+: a99f sh v1,30\(s1\)
+[ 0-9a-f]+: aa1f sh a0,30\(s1\)
+[ 0-9a-f]+: aa9f sh a1,30\(s1\)
+[ 0-9a-f]+: ab1f sh a2,30\(s1\)
+[ 0-9a-f]+: ab9f sh a3,30\(s1\)
+[ 0-9a-f]+: a89f sh s1,30\(s1\)
+[ 0-9a-f]+: a81f sh zero,30\(s1\)
+[ 0-9a-f]+: 3860 0004 sh v1,4\(zero\)
+[ 0-9a-f]+: 3860 0004 sh v1,4\(zero\)
+[ 0-9a-f]+: 3860 7fff sh v1,32767\(zero\)
+[ 0-9a-f]+: 3860 8000 sh v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 3861 ffff sh v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3860 8000 sh v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 3861 0001 sh v1,1\(at\)
+[ 0-9a-f]+: 3860 8001 sh v1,-32767\(zero\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3860 ffff sh v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 3861 5678 sh v1,22136\(at\)
+[ 0-9a-f]+: 3864 0000 sh v1,0\(a0\)
+[ 0-9a-f]+: 3864 0000 sh v1,0\(a0\)
+[ 0-9a-f]+: 3864 7fff sh v1,32767\(a0\)
+[ 0-9a-f]+: 3864 8000 sh v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 ffff sh v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3864 8000 sh v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 0001 sh v1,1\(at\)
+[ 0-9a-f]+: 3864 8001 sh v1,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3864 ffff sh v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 5678 sh v1,22136\(at\)
+[ 0-9a-f]+: 0064 1350 slt v0,a0,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0064 1390 sltu v0,a0,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 2522 sll v0,v0,1
+[ 0-9a-f]+: 2524 sll v0,v0,2
+[ 0-9a-f]+: 2526 sll v0,v0,3
+[ 0-9a-f]+: 2528 sll v0,v0,4
+[ 0-9a-f]+: 252a sll v0,v0,5
+[ 0-9a-f]+: 252c sll v0,v0,6
+[ 0-9a-f]+: 252e sll v0,v0,7
+[ 0-9a-f]+: 2520 sll v0,v0,8
+[ 0-9a-f]+: 2530 sll v0,v1,8
+[ 0-9a-f]+: 2540 sll v0,a0,8
+[ 0-9a-f]+: 2550 sll v0,a1,8
+[ 0-9a-f]+: 2560 sll v0,a2,8
+[ 0-9a-f]+: 2570 sll v0,a3,8
+[ 0-9a-f]+: 2500 sll v0,s0,8
+[ 0-9a-f]+: 2510 sll v0,s1,8
+[ 0-9a-f]+: 25a0 sll v1,v0,8
+[ 0-9a-f]+: 2620 sll a0,v0,8
+[ 0-9a-f]+: 26a0 sll a1,v0,8
+[ 0-9a-f]+: 2720 sll a2,v0,8
+[ 0-9a-f]+: 27a0 sll a3,v0,8
+[ 0-9a-f]+: 2420 sll s0,v0,8
+[ 0-9a-f]+: 24a0 sll s1,v0,8
+[ 0-9a-f]+: 2522 sll v0,v0,1
+[ 0-9a-f]+: 25b2 sll v1,v1,1
+[ 0-9a-f]+: 0064 1010 sllv v0,v1,a0
+[ 0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ 0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ 0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ 0-9a-f]+: 0044 0000 sll v0,a0,0x0
+[ 0-9a-f]+: 0044 0800 sll v0,a0,0x1
+[ 0-9a-f]+: 0044 f800 sll v0,a0,0x1f
+[ 0-9a-f]+: 0042 f800 sll v0,v0,0x1f
+[ 0-9a-f]+: 0042 f800 sll v0,v0,0x1f
+[ 0-9a-f]+: 0083 1350 slt v0,v1,a0
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 9043 8000 slti v0,v1,-32768
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 9043 7fff slti v0,v1,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 9064 8000 slti v1,a0,-32768
+[ 0-9a-f]+: 9064 0000 slti v1,a0,0
+[ 0-9a-f]+: 9064 7fff slti v1,a0,32767
+[ 0-9a-f]+: 9064 ffff slti v1,a0,-1
+[ 0-9a-f]+: 9063 ffff slti v1,v1,-1
+[ 0-9a-f]+: 9063 ffff slti v1,v1,-1
+[ 0-9a-f]+: b064 8000 sltiu v1,a0,-32768
+[ 0-9a-f]+: b064 0000 sltiu v1,a0,0
+[ 0-9a-f]+: b064 7fff sltiu v1,a0,32767
+[ 0-9a-f]+: b064 ffff sltiu v1,a0,-1
+[ 0-9a-f]+: b063 ffff sltiu v1,v1,-1
+[ 0-9a-f]+: b063 ffff sltiu v1,v1,-1
+[ 0-9a-f]+: 0083 1390 sltu v0,v1,a0
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: b043 8000 sltiu v0,v1,-32768
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: b043 7fff sltiu v0,v1,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 0080 1390 sltu v0,zero,a0
+[ 0-9a-f]+: 0060 1390 sltu v0,zero,v1
+[ 0-9a-f]+: 0060 1390 sltu v0,zero,v1
+[ 0-9a-f]+: 7043 0001 xori v0,v1,0x1
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 3043 0001 addiu v0,v1,1
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 0064 1090 srav v0,v1,a0
+[ 0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ 0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ 0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ 0-9a-f]+: 0044 0080 sra v0,a0,0x0
+[ 0-9a-f]+: 0044 0880 sra v0,a0,0x1
+[ 0-9a-f]+: 0044 f880 sra v0,a0,0x1f
+[ 0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ 0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ 0-9a-f]+: 0064 1050 srlv v0,v1,a0
+[ 0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ 0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ 0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ 0-9a-f]+: 0044 0040 srl v0,a0,0x0
+[ 0-9a-f]+: 2543 srl v0,a0,1
+[ 0-9a-f]+: 0044 f840 srl v0,a0,0x1f
+[ 0-9a-f]+: 0042 f840 srl v0,v0,0x1f
+[ 0-9a-f]+: 0042 f840 srl v0,v0,0x1f
+[ 0-9a-f]+: 2523 srl v0,v0,1
+[ 0-9a-f]+: 2525 srl v0,v0,2
+[ 0-9a-f]+: 2527 srl v0,v0,3
+[ 0-9a-f]+: 2529 srl v0,v0,4
+[ 0-9a-f]+: 252b srl v0,v0,5
+[ 0-9a-f]+: 252d srl v0,v0,6
+[ 0-9a-f]+: 252f srl v0,v0,7
+[ 0-9a-f]+: 2521 srl v0,v0,8
+[ 0-9a-f]+: 2531 srl v0,v1,8
+[ 0-9a-f]+: 2541 srl v0,a0,8
+[ 0-9a-f]+: 2551 srl v0,a1,8
+[ 0-9a-f]+: 2561 srl v0,a2,8
+[ 0-9a-f]+: 2571 srl v0,a3,8
+[ 0-9a-f]+: 2501 srl v0,s0,8
+[ 0-9a-f]+: 2511 srl v0,s1,8
+[ 0-9a-f]+: 2521 srl v0,v0,8
+[ 0-9a-f]+: 25a1 srl v1,v0,8
+[ 0-9a-f]+: 2621 srl a0,v0,8
+[ 0-9a-f]+: 26a1 srl a1,v0,8
+[ 0-9a-f]+: 2721 srl a2,v0,8
+[ 0-9a-f]+: 27a1 srl a3,v0,8
+[ 0-9a-f]+: 2421 srl s0,v0,8
+[ 0-9a-f]+: 24a1 srl s1,v0,8
+[ 0-9a-f]+: 25b3 srl v1,v1,1
+[ 0-9a-f]+: 25b3 srl v1,v1,1
+[ 0-9a-f]+: 0083 1190 sub v0,v1,a0
+[ 0-9a-f]+: 03fe e990 sub sp,s8,ra
+[ 0-9a-f]+: 0082 1190 sub v0,v0,a0
+[ 0-9a-f]+: 0082 1190 sub v0,v0,a0
+[ 0-9a-f]+: 1042 0000 addi v0,v0,0
+[ 0-9a-f]+: 1042 ffff addi v0,v0,-1
+[ 0-9a-f]+: 1042 8001 addi v0,v0,-32767
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 1190 sub v0,v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 1190 sub v0,v0,at
+[ 0-9a-f]+: 0527 subu v0,v1,v0
+[ 0-9a-f]+: 0537 subu v0,v1,v1
+[ 0-9a-f]+: 0547 subu v0,v1,a0
+[ 0-9a-f]+: 0557 subu v0,v1,a1
+[ 0-9a-f]+: 0567 subu v0,v1,a2
+[ 0-9a-f]+: 0577 subu v0,v1,a3
+[ 0-9a-f]+: 0507 subu v0,v1,s0
+[ 0-9a-f]+: 0517 subu v0,v1,s1
+[ 0-9a-f]+: 0515 subu v0,v0,s1
+[ 0-9a-f]+: 0519 subu v0,a0,s1
+[ 0-9a-f]+: 051b subu v0,a1,s1
+[ 0-9a-f]+: 051d subu v0,a2,s1
+[ 0-9a-f]+: 051f subu v0,a3,s1
+[ 0-9a-f]+: 0511 subu v0,s0,s1
+[ 0-9a-f]+: 0513 subu v0,s1,s1
+[ 0-9a-f]+: 0515 subu v0,v0,s1
+[ 0-9a-f]+: 0595 subu v1,v0,s1
+[ 0-9a-f]+: 0615 subu a0,v0,s1
+[ 0-9a-f]+: 0695 subu a1,v0,s1
+[ 0-9a-f]+: 0715 subu a2,v0,s1
+[ 0-9a-f]+: 0795 subu a3,v0,s1
+[ 0-9a-f]+: 0415 subu s0,v0,s1
+[ 0-9a-f]+: 0495 subu s1,v0,s1
+[ 0-9a-f]+: 07af subu a3,a3,v0
+[ 0-9a-f]+: 07af subu a3,a3,v0
+[ 0-9a-f]+: 0083 11d0 subu v0,v1,a0
+[ 0-9a-f]+: 03fe e9d0 subu sp,s8,ra
+[ 0-9a-f]+: 0082 11d0 subu v0,v0,a0
+[ 0-9a-f]+: 0082 11d0 subu v0,v0,a0
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ 0-9a-f]+: 3042 ffff addiu v0,v0,-1
+[ 0-9a-f]+: 3042 8001 addiu v0,v0,-32767
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 11d0 subu v0,v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 11d0 subu v0,v0,at
+[ 0-9a-f]+: e940 sw v0,0\(a0\)
+[ 0-9a-f]+: e940 sw v0,0\(a0\)
+[ 0-9a-f]+: e941 sw v0,4\(a0\)
+[ 0-9a-f]+: e942 sw v0,8\(a0\)
+[ 0-9a-f]+: e943 sw v0,12\(a0\)
+[ 0-9a-f]+: e944 sw v0,16\(a0\)
+[ 0-9a-f]+: e945 sw v0,20\(a0\)
+[ 0-9a-f]+: e946 sw v0,24\(a0\)
+[ 0-9a-f]+: e947 sw v0,28\(a0\)
+[ 0-9a-f]+: e948 sw v0,32\(a0\)
+[ 0-9a-f]+: e949 sw v0,36\(a0\)
+[ 0-9a-f]+: e94a sw v0,40\(a0\)
+[ 0-9a-f]+: e94b sw v0,44\(a0\)
+[ 0-9a-f]+: e94c sw v0,48\(a0\)
+[ 0-9a-f]+: e94d sw v0,52\(a0\)
+[ 0-9a-f]+: e94e sw v0,56\(a0\)
+[ 0-9a-f]+: e94f sw v0,60\(a0\)
+[ 0-9a-f]+: e95f sw v0,60\(a1\)
+[ 0-9a-f]+: e96f sw v0,60\(a2\)
+[ 0-9a-f]+: e97f sw v0,60\(a3\)
+[ 0-9a-f]+: e90f sw v0,60\(s0\)
+[ 0-9a-f]+: e91f sw v0,60\(s1\)
+[ 0-9a-f]+: e92f sw v0,60\(v0\)
+[ 0-9a-f]+: e93f sw v0,60\(v1\)
+[ 0-9a-f]+: e9bf sw v1,60\(v1\)
+[ 0-9a-f]+: ea3f sw a0,60\(v1\)
+[ 0-9a-f]+: eabf sw a1,60\(v1\)
+[ 0-9a-f]+: eb3f sw a2,60\(v1\)
+[ 0-9a-f]+: ebbf sw a3,60\(v1\)
+[ 0-9a-f]+: e8bf sw s1,60\(v1\)
+[ 0-9a-f]+: e83f sw zero,60\(v1\)
+[ 0-9a-f]+: c800 sw zero,0\(sp\)
+[ 0-9a-f]+: c800 sw zero,0\(sp\)
+[ 0-9a-f]+: c801 sw zero,4\(sp\)
+[ 0-9a-f]+: c802 sw zero,8\(sp\)
+[ 0-9a-f]+: c803 sw zero,12\(sp\)
+[ 0-9a-f]+: c804 sw zero,16\(sp\)
+[ 0-9a-f]+: c805 sw zero,20\(sp\)
+[ 0-9a-f]+: c81e sw zero,120\(sp\)
+[ 0-9a-f]+: c81f sw zero,124\(sp\)
+[ 0-9a-f]+: c85f sw v0,124\(sp\)
+[ 0-9a-f]+: ca3f sw s1,124\(sp\)
+[ 0-9a-f]+: c87f sw v1,124\(sp\)
+[ 0-9a-f]+: c89f sw a0,124\(sp\)
+[ 0-9a-f]+: c8bf sw a1,124\(sp\)
+[ 0-9a-f]+: c8df sw a2,124\(sp\)
+[ 0-9a-f]+: c8ff sw a3,124\(sp\)
+[ 0-9a-f]+: cbff sw ra,124\(sp\)
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f860 7fff sw v1,32767\(zero\)
+[ 0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f860 8001 sw v1,-32767\(zero\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f860 ffff sw v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f864 7fff sw v1,32767\(a0\)
+[ 0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f864 8001 sw v1,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f864 ffff sw v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 87ff swl v1,2047\(zero\)
+[ 0-9a-f]+: 6060 8800 swl v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6060 8fff swl v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 8678 swl v1,1656\(at\)
+[ 0-9a-f]+: 6064 8000 swl v1,0\(a0\)
+[ 0-9a-f]+: 6064 8000 swl v1,0\(a0\)
+[ 0-9a-f]+: 6064 87ff swl v1,2047\(a0\)
+[ 0-9a-f]+: 6064 8800 swl v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6064 8fff swl v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8678 swl v1,1656\(at\)
+[ 0-9a-f]+: 6060 9004 swr v1,4\(zero\)
+[ 0-9a-f]+: 6060 9004 swr v1,4\(zero\)
+[ 0-9a-f]+: 6060 97ff swr v1,2047\(zero\)
+[ 0-9a-f]+: 6060 9800 swr v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 6060 9fff swr v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 9678 swr v1,1656\(at\)
+[ 0-9a-f]+: 6064 9000 swr v1,0\(a0\)
+[ 0-9a-f]+: 6064 9000 swr v1,0\(a0\)
+[ 0-9a-f]+: 6064 97ff swr v1,2047\(a0\)
+[ 0-9a-f]+: 6064 9800 swr v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 6064 9fff swr v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9678 swr v1,1656\(at\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 87ff swl v1,2047\(zero\)
+[ 0-9a-f]+: 6060 8800 swl v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6060 8fff swl v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 8678 swl v1,1656\(at\)
+[ 0-9a-f]+: 6064 8000 swl v1,0\(a0\)
+[ 0-9a-f]+: 6064 8000 swl v1,0\(a0\)
+[ 0-9a-f]+: 6064 87ff swl v1,2047\(a0\)
+[ 0-9a-f]+: 6064 8800 swl v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8fff swl v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8001 swl v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6064 8fff swl v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8678 swl v1,1656\(at\)
+[ 0-9a-f]+: 6060 9004 swr v1,4\(zero\)
+[ 0-9a-f]+: 6060 9004 swr v1,4\(zero\)
+[ 0-9a-f]+: 6060 97ff swr v1,2047\(zero\)
+[ 0-9a-f]+: 6060 9800 swr v1,-2048\(zero\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 6060 9fff swr v1,-1\(zero\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 6061 9678 swr v1,1656\(at\)
+[ 0-9a-f]+: 6064 9000 swr v1,0\(a0\)
+[ 0-9a-f]+: 6064 9000 swr v1,0\(a0\)
+[ 0-9a-f]+: 6064 97ff swr v1,2047\(a0\)
+[ 0-9a-f]+: 6064 9800 swr v1,-2048\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9fff swr v1,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9001 swr v1,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9000 swr v1,0\(at\)
+[ 0-9a-f]+: 6064 9fff swr v1,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 9678 swr v1,1656\(at\)
+[ 0-9a-f]+: 454c swm s0,ra,48\(sp\)
+[ 0-9a-f]+: 455c swm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 455c swm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 456c swm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 456c swm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 457c swm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 457c swm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 4540 swm s0,ra,0\(sp\)
+[ 0-9a-f]+: 4540 swm s0,ra,0\(sp\)
+[ 0-9a-f]+: 4541 swm s0,ra,4\(sp\)
+[ 0-9a-f]+: 4542 swm s0,ra,8\(sp\)
+[ 0-9a-f]+: 4543 swm s0,ra,12\(sp\)
+[ 0-9a-f]+: 4544 swm s0,ra,16\(sp\)
+[ 0-9a-f]+: 4545 swm s0,ra,20\(sp\)
+[ 0-9a-f]+: 4546 swm s0,ra,24\(sp\)
+[ 0-9a-f]+: 4547 swm s0,ra,28\(sp\)
+[ 0-9a-f]+: 4548 swm s0,ra,32\(sp\)
+[ 0-9a-f]+: 4549 swm s0,ra,36\(sp\)
+[ 0-9a-f]+: 454a swm s0,ra,40\(sp\)
+[ 0-9a-f]+: 454b swm s0,ra,44\(sp\)
+[ 0-9a-f]+: 454c swm s0,ra,48\(sp\)
+[ 0-9a-f]+: 454d swm s0,ra,52\(sp\)
+[ 0-9a-f]+: 454e swm s0,ra,56\(sp\)
+[ 0-9a-f]+: 454f swm s0,ra,60\(sp\)
+[ 0-9a-f]+: 2020 d000 swm s0,0\(zero\)
+[ 0-9a-f]+: 2020 d004 swm s0,4\(zero\)
+[ 0-9a-f]+: 2020 d7ff swm s0,2047\(zero\)
+[ 0-9a-f]+: 2020 d800 swm s0,-2048\(zero\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 2021 d800 swm s0,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 2021 d7ff swm s0,2047\(at\)
+[ 0-9a-f]+: 2025 d000 swm s0,0\(a1\)
+[ 0-9a-f]+: 2025 d7ff swm s0,2047\(a1\)
+[ 0-9a-f]+: 2025 d800 swm s0,-2048\(a1\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 00a1 0950 addu at,at,a1
+[ 0-9a-f]+: 2021 d800 swm s0,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 00a1 0950 addu at,at,a1
+[ 0-9a-f]+: 2021 d7ff swm s0,2047\(at\)
+[ 0-9a-f]+: 2045 d7ff swm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 d7ff swm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 d7ff swm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 d7ff swm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 d7ff swm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 d7ff swm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 d7ff swm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 d7ff swm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 d7ff swm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 d000 swm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 d000 swm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 d000 swm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 d000 swm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 d000 swm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 d000 swm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 d000 swm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 d000 swm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 d000 swm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 dfff swm s0,-1\(at\)
+[ 0-9a-f]+: 203d d000 swm s0,0\(sp\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 dfff swm s0,-1\(at\)
+[ 0-9a-f]+: 2040 9000 swp v0,0\(zero\)
+[ 0-9a-f]+: 2040 9004 swp v0,4\(zero\)
+[ 0-9a-f]+: 2040 97ff swp v0,2047\(zero\)
+[ 0-9a-f]+: 2040 9800 swp v0,-2048\(zero\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 2041 9800 swp v0,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 2041 97ff swp v0,2047\(at\)
+[ 0-9a-f]+: 205d 9000 swp v0,0\(sp\)
+[ 0-9a-f]+: 205d 9000 swp v0,0\(sp\)
+[ 0-9a-f]+: 2043 97ff swp v0,2047\(v1\)
+[ 0-9a-f]+: 2043 9800 swp v0,-2048\(v1\)
+[ 0-9a-f]+: 3020 1000 li at,4096
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 9800 swp v0,-2048\(at\)
+[ 0-9a-f]+: 3020 f000 li at,-4096
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 97ff swp v0,2047\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 9fff swp v0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 2043 9000 swp v0,0\(v1\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 9fff swp v0,-1\(at\)
+[ 0-9a-f]+: 0000 6b7c sync
+[ 0-9a-f]+: 0000 6b7c sync
+[ 0-9a-f]+: 0001 6b7c sync 0x1
+[ 0-9a-f]+: 0002 6b7c sync 0x2
+[ 0-9a-f]+: 0003 6b7c sync 0x3
+[ 0-9a-f]+: 0004 6b7c sync_wmb
+[ 0-9a-f]+: 001e 6b7c sync 0x1e
+[ 0-9a-f]+: 001f 6b7c sync 0x1f
+[ 0-9a-f]+: 4200 0000 synci 0\(zero\)
+[ 0-9a-f]+: 4200 0000 synci 0\(zero\)
+[ 0-9a-f]+: 4200 0000 synci 0\(zero\)
+[ 0-9a-f]+: 4200 07ff synci 2047\(zero\)
+[ 0-9a-f]+: 4200 f800 synci -2048\(zero\)
+[ 0-9a-f]+: 4200 0800 synci 2048\(zero\)
+[ 0-9a-f]+: 4200 f7ff synci -2049\(zero\)
+[ 0-9a-f]+: 4200 7fff synci 32767\(zero\)
+[ 0-9a-f]+: 4200 8000 synci -32768\(zero\)
+[ 0-9a-f]+: 4202 0000 synci 0\(v0\)
+[ 0-9a-f]+: 4203 0000 synci 0\(v1\)
+[ 0-9a-f]+: 4203 07ff synci 2047\(v1\)
+[ 0-9a-f]+: 4203 f800 synci -2048\(v1\)
+[ 0-9a-f]+: 4203 0800 synci 2048\(v1\)
+[ 0-9a-f]+: 4203 f7ff synci -2049\(v1\)
+[ 0-9a-f]+: 4203 7fff synci 32767\(v1\)
+[ 0-9a-f]+: 4203 8000 synci -32768\(v1\)
+[ 0-9a-f]+: 0000 8b7c syscall
+[ 0-9a-f]+: 0000 8b7c syscall
+[ 0-9a-f]+: 0001 8b7c syscall 0x1
+[ 0-9a-f]+: 0002 8b7c syscall 0x2
+[ 0-9a-f]+: 00ff 8b7c syscall 0xff
+[ 0-9a-f]+: 41c2 0000 teqi v0,0
+[ 0-9a-f]+: 41c2 8000 teqi v0,-32768
+[ 0-9a-f]+: 41c2 7fff teqi v0,32767
+[ 0-9a-f]+: 41c2 ffff teqi v0,-1
+[ 0-9a-f]+: 0062 003c teq v0,v1
+[ 0-9a-f]+: 0043 003c teq v1,v0
+[ 0-9a-f]+: 0062 003c teq v0,v1
+[ 0-9a-f]+: 0062 103c teq v0,v1,0x1
+[ 0-9a-f]+: 0062 f03c teq v0,v1,0xf
+[ 0-9a-f]+: 41c2 0000 teqi v0,0
+[ 0-9a-f]+: 41c2 8000 teqi v0,-32768
+[ 0-9a-f]+: 41c2 7fff teqi v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 003c teq v0,at
+[ 0-9a-f]+: 4122 0000 tgei v0,0
+[ 0-9a-f]+: 4122 8000 tgei v0,-32768
+[ 0-9a-f]+: 4122 7fff tgei v0,32767
+[ 0-9a-f]+: 4122 ffff tgei v0,-1
+[ 0-9a-f]+: 0062 023c tge v0,v1
+[ 0-9a-f]+: 0043 023c tge v1,v0
+[ 0-9a-f]+: 0062 023c tge v0,v1
+[ 0-9a-f]+: 0062 123c tge v0,v1,0x1
+[ 0-9a-f]+: 0062 f23c tge v0,v1,0xf
+[ 0-9a-f]+: 4122 0000 tgei v0,0
+[ 0-9a-f]+: 4122 8000 tgei v0,-32768
+[ 0-9a-f]+: 4122 7fff tgei v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 023c tge v0,at
+[ 0-9a-f]+: 4162 0000 tgeiu v0,0
+[ 0-9a-f]+: 4162 8000 tgeiu v0,-32768
+[ 0-9a-f]+: 4162 7fff tgeiu v0,32767
+[ 0-9a-f]+: 4162 ffff tgeiu v0,-1
+[ 0-9a-f]+: 0062 043c tgeu v0,v1
+[ 0-9a-f]+: 0043 043c tgeu v1,v0
+[ 0-9a-f]+: 0062 043c tgeu v0,v1
+[ 0-9a-f]+: 0062 143c tgeu v0,v1,0x1
+[ 0-9a-f]+: 0062 f43c tgeu v0,v1,0xf
+[ 0-9a-f]+: 4162 0000 tgeiu v0,0
+[ 0-9a-f]+: 4162 8000 tgeiu v0,-32768
+[ 0-9a-f]+: 4162 7fff tgeiu v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 043c tgeu v0,at
+[ 0-9a-f]+: 0000 037c tlbp
+[ 0-9a-f]+: 0000 137c tlbr
+[ 0-9a-f]+: 0000 237c tlbwi
+[ 0-9a-f]+: 0000 337c tlbwr
+[ 0-9a-f]+: 4102 0000 tlti v0,0
+[ 0-9a-f]+: 4102 8000 tlti v0,-32768
+[ 0-9a-f]+: 4102 7fff tlti v0,32767
+[ 0-9a-f]+: 4102 ffff tlti v0,-1
+[ 0-9a-f]+: 0062 083c tlt v0,v1
+[ 0-9a-f]+: 0043 083c tlt v1,v0
+[ 0-9a-f]+: 0062 083c tlt v0,v1
+[ 0-9a-f]+: 0062 183c tlt v0,v1,0x1
+[ 0-9a-f]+: 0062 f83c tlt v0,v1,0xf
+[ 0-9a-f]+: 4102 0000 tlti v0,0
+[ 0-9a-f]+: 4102 8000 tlti v0,-32768
+[ 0-9a-f]+: 4102 7fff tlti v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 083c tlt v0,at
+[ 0-9a-f]+: 4142 0000 tltiu v0,0
+[ 0-9a-f]+: 4142 8000 tltiu v0,-32768
+[ 0-9a-f]+: 4142 7fff tltiu v0,32767
+[ 0-9a-f]+: 4142 ffff tltiu v0,-1
+[ 0-9a-f]+: 0062 0a3c tltu v0,v1
+[ 0-9a-f]+: 0043 0a3c tltu v1,v0
+[ 0-9a-f]+: 0062 0a3c tltu v0,v1
+[ 0-9a-f]+: 0062 1a3c tltu v0,v1,0x1
+[ 0-9a-f]+: 0062 fa3c tltu v0,v1,0xf
+[ 0-9a-f]+: 4142 0000 tltiu v0,0
+[ 0-9a-f]+: 4142 8000 tltiu v0,-32768
+[ 0-9a-f]+: 4142 7fff tltiu v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 4182 0000 tnei v0,0
+[ 0-9a-f]+: 4182 8000 tnei v0,-32768
+[ 0-9a-f]+: 4182 7fff tnei v0,32767
+[ 0-9a-f]+: 4182 ffff tnei v0,-1
+[ 0-9a-f]+: 0062 0c3c tne v0,v1
+[ 0-9a-f]+: 0043 0c3c tne v1,v0
+[ 0-9a-f]+: 0062 0c3c tne v0,v1
+[ 0-9a-f]+: 0062 1c3c tne v0,v1,0x1
+[ 0-9a-f]+: 0062 fc3c tne v0,v1,0xf
+[ 0-9a-f]+: 4182 0000 tnei v0,0
+[ 0-9a-f]+: 4182 8000 tnei v0,-32768
+[ 0-9a-f]+: 4182 7fff tnei v0,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 1c20 0004 lb at,4\(zero\)
+[ 0-9a-f]+: 1460 0005 lbu v1,5\(zero\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1c20 0004 lb at,4\(zero\)
+[ 0-9a-f]+: 1460 0005 lbu v1,5\(zero\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1c24 0000 lb at,0\(a0\)
+[ 0-9a-f]+: 1464 0001 lbu v1,1\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1c24 0000 lb at,0\(a0\)
+[ 0-9a-f]+: 1464 0001 lbu v1,1\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1c24 7ffb lb at,32763\(a0\)
+[ 0-9a-f]+: 1464 7ffc lbu v1,32764\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1c24 8000 lb at,-32768\(a0\)
+[ 0-9a-f]+: 1464 8001 lbu v1,-32767\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1c61 0000 lb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1420 0004 lbu at,4\(zero\)
+[ 0-9a-f]+: 1460 0005 lbu v1,5\(zero\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1420 0004 lbu at,4\(zero\)
+[ 0-9a-f]+: 1460 0005 lbu v1,5\(zero\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1424 0000 lbu at,0\(a0\)
+[ 0-9a-f]+: 1464 0001 lbu v1,1\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1424 0000 lbu at,0\(a0\)
+[ 0-9a-f]+: 1464 0001 lbu v1,1\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1424 7ffb lbu at,32763\(a0\)
+[ 0-9a-f]+: 1464 7ffc lbu v1,32764\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 1424 8000 lbu at,-32768\(a0\)
+[ 0-9a-f]+: 1464 8001 lbu v1,-32767\(a0\)
+[ 0-9a-f]+: 0021 4000 sll at,at,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1461 0000 lbu v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 1003 lwr v1,3\(zero\)
+[ 0-9a-f]+: 6060 0000 lwl v1,0\(zero\)
+[ 0-9a-f]+: 6060 1003 lwr v1,3\(zero\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 1007 lwr v1,7\(zero\)
+[ 0-9a-f]+: 6060 0004 lwl v1,4\(zero\)
+[ 0-9a-f]+: 6060 1007 lwr v1,7\(zero\)
+[ 0-9a-f]+: 3020 07ff li at,2047
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 6060 0800 lwl v1,-2048\(zero\)
+[ 0-9a-f]+: 6060 1803 lwr v1,-2045\(zero\)
+[ 0-9a-f]+: 3020 0800 li at,2048
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 f7ff li at,-2049
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 7ffb li at,32763
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 6064 0000 lwl v1,0\(a0\)
+[ 0-9a-f]+: 6064 1003 lwr v1,3\(a0\)
+[ 0-9a-f]+: 6064 0004 lwl v1,4\(a0\)
+[ 0-9a-f]+: 6064 1007 lwr v1,7\(a0\)
+[ 0-9a-f]+: 3024 07ff addiu at,a0,2047
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 6064 0800 lwl v1,-2048\(a0\)
+[ 0-9a-f]+: 6064 1803 lwr v1,-2045\(a0\)
+[ 0-9a-f]+: 3024 0800 addiu at,a0,2048
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3024 f7ff addiu at,a0,-2049
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3024 7ffb addiu at,a0,32763
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 0000 lwl v1,0\(at\)
+[ 0-9a-f]+: 6061 1003 lwr v1,3\(at\)
+[ 0-9a-f]+: 1860 0005 sb v1,5\(zero\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1820 0004 sb at,4\(zero\)
+[ 0-9a-f]+: 1860 0005 sb v1,5\(zero\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1820 0004 sb at,4\(zero\)
+[ 0-9a-f]+: 1864 0001 sb v1,1\(a0\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1824 0000 sb at,0\(a0\)
+[ 0-9a-f]+: 1864 0001 sb v1,1\(a0\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1824 0000 sb at,0\(a0\)
+[ 0-9a-f]+: 1864 7ffc sb v1,32764\(a0\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1824 7ffb sb at,32763\(a0\)
+[ 0-9a-f]+: 1864 8001 sb v1,-32767\(a0\)
+[ 0-9a-f]+: 0023 4040 srl at,v1,0x8
+[ 0-9a-f]+: 1824 8000 sb at,-32768\(a0\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 0063 4040 srl v1,v1,0x8
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1421 0001 lbu at,1\(at\)
+[ 0-9a-f]+: 0063 4000 sll v1,v1,0x8
+[ 0-9a-f]+: 0023 1a90 or v1,v1,at
+[ 0-9a-f]+: 6060 8000 swl v1,0\(zero\)
+[ 0-9a-f]+: 6060 9003 swr v1,3\(zero\)
+[ 0-9a-f]+: 6060 8000 swl v1,0\(zero\)
+[ 0-9a-f]+: 6060 9003 swr v1,3\(zero\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 9007 swr v1,7\(zero\)
+[ 0-9a-f]+: 6060 8004 swl v1,4\(zero\)
+[ 0-9a-f]+: 6060 9007 swr v1,7\(zero\)
+[ 0-9a-f]+: 3020 07ff li at,2047
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 6060 8800 swl v1,-2048\(zero\)
+[ 0-9a-f]+: 6060 9803 swr v1,-2045\(zero\)
+[ 0-9a-f]+: 3020 0800 li at,2048
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 f7ff li at,-2049
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 7ffb li at,32763
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 6064 8000 swl v1,0\(a0\)
+[ 0-9a-f]+: 6064 9003 swr v1,3\(a0\)
+[ 0-9a-f]+: 6064 8004 swl v1,4\(a0\)
+[ 0-9a-f]+: 6064 9007 swr v1,7\(a0\)
+[ 0-9a-f]+: 3024 07ff addiu at,a0,2047
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 6064 8800 swl v1,-2048\(a0\)
+[ 0-9a-f]+: 6064 9803 swr v1,-2045\(a0\)
+[ 0-9a-f]+: 3024 0800 addiu at,a0,2048
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3024 f7ff addiu at,a0,-2049
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3024 7ffb addiu at,a0,32763
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 8000 swl v1,0\(at\)
+[ 0-9a-f]+: 6061 9003 swr v1,3\(at\)
+[ 0-9a-f]+: 0000 937c wait
+[ 0-9a-f]+: 0000 937c wait
+[ 0-9a-f]+: 0001 937c wait 0x1
+[ 0-9a-f]+: 00ff 937c wait 0xff
+[ 0-9a-f]+: 0043 f17c wrpgpr v0,v1
+[ 0-9a-f]+: 0044 f17c wrpgpr v0,a0
+[ 0-9a-f]+: 0042 f17c wrpgpr v0,v0
+[ 0-9a-f]+: 0042 f17c wrpgpr v0,v0
+[ 0-9a-f]+: 0043 7b3c wsbh v0,v1
+[ 0-9a-f]+: 0044 7b3c wsbh v0,a0
+[ 0-9a-f]+: 0042 7b3c wsbh v0,v0
+[ 0-9a-f]+: 0042 7b3c wsbh v0,v0
+[ 0-9a-f]+: 4452 xor v0,v0,v0
+[ 0-9a-f]+: 4453 xor v0,v0,v1
+[ 0-9a-f]+: 4454 xor v0,v0,a0
+[ 0-9a-f]+: 4455 xor v0,v0,a1
+[ 0-9a-f]+: 4456 xor v0,v0,a2
+[ 0-9a-f]+: 4457 xor v0,v0,a3
+[ 0-9a-f]+: 4450 xor v0,v0,s0
+[ 0-9a-f]+: 4451 xor v0,v0,s1
+[ 0-9a-f]+: 4459 xor v1,v1,s1
+[ 0-9a-f]+: 4461 xor a0,a0,s1
+[ 0-9a-f]+: 4469 xor a1,a1,s1
+[ 0-9a-f]+: 4471 xor a2,a2,s1
+[ 0-9a-f]+: 4479 xor a3,a3,s1
+[ 0-9a-f]+: 4441 xor s0,s0,s1
+[ 0-9a-f]+: 4449 xor s1,s1,s1
+[ 0-9a-f]+: 4453 xor v0,v0,v1
+[ 0-9a-f]+: 4453 xor v0,v0,v1
+[ 0-9a-f]+: 4453 xor v0,v0,v1
+[ 0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ 0-9a-f]+: 03fe eb10 xor sp,s8,ra
+[ 0-9a-f]+: 0082 1310 xor v0,v0,a0
+[ 0-9a-f]+: 0082 1310 xor v0,v0,a0
+[ 0-9a-f]+: 7043 8000 xori v0,v1,0x8000
+[ 0-9a-f]+: 7043 ffff xori v0,v1,0xffff
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 7064 0000 xori v1,a0,0x0
+[ 0-9a-f]+: 7064 7fff xori v1,a0,0x7fff
+[ 0-9a-f]+: 7064 ffff xori v1,a0,0xffff
+[ 0-9a-f]+: 7063 ffff xori v1,v1,0xffff
+[ 0-9a-f]+: 7063 ffff xori v1,v1,0xffff
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9549 fffe beq t1,t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 9429 fffe beq t1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 404a fffe bgez t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 404a fffe bgez t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 408a fffe blez t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 016a 0b50 slt at,t2,t3
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 404a fffe bgez t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40ca fffe bgtz t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 902a 0002 slti at,t2,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9440 fffe beq zero,v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0062 0b90 sltu at,v0,v1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b402 fffe bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b022 0002 sltiu at,v0,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4062 fffe bgezal v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: 40c2 fffe bgtz v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4002 fffe bltz v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 012a 0b50 slt at,t2,t1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0029 0b50 slt at,t1,at
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 012a 0b90 sltu at,t2,t1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 404a fffe bgez t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 012a 0b50 slt at,t2,t1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4009 fffe bltz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 012a 0b90 sltu at,t2,t1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4009 fffe bltz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 40ca fffe bgtz t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0149 0b50 slt at,t1,t2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4009 fffe bltz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b540 fffe bne zero,t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0149 0b90 sltu at,t1,t2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4009 fffe bltz t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4029 fffe bltzal t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b549 fffe bne t1,t2,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: b429 fffe bne t1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b549 fffe bne t1,t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: b429 fffe bne t1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 400a fffe bltz t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 400a fffe bltz t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40ca fffe bgtz t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 016a 0b50 slt at,t2,t3
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 400a fffe bltz t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 408a fffe blez t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 902a 0002 slti at,t2,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b440 fffe bne zero,v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0062 0b90 sltu at,v0,v1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9402 fffe beqz v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b022 0002 sltiu at,v0,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4002 fffe bltz v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4002 fffe bltz v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4082 fffe blez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 012a 0b50 slt at,t2,t1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4009 fffe bltz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 41a1 8000 lui at,0x8000
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0029 0b50 slt at,t1,at
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 012a 0b90 sltu at,t2,t1
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4089 fffe blez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 400a fffe bltz t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 012a 0b50 slt at,t2,t1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 012a 0b90 sltu at,t2,t1
+[ 0-9a-f]+: b401 fffe bnez at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 408a fffe blez t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0149 0b50 slt at,t1,t2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 40c9 fffe bgtz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9029 0002 slti at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9540 fffe beq zero,t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 0149 0b90 sltu at,t1,t2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b409 fffe bnez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: b029 0002 sltiu at,t1,2
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4049 fffe bgez t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9549 fffe beq t1,t2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 9409 fffe beqz t1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 9429 fffe beq t1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 6d01 addiu v0,sp,0
+[ 0-9a-f]+: 6d03 addiu v0,sp,4
+[ 0-9a-f]+: 6d05 addiu v0,sp,8
+[ 0-9a-f]+: 6d07 addiu v0,sp,12
+[ 0-9a-f]+: 6d09 addiu v0,sp,16
+[ 0-9a-f]+: 6d7f addiu v0,sp,252
+[ 0-9a-f]+: 6dff addiu v1,sp,252
+[ 0-9a-f]+: 6e7f addiu a0,sp,252
+[ 0-9a-f]+: 6eff addiu a1,sp,252
+[ 0-9a-f]+: 6f7f addiu a2,sp,252
+[ 0-9a-f]+: 6fff addiu a3,sp,252
+[ 0-9a-f]+: 6c7f addiu s0,sp,252
+[ 0-9a-f]+: 6cff addiu s1,sp,252
+[ 0-9a-f]+: 6d2e addiu v0,v0,-1
+[ 0-9a-f]+: 6d3e addiu v0,v1,-1
+[ 0-9a-f]+: 6d4e addiu v0,a0,-1
+[ 0-9a-f]+: 6d5e addiu v0,a1,-1
+[ 0-9a-f]+: 6d6e addiu v0,a2,-1
+[ 0-9a-f]+: 6d7e addiu v0,a3,-1
+[ 0-9a-f]+: 6d0e addiu v0,s0,-1
+[ 0-9a-f]+: 6d1e addiu v0,s1,-1
+[ 0-9a-f]+: 6d9e addiu v1,s1,-1
+[ 0-9a-f]+: 6e1e addiu a0,s1,-1
+[ 0-9a-f]+: 6e9e addiu a1,s1,-1
+[ 0-9a-f]+: 6f1e addiu a2,s1,-1
+[ 0-9a-f]+: 6f9e addiu a3,s1,-1
+[ 0-9a-f]+: 6c1e addiu s0,s1,-1
+[ 0-9a-f]+: 6c9e addiu s1,s1,-1
+[ 0-9a-f]+: 6c90 addiu s1,s1,1
+[ 0-9a-f]+: 6c92 addiu s1,s1,4
+[ 0-9a-f]+: 6c94 addiu s1,s1,8
+[ 0-9a-f]+: 6c96 addiu s1,s1,12
+[ 0-9a-f]+: 6c98 addiu s1,s1,16
+[ 0-9a-f]+: 6c9a addiu s1,s1,20
+[ 0-9a-f]+: 6c9c addiu s1,s1,24
+[ 0-9a-f]+: 4c05 addiu sp,sp,8
+[ 0-9a-f]+: 4c07 addiu sp,sp,12
+[ 0-9a-f]+: 4dfd addiu sp,sp,1016
+[ 0-9a-f]+: 4dff addiu sp,sp,1020
+[ 0-9a-f]+: 4c01 addiu sp,sp,1024
+[ 0-9a-f]+: 4c03 addiu sp,sp,1028
+[ 0-9a-f]+: 4ffb addiu sp,sp,-12
+[ 0-9a-f]+: 4ff9 addiu sp,sp,-16
+[ 0-9a-f]+: 4e03 addiu sp,sp,-1020
+[ 0-9a-f]+: 4e01 addiu sp,sp,-1024
+[ 0-9a-f]+: 4fff addiu sp,sp,-1028
+[ 0-9a-f]+: 4ffd addiu sp,sp,-1032
+[ 0-9a-f]+: 4c00 addiu zero,zero,0
+[ 0-9a-f]+: 4c40 addiu v0,v0,0
+[ 0-9a-f]+: 4c60 addiu v1,v1,0
+[ 0-9a-f]+: 4fc0 addiu s8,s8,0
+[ 0-9a-f]+: 4fe0 addiu ra,ra,0
+[ 0-9a-f]+: 4fe2 addiu ra,ra,1
+[ 0-9a-f]+: 4fe4 addiu ra,ra,2
+[ 0-9a-f]+: 4fe6 addiu ra,ra,3
+[ 0-9a-f]+: 4fee addiu ra,ra,7
+[ 0-9a-f]+: 4ff4 addiu ra,ra,-6
+[ 0-9a-f]+: 4ff2 addiu ra,ra,-7
+[ 0-9a-f]+: 4ff0 addiu ra,ra,-8
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f880 0008 sw a0,8\(zero\)
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f880 0008 sw a0,8\(zero\)
+[ 0-9a-f]+: f860 7fff sw v1,32767\(zero\)
+[ 0-9a-f]+: f880 8003 sw a0,-32765\(zero\)
+[ 0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ 0-9a-f]+: f880 8004 sw a0,-32764\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: f861 8000 sw v1,-32768\(at\)
+[ 0-9a-f]+: f881 8004 sw a0,-32764\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f881 0005 sw a0,5\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: f861 8001 sw v1,-32767\(at\)
+[ 0-9a-f]+: f881 8005 sw a0,-32763\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: f881 567c sw a0,22140\(at\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f884 0004 sw a0,4\(a0\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f884 0004 sw a0,4\(a0\)
+[ 0-9a-f]+: f864 7fff sw v1,32767\(a0\)
+[ 0-9a-f]+: f884 8003 sw a0,-32765\(a0\)
+[ 0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ 0-9a-f]+: f884 8004 sw a0,-32764\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 8000 sw v1,-32768\(at\)
+[ 0-9a-f]+: f881 8004 sw a0,-32764\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f881 0005 sw a0,5\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 8001 sw v1,-32767\(at\)
+[ 0-9a-f]+: f881 8005 sw a0,-32763\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: f881 567c sw a0,22140\(at\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc80 0008 lw a0,8\(zero\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc80 0008 lw a0,8\(zero\)
+[ 0-9a-f]+: fc60 7fff lw v1,32767\(zero\)
+[ 0-9a-f]+: fc80 8003 lw a0,-32765\(zero\)
+[ 0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ 0-9a-f]+: fc80 8004 lw a0,-32764\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ 0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: fc61 8000 lw v1,-32768\(at\)
+[ 0-9a-f]+: fc81 8004 lw a0,-32764\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: fc61 0001 lw v1,1\(at\)
+[ 0-9a-f]+: fc81 0005 lw a0,5\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: fc61 8001 lw v1,-32767\(at\)
+[ 0-9a-f]+: fc81 8005 lw a0,-32763\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ 0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: fc61 5678 lw v1,22136\(at\)
+[ 0-9a-f]+: fc81 567c lw a0,22140\(at\)
+[ 0-9a-f]+: fc64 0000 lw v1,0\(a0\)
+[ 0-9a-f]+: fc84 0004 lw a0,4\(a0\)
+[ 0-9a-f]+: fc64 0000 lw v1,0\(a0\)
+[ 0-9a-f]+: fc84 0004 lw a0,4\(a0\)
+[ 0-9a-f]+: fc64 7fff lw v1,32767\(a0\)
+[ 0-9a-f]+: fc84 8003 lw a0,-32765\(a0\)
+[ 0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ 0-9a-f]+: fc84 8004 lw a0,-32764\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ 0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 8000 lw v1,-32768\(at\)
+[ 0-9a-f]+: fc81 8004 lw a0,-32764\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 0001 lw v1,1\(at\)
+[ 0-9a-f]+: fc81 0005 lw a0,5\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 8001 lw v1,-32767\(at\)
+[ 0-9a-f]+: fc81 8005 lw a0,-32763\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: 41a1 0000 lui at,0x0
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ 0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 5678 lw v1,22136\(at\)
+[ 0-9a-f]+: fc81 567c lw a0,22140\(at\)
+[ 0-9a-f]+: 4700 jraddiusp 0
+[ 0-9a-f]+: 4701 jraddiusp 4
+[ 0-9a-f]+: 4702 jraddiusp 8
+[ 0-9a-f]+: 4703 jraddiusp 12
+[ 0-9a-f]+: 4704 jraddiusp 16
+[ 0-9a-f]+: 4705 jraddiusp 20
+[ 0-9a-f]+: 4706 jraddiusp 24
+[ 0-9a-f]+: 4707 jraddiusp 28
+[ 0-9a-f]+: 4708 jraddiusp 32
+[ 0-9a-f]+: 4709 jraddiusp 36
+[ 0-9a-f]+: 470a jraddiusp 40
+[ 0-9a-f]+: 471e jraddiusp 120
+[ 0-9a-f]+: 471f jraddiusp 124
+[ 0-9a-f]+: 2060 2000 ldc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 2000 ldc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 2004 ldc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 2004 ldc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 2000 ldc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 2000 ldc2 \$3,0\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2fff ldc2 \$3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2fff ldc2 \$3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2001 ldc2 \$3,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2001 ldc2 \$3,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 2fff ldc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2678 ldc2 \$3,1656\(at\)
+[ 0-9a-f]+: 2060 0000 lwc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 0000 lwc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 0004 lwc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 0004 lwc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 0000 lwc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 0000 lwc2 \$3,0\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0fff lwc2 \$3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0fff lwc2 \$3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0001 lwc2 \$3,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0001 lwc2 \$3,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 0fff lwc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0678 lwc2 \$3,1656\(at\)
+[ 0-9a-f]+: 00a0 4d3c mfc2 a1,\$0
+[ 0-9a-f]+: 00a1 4d3c mfc2 a1,\$1
+[ 0-9a-f]+: 00a2 4d3c mfc2 a1,\$2
+[ 0-9a-f]+: 00a3 4d3c mfc2 a1,\$3
+[ 0-9a-f]+: 00a4 4d3c mfc2 a1,\$4
+[ 0-9a-f]+: 00a5 4d3c mfc2 a1,\$5
+[ 0-9a-f]+: 00a6 4d3c mfc2 a1,\$6
+[ 0-9a-f]+: 00a7 4d3c mfc2 a1,\$7
+[ 0-9a-f]+: 00a8 4d3c mfc2 a1,\$8
+[ 0-9a-f]+: 00a9 4d3c mfc2 a1,\$9
+[ 0-9a-f]+: 00aa 4d3c mfc2 a1,\$10
+[ 0-9a-f]+: 00ab 4d3c mfc2 a1,\$11
+[ 0-9a-f]+: 00ac 4d3c mfc2 a1,\$12
+[ 0-9a-f]+: 00ad 4d3c mfc2 a1,\$13
+[ 0-9a-f]+: 00ae 4d3c mfc2 a1,\$14
+[ 0-9a-f]+: 00af 4d3c mfc2 a1,\$15
+[ 0-9a-f]+: 00b0 4d3c mfc2 a1,\$16
+[ 0-9a-f]+: 00b1 4d3c mfc2 a1,\$17
+[ 0-9a-f]+: 00b2 4d3c mfc2 a1,\$18
+[ 0-9a-f]+: 00b3 4d3c mfc2 a1,\$19
+[ 0-9a-f]+: 00b4 4d3c mfc2 a1,\$20
+[ 0-9a-f]+: 00b5 4d3c mfc2 a1,\$21
+[ 0-9a-f]+: 00b6 4d3c mfc2 a1,\$22
+[ 0-9a-f]+: 00b7 4d3c mfc2 a1,\$23
+[ 0-9a-f]+: 00b8 4d3c mfc2 a1,\$24
+[ 0-9a-f]+: 00b9 4d3c mfc2 a1,\$25
+[ 0-9a-f]+: 00ba 4d3c mfc2 a1,\$26
+[ 0-9a-f]+: 00bb 4d3c mfc2 a1,\$27
+[ 0-9a-f]+: 00bc 4d3c mfc2 a1,\$28
+[ 0-9a-f]+: 00bd 4d3c mfc2 a1,\$29
+[ 0-9a-f]+: 00be 4d3c mfc2 a1,\$30
+[ 0-9a-f]+: 00bf 4d3c mfc2 a1,\$31
+[ 0-9a-f]+: 00a0 8d3c mfhc2 a1,\$0
+[ 0-9a-f]+: 00a1 8d3c mfhc2 a1,\$1
+[ 0-9a-f]+: 00a2 8d3c mfhc2 a1,\$2
+[ 0-9a-f]+: 00a3 8d3c mfhc2 a1,\$3
+[ 0-9a-f]+: 00a4 8d3c mfhc2 a1,\$4
+[ 0-9a-f]+: 00a5 8d3c mfhc2 a1,\$5
+[ 0-9a-f]+: 00a6 8d3c mfhc2 a1,\$6
+[ 0-9a-f]+: 00a7 8d3c mfhc2 a1,\$7
+[ 0-9a-f]+: 00a8 8d3c mfhc2 a1,\$8
+[ 0-9a-f]+: 00a9 8d3c mfhc2 a1,\$9
+[ 0-9a-f]+: 00aa 8d3c mfhc2 a1,\$10
+[ 0-9a-f]+: 00ab 8d3c mfhc2 a1,\$11
+[ 0-9a-f]+: 00ac 8d3c mfhc2 a1,\$12
+[ 0-9a-f]+: 00ad 8d3c mfhc2 a1,\$13
+[ 0-9a-f]+: 00ae 8d3c mfhc2 a1,\$14
+[ 0-9a-f]+: 00af 8d3c mfhc2 a1,\$15
+[ 0-9a-f]+: 00b0 8d3c mfhc2 a1,\$16
+[ 0-9a-f]+: 00b1 8d3c mfhc2 a1,\$17
+[ 0-9a-f]+: 00b2 8d3c mfhc2 a1,\$18
+[ 0-9a-f]+: 00b3 8d3c mfhc2 a1,\$19
+[ 0-9a-f]+: 00b4 8d3c mfhc2 a1,\$20
+[ 0-9a-f]+: 00b5 8d3c mfhc2 a1,\$21
+[ 0-9a-f]+: 00b6 8d3c mfhc2 a1,\$22
+[ 0-9a-f]+: 00b7 8d3c mfhc2 a1,\$23
+[ 0-9a-f]+: 00b8 8d3c mfhc2 a1,\$24
+[ 0-9a-f]+: 00b9 8d3c mfhc2 a1,\$25
+[ 0-9a-f]+: 00ba 8d3c mfhc2 a1,\$26
+[ 0-9a-f]+: 00bb 8d3c mfhc2 a1,\$27
+[ 0-9a-f]+: 00bc 8d3c mfhc2 a1,\$28
+[ 0-9a-f]+: 00bd 8d3c mfhc2 a1,\$29
+[ 0-9a-f]+: 00be 8d3c mfhc2 a1,\$30
+[ 0-9a-f]+: 00bf 8d3c mfhc2 a1,\$31
+[ 0-9a-f]+: 00a0 5d3c mtc2 a1,\$0
+[ 0-9a-f]+: 00a1 5d3c mtc2 a1,\$1
+[ 0-9a-f]+: 00a2 5d3c mtc2 a1,\$2
+[ 0-9a-f]+: 00a3 5d3c mtc2 a1,\$3
+[ 0-9a-f]+: 00a4 5d3c mtc2 a1,\$4
+[ 0-9a-f]+: 00a5 5d3c mtc2 a1,\$5
+[ 0-9a-f]+: 00a6 5d3c mtc2 a1,\$6
+[ 0-9a-f]+: 00a7 5d3c mtc2 a1,\$7
+[ 0-9a-f]+: 00a8 5d3c mtc2 a1,\$8
+[ 0-9a-f]+: 00a9 5d3c mtc2 a1,\$9
+[ 0-9a-f]+: 00aa 5d3c mtc2 a1,\$10
+[ 0-9a-f]+: 00ab 5d3c mtc2 a1,\$11
+[ 0-9a-f]+: 00ac 5d3c mtc2 a1,\$12
+[ 0-9a-f]+: 00ad 5d3c mtc2 a1,\$13
+[ 0-9a-f]+: 00ae 5d3c mtc2 a1,\$14
+[ 0-9a-f]+: 00af 5d3c mtc2 a1,\$15
+[ 0-9a-f]+: 00b0 5d3c mtc2 a1,\$16
+[ 0-9a-f]+: 00b1 5d3c mtc2 a1,\$17
+[ 0-9a-f]+: 00b2 5d3c mtc2 a1,\$18
+[ 0-9a-f]+: 00b3 5d3c mtc2 a1,\$19
+[ 0-9a-f]+: 00b4 5d3c mtc2 a1,\$20
+[ 0-9a-f]+: 00b5 5d3c mtc2 a1,\$21
+[ 0-9a-f]+: 00b6 5d3c mtc2 a1,\$22
+[ 0-9a-f]+: 00b7 5d3c mtc2 a1,\$23
+[ 0-9a-f]+: 00b8 5d3c mtc2 a1,\$24
+[ 0-9a-f]+: 00b9 5d3c mtc2 a1,\$25
+[ 0-9a-f]+: 00ba 5d3c mtc2 a1,\$26
+[ 0-9a-f]+: 00bb 5d3c mtc2 a1,\$27
+[ 0-9a-f]+: 00bc 5d3c mtc2 a1,\$28
+[ 0-9a-f]+: 00bd 5d3c mtc2 a1,\$29
+[ 0-9a-f]+: 00be 5d3c mtc2 a1,\$30
+[ 0-9a-f]+: 00bf 5d3c mtc2 a1,\$31
+[ 0-9a-f]+: 00a0 9d3c mthc2 a1,\$0
+[ 0-9a-f]+: 00a1 9d3c mthc2 a1,\$1
+[ 0-9a-f]+: 00a2 9d3c mthc2 a1,\$2
+[ 0-9a-f]+: 00a3 9d3c mthc2 a1,\$3
+[ 0-9a-f]+: 00a4 9d3c mthc2 a1,\$4
+[ 0-9a-f]+: 00a5 9d3c mthc2 a1,\$5
+[ 0-9a-f]+: 00a6 9d3c mthc2 a1,\$6
+[ 0-9a-f]+: 00a7 9d3c mthc2 a1,\$7
+[ 0-9a-f]+: 00a8 9d3c mthc2 a1,\$8
+[ 0-9a-f]+: 00a9 9d3c mthc2 a1,\$9
+[ 0-9a-f]+: 00aa 9d3c mthc2 a1,\$10
+[ 0-9a-f]+: 00ab 9d3c mthc2 a1,\$11
+[ 0-9a-f]+: 00ac 9d3c mthc2 a1,\$12
+[ 0-9a-f]+: 00ad 9d3c mthc2 a1,\$13
+[ 0-9a-f]+: 00ae 9d3c mthc2 a1,\$14
+[ 0-9a-f]+: 00af 9d3c mthc2 a1,\$15
+[ 0-9a-f]+: 00b0 9d3c mthc2 a1,\$16
+[ 0-9a-f]+: 00b1 9d3c mthc2 a1,\$17
+[ 0-9a-f]+: 00b2 9d3c mthc2 a1,\$18
+[ 0-9a-f]+: 00b3 9d3c mthc2 a1,\$19
+[ 0-9a-f]+: 00b4 9d3c mthc2 a1,\$20
+[ 0-9a-f]+: 00b5 9d3c mthc2 a1,\$21
+[ 0-9a-f]+: 00b6 9d3c mthc2 a1,\$22
+[ 0-9a-f]+: 00b7 9d3c mthc2 a1,\$23
+[ 0-9a-f]+: 00b8 9d3c mthc2 a1,\$24
+[ 0-9a-f]+: 00b9 9d3c mthc2 a1,\$25
+[ 0-9a-f]+: 00ba 9d3c mthc2 a1,\$26
+[ 0-9a-f]+: 00bb 9d3c mthc2 a1,\$27
+[ 0-9a-f]+: 00bc 9d3c mthc2 a1,\$28
+[ 0-9a-f]+: 00bd 9d3c mthc2 a1,\$29
+[ 0-9a-f]+: 00be 9d3c mthc2 a1,\$30
+[ 0-9a-f]+: 00bf 9d3c mthc2 a1,\$31
+[ 0-9a-f]+: 2060 a000 sdc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 a000 sdc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 a004 sdc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 a004 sdc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 a000 sdc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 a000 sdc2 \$3,0\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 afff sdc2 \$3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 afff sdc2 \$3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a001 sdc2 \$3,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a001 sdc2 \$3,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 afff sdc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a678 sdc2 \$3,1656\(at\)
+[ 0-9a-f]+: 2060 8000 swc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 8000 swc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 8004 swc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 8004 swc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 8000 swc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 8000 swc2 \$3,0\(a0\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8fff swc2 \$3,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8fff swc2 \$3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8001 swc2 \$3,1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8001 swc2 \$3,1\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 8fff swc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8678 swc2 \$3,1656\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2041 1000 lwp v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 3043 0000 addiu v0,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6042 3000 ll v0,0\(v0\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 b000 sc v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 0000 lwl v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 1000 lwr v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 8000 swl v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 9000 swr v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 0000 lwc2 \$16,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 8000 swc2 \$16,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 0000 lwl v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 1000 lwr v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 8000 swl v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 9000 swr v0,0\(at\)
+[ 0-9a-f]+: 03ff db7c sdbbp 0x3ff
+[ 0-9a-f]+: 03ff 937c wait 0x3ff
+[ 0-9a-f]+: 03ff 8b7c syscall 0x3ff
+[ 0-9a-f]+: 03ff fffa cop2 0x7fffff
+
+[0-9a-f]+ <fp_test>:
+[ 0-9a-f]+: 5400 01a0 prefx 0x0,zero\(zero\)
+[ 0-9a-f]+: 5402 01a0 prefx 0x0,zero\(v0\)
+[ 0-9a-f]+: 541f 01a0 prefx 0x0,zero\(ra\)
+[ 0-9a-f]+: 545f 01a0 prefx 0x0,v0\(ra\)
+[ 0-9a-f]+: 57ff 01a0 prefx 0x0,ra\(ra\)
+[ 0-9a-f]+: 57ff 09a0 prefx 0x1,ra\(ra\)
+[ 0-9a-f]+: 57ff 11a0 prefx 0x2,ra\(ra\)
+[ 0-9a-f]+: 57ff f9a0 prefx 0x1f,ra\(ra\)
+[ 0-9a-f]+: 5401 037b abs\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 037b abs\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 037b abs\.s \$f2,\$f2
+[ 0-9a-f]+: 5442 037b abs\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 237b abs\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 237b abs\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 237b abs\.d \$f2,\$f2
+[ 0-9a-f]+: 5442 237b abs\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 437b abs\.ps \$f0,\$f1
+[ 0-9a-f]+: 57df 437b abs\.ps \$f30,\$f31
+[ 0-9a-f]+: 5442 437b abs\.ps \$f2,\$f2
+[ 0-9a-f]+: 5442 437b abs\.ps \$f2,\$f2
+[ 0-9a-f]+: 5441 0030 add\.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e830 add\.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e830 add\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e830 add\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0130 add\.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e930 add\.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e930 add\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e930 add\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0230 add\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe ea30 add\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd ea30 add\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd ea30 add\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0019 alnv\.ps \$f0,\$f1,\$f2,zero
+[ 0-9a-f]+: 5441 0099 alnv\.ps \$f0,\$f1,\$f2,v0
+[ 0-9a-f]+: 5441 07d9 alnv\.ps \$f0,\$f1,\$f2,ra
+[ 0-9a-f]+: 57fe efd9 alnv\.ps \$f29,\$f30,\$f31,ra
+[ 0-9a-f]+: 57fd efd9 alnv\.ps \$f29,\$f29,\$f31,ra
+[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4380 fffe bc1f [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4384 fffe bc1f \$fcc1,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4388 fffe bc1f \$fcc2,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 438c fffe bc1f \$fcc3,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4390 fffe bc1f \$fcc4,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4394 fffe bc1f \$fcc5,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4398 fffe bc1f \$fcc6,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 439c fffe bc1f \$fcc7,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43a0 fffe bc1t [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43a0 fffe bc1t [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43a4 fffe bc1t \$fcc1,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43a8 fffe bc1t \$fcc2,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43ac fffe bc1t \$fcc3,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43b0 fffe bc1t \$fcc4,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43b4 fffe bc1t \$fcc5,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43b8 fffe bc1t \$fcc6,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 43bc fffe bc1t \$fcc7,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 fp_test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 5420 043c c\.f\.d \$f0,\$f1
+[ 0-9a-f]+: 57fe 043c c\.f\.d \$f30,\$f31
+[ 0-9a-f]+: 57fe 043c c\.f\.d \$f30,\$f31
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+[ 0-9a-f]+: 54b2 103b cfc1 a1,\$18
+[ 0-9a-f]+: 54b3 103b cfc1 a1,\$19
+[ 0-9a-f]+: 54b4 103b cfc1 a1,\$20
+[ 0-9a-f]+: 54b5 103b cfc1 a1,\$21
+[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
+[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
+[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
+[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
+[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
+[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
+[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
+[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
+[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
+[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
+[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
+[ 0-9a-f]+: 54a8 103b cfc1 a1,\$8
+[ 0-9a-f]+: 54a9 103b cfc1 a1,\$9
+[ 0-9a-f]+: 54aa 103b cfc1 a1,\$10
+[ 0-9a-f]+: 54ab 103b cfc1 a1,\$11
+[ 0-9a-f]+: 54ac 103b cfc1 a1,\$12
+[ 0-9a-f]+: 54ad 103b cfc1 a1,\$13
+[ 0-9a-f]+: 54ae 103b cfc1 a1,\$14
+[ 0-9a-f]+: 54af 103b cfc1 a1,\$15
+[ 0-9a-f]+: 54b0 103b cfc1 a1,\$16
+[ 0-9a-f]+: 54b1 103b cfc1 a1,\$17
+[ 0-9a-f]+: 54b2 103b cfc1 a1,\$18
+[ 0-9a-f]+: 54b3 103b cfc1 a1,\$19
+[ 0-9a-f]+: 54b4 103b cfc1 a1,\$20
+[ 0-9a-f]+: 54b5 103b cfc1 a1,\$21
+[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
+[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
+[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
+[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
+[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
+[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0
+[ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1
+[ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2
+[ 0-9a-f]+: 00a3 cd3c cfc2 a1,\$3
+[ 0-9a-f]+: 00a4 cd3c cfc2 a1,\$4
+[ 0-9a-f]+: 00a5 cd3c cfc2 a1,\$5
+[ 0-9a-f]+: 00a6 cd3c cfc2 a1,\$6
+[ 0-9a-f]+: 00a7 cd3c cfc2 a1,\$7
+[ 0-9a-f]+: 00a8 cd3c cfc2 a1,\$8
+[ 0-9a-f]+: 00a9 cd3c cfc2 a1,\$9
+[ 0-9a-f]+: 00aa cd3c cfc2 a1,\$10
+[ 0-9a-f]+: 00ab cd3c cfc2 a1,\$11
+[ 0-9a-f]+: 00ac cd3c cfc2 a1,\$12
+[ 0-9a-f]+: 00ad cd3c cfc2 a1,\$13
+[ 0-9a-f]+: 00ae cd3c cfc2 a1,\$14
+[ 0-9a-f]+: 00af cd3c cfc2 a1,\$15
+[ 0-9a-f]+: 00b0 cd3c cfc2 a1,\$16
+[ 0-9a-f]+: 00b1 cd3c cfc2 a1,\$17
+[ 0-9a-f]+: 00b2 cd3c cfc2 a1,\$18
+[ 0-9a-f]+: 00b3 cd3c cfc2 a1,\$19
+[ 0-9a-f]+: 00b4 cd3c cfc2 a1,\$20
+[ 0-9a-f]+: 00b5 cd3c cfc2 a1,\$21
+[ 0-9a-f]+: 00b6 cd3c cfc2 a1,\$22
+[ 0-9a-f]+: 00b7 cd3c cfc2 a1,\$23
+[ 0-9a-f]+: 00b8 cd3c cfc2 a1,\$24
+[ 0-9a-f]+: 00b9 cd3c cfc2 a1,\$25
+[ 0-9a-f]+: 00ba cd3c cfc2 a1,\$26
+[ 0-9a-f]+: 00bb cd3c cfc2 a1,\$27
+[ 0-9a-f]+: 00bc cd3c cfc2 a1,\$28
+[ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29
+[ 0-9a-f]+: 00be cd3c cfc2 a1,\$30
+[ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
+[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
+[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
+[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
+[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
+[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
+[ 0-9a-f]+: 54a8 183b ctc1 a1,\$8
+[ 0-9a-f]+: 54a9 183b ctc1 a1,\$9
+[ 0-9a-f]+: 54aa 183b ctc1 a1,\$10
+[ 0-9a-f]+: 54ab 183b ctc1 a1,\$11
+[ 0-9a-f]+: 54ac 183b ctc1 a1,\$12
+[ 0-9a-f]+: 54ad 183b ctc1 a1,\$13
+[ 0-9a-f]+: 54ae 183b ctc1 a1,\$14
+[ 0-9a-f]+: 54af 183b ctc1 a1,\$15
+[ 0-9a-f]+: 54b0 183b ctc1 a1,\$16
+[ 0-9a-f]+: 54b1 183b ctc1 a1,\$17
+[ 0-9a-f]+: 54b2 183b ctc1 a1,\$18
+[ 0-9a-f]+: 54b3 183b ctc1 a1,\$19
+[ 0-9a-f]+: 54b4 183b ctc1 a1,\$20
+[ 0-9a-f]+: 54b5 183b ctc1 a1,\$21
+[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
+[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
+[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
+[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
+[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
+[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
+[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
+[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
+[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
+[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
+[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
+[ 0-9a-f]+: 54a8 183b ctc1 a1,\$8
+[ 0-9a-f]+: 54a9 183b ctc1 a1,\$9
+[ 0-9a-f]+: 54aa 183b ctc1 a1,\$10
+[ 0-9a-f]+: 54ab 183b ctc1 a1,\$11
+[ 0-9a-f]+: 54ac 183b ctc1 a1,\$12
+[ 0-9a-f]+: 54ad 183b ctc1 a1,\$13
+[ 0-9a-f]+: 54ae 183b ctc1 a1,\$14
+[ 0-9a-f]+: 54af 183b ctc1 a1,\$15
+[ 0-9a-f]+: 54b0 183b ctc1 a1,\$16
+[ 0-9a-f]+: 54b1 183b ctc1 a1,\$17
+[ 0-9a-f]+: 54b2 183b ctc1 a1,\$18
+[ 0-9a-f]+: 54b3 183b ctc1 a1,\$19
+[ 0-9a-f]+: 54b4 183b ctc1 a1,\$20
+[ 0-9a-f]+: 54b5 183b ctc1 a1,\$21
+[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
+[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
+[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
+[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
+[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
+[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0
+[ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1
+[ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2
+[ 0-9a-f]+: 00a3 dd3c ctc2 a1,\$3
+[ 0-9a-f]+: 00a4 dd3c ctc2 a1,\$4
+[ 0-9a-f]+: 00a5 dd3c ctc2 a1,\$5
+[ 0-9a-f]+: 00a6 dd3c ctc2 a1,\$6
+[ 0-9a-f]+: 00a7 dd3c ctc2 a1,\$7
+[ 0-9a-f]+: 00a8 dd3c ctc2 a1,\$8
+[ 0-9a-f]+: 00a9 dd3c ctc2 a1,\$9
+[ 0-9a-f]+: 00aa dd3c ctc2 a1,\$10
+[ 0-9a-f]+: 00ab dd3c ctc2 a1,\$11
+[ 0-9a-f]+: 00ac dd3c ctc2 a1,\$12
+[ 0-9a-f]+: 00ad dd3c ctc2 a1,\$13
+[ 0-9a-f]+: 00ae dd3c ctc2 a1,\$14
+[ 0-9a-f]+: 00af dd3c ctc2 a1,\$15
+[ 0-9a-f]+: 00b0 dd3c ctc2 a1,\$16
+[ 0-9a-f]+: 00b1 dd3c ctc2 a1,\$17
+[ 0-9a-f]+: 00b2 dd3c ctc2 a1,\$18
+[ 0-9a-f]+: 00b3 dd3c ctc2 a1,\$19
+[ 0-9a-f]+: 00b4 dd3c ctc2 a1,\$20
+[ 0-9a-f]+: 00b5 dd3c ctc2 a1,\$21
+[ 0-9a-f]+: 00b6 dd3c ctc2 a1,\$22
+[ 0-9a-f]+: 00b7 dd3c ctc2 a1,\$23
+[ 0-9a-f]+: 00b8 dd3c ctc2 a1,\$24
+[ 0-9a-f]+: 00b9 dd3c ctc2 a1,\$25
+[ 0-9a-f]+: 00ba dd3c ctc2 a1,\$26
+[ 0-9a-f]+: 00bb dd3c ctc2 a1,\$27
+[ 0-9a-f]+: 00bc dd3c ctc2 a1,\$28
+[ 0-9a-f]+: 00bd dd3c ctc2 a1,\$29
+[ 0-9a-f]+: 00be dd3c ctc2 a1,\$30
+[ 0-9a-f]+: 00bf dd3c ctc2 a1,\$31
+[ 0-9a-f]+: 5401 537b cvt\.d\.l \$f0,\$f1
+[ 0-9a-f]+: 57df 537b cvt\.d\.l \$f30,\$f31
+[ 0-9a-f]+: 5442 537b cvt\.d\.l \$f2,\$f2
+[ 0-9a-f]+: 5401 137b cvt\.d\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 137b cvt\.d\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 137b cvt\.d\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 337b cvt\.d\.w \$f0,\$f1
+[ 0-9a-f]+: 57df 337b cvt\.d\.w \$f30,\$f31
+[ 0-9a-f]+: 5442 337b cvt\.d\.w \$f2,\$f2
+[ 0-9a-f]+: 5401 013b cvt\.l\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 013b cvt\.l\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 013b cvt\.l\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 413b cvt\.l\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 413b cvt\.l\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 413b cvt\.l\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 5b7b cvt\.s\.l \$f0,\$f1
+[ 0-9a-f]+: 57df 5b7b cvt\.s\.l \$f30,\$f31
+[ 0-9a-f]+: 5442 5b7b cvt\.s\.l \$f2,\$f2
+[ 0-9a-f]+: 5401 1b7b cvt\.s\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 1b7b cvt\.s\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 1b7b cvt\.s\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 3b7b cvt\.s\.w \$f0,\$f1
+[ 0-9a-f]+: 57df 3b7b cvt\.s\.w \$f30,\$f31
+[ 0-9a-f]+: 5442 3b7b cvt\.s\.w \$f2,\$f2
+[ 0-9a-f]+: 5401 213b cvt\.s\.pl \$f0,\$f1
+[ 0-9a-f]+: 57df 213b cvt\.s\.pl \$f30,\$f31
+[ 0-9a-f]+: 5442 213b cvt\.s\.pl \$f2,\$f2
+[ 0-9a-f]+: 5401 293b cvt\.s\.pu \$f0,\$f1
+[ 0-9a-f]+: 57df 293b cvt\.s\.pu \$f30,\$f31
+[ 0-9a-f]+: 5442 293b cvt\.s\.pu \$f2,\$f2
+[ 0-9a-f]+: 5401 093b cvt\.w\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 093b cvt\.w\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 093b cvt\.w\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 493b cvt\.w\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 493b cvt\.w\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 493b cvt\.w\.d \$f2,\$f2
+[ 0-9a-f]+: 5441 0180 cvt\.ps\.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e980 cvt\.ps\.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57fd e980 cvt\.ps\.s \$f29,\$f29,\$f31
+[ 0-9a-f]+: 57fd e980 cvt\.ps\.s \$f29,\$f29,\$f31
+[ 0-9a-f]+: 5441 01f0 div\.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e9f0 div\.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e9f0 div\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e9f0 div\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 00f0 div\.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e8f0 div\.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e8f0 div\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e8f0 div\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5401 433b floor\.l\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 433b floor\.l\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 433b floor\.l\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 033b floor\.l\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 033b floor\.l\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 033b floor\.l\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 4b3b floor\.w\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 4b3b floor\.w\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 4b3b floor\.w\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 0b3b floor\.w\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 0b3b floor\.w\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 0b3b floor\.w\.s \$f2,\$f2
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 ffff ldc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0001 ldc1 \$f3,1\(at\)
+[ 0-9a-f]+: bc64 8001 ldc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 ffff ldc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 5678 ldc1 \$f3,22136\(at\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 ffff ldc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0001 ldc1 \$f3,1\(at\)
+[ 0-9a-f]+: bc64 8001 ldc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 ffff ldc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 5678 ldc1 \$f3,22136\(at\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 5400 00c8 ldxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 00c8 ldxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 00c8 ldxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 00c8 ldxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 00c8 ldxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 08c8 ldxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 10c8 ldxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f8c8 ldxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 5400 0148 luxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 0148 luxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 0148 luxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 0148 luxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 0148 luxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 0948 luxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 1148 luxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f948 luxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 5400 0048 lwxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 0048 lwxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 0048 lwxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 0048 lwxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 0048 lwxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 0848 lwxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 1048 lwxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f848 lwxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 5462 0049 madd\.d \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e749 madd\.d \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0041 madd\.s \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e741 madd\.s \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0051 madd\.ps \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e751 madd\.ps \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 54a0 203b mfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 203b mfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 203b mfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 203b mfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 203b mfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 203b mfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 203b mfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 203b mfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 203b mfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 203b mfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 203b mfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 203b mfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 203b mfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 203b mfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 203b mfc1 a1,\$f14
+[ 0-9a-f]+: 54af 203b mfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 203b mfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 203b mfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 203b mfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 203b mfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 203b mfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 203b mfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 203b mfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 203b mfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 203b mfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 203b mfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 203b mfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 203b mfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 203b mfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 203b mfc1 a1,\$f29
+[ 0-9a-f]+: 54be 203b mfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 203b mfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 203b mfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 203b mfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 203b mfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 203b mfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 203b mfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 203b mfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 203b mfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 203b mfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 203b mfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 203b mfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 203b mfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 203b mfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 203b mfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 203b mfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 203b mfc1 a1,\$f14
+[ 0-9a-f]+: 54af 203b mfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 203b mfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 203b mfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 203b mfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 203b mfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 203b mfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 203b mfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 203b mfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 203b mfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 203b mfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 203b mfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 203b mfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 203b mfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 203b mfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 203b mfc1 a1,\$f29
+[ 0-9a-f]+: 54be 203b mfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 203b mfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 303b mfhc1 a1,\$f0
+[ 0-9a-f]+: 54a1 303b mfhc1 a1,\$f1
+[ 0-9a-f]+: 54a2 303b mfhc1 a1,\$f2
+[ 0-9a-f]+: 54a3 303b mfhc1 a1,\$f3
+[ 0-9a-f]+: 54a4 303b mfhc1 a1,\$f4
+[ 0-9a-f]+: 54a5 303b mfhc1 a1,\$f5
+[ 0-9a-f]+: 54a6 303b mfhc1 a1,\$f6
+[ 0-9a-f]+: 54a7 303b mfhc1 a1,\$f7
+[ 0-9a-f]+: 54a8 303b mfhc1 a1,\$f8
+[ 0-9a-f]+: 54a9 303b mfhc1 a1,\$f9
+[ 0-9a-f]+: 54aa 303b mfhc1 a1,\$f10
+[ 0-9a-f]+: 54ab 303b mfhc1 a1,\$f11
+[ 0-9a-f]+: 54ac 303b mfhc1 a1,\$f12
+[ 0-9a-f]+: 54ad 303b mfhc1 a1,\$f13
+[ 0-9a-f]+: 54ae 303b mfhc1 a1,\$f14
+[ 0-9a-f]+: 54af 303b mfhc1 a1,\$f15
+[ 0-9a-f]+: 54b0 303b mfhc1 a1,\$f16
+[ 0-9a-f]+: 54b1 303b mfhc1 a1,\$f17
+[ 0-9a-f]+: 54b2 303b mfhc1 a1,\$f18
+[ 0-9a-f]+: 54b3 303b mfhc1 a1,\$f19
+[ 0-9a-f]+: 54b4 303b mfhc1 a1,\$f20
+[ 0-9a-f]+: 54b5 303b mfhc1 a1,\$f21
+[ 0-9a-f]+: 54b6 303b mfhc1 a1,\$f22
+[ 0-9a-f]+: 54b7 303b mfhc1 a1,\$f23
+[ 0-9a-f]+: 54b8 303b mfhc1 a1,\$f24
+[ 0-9a-f]+: 54b9 303b mfhc1 a1,\$f25
+[ 0-9a-f]+: 54ba 303b mfhc1 a1,\$f26
+[ 0-9a-f]+: 54bb 303b mfhc1 a1,\$f27
+[ 0-9a-f]+: 54bc 303b mfhc1 a1,\$f28
+[ 0-9a-f]+: 54bd 303b mfhc1 a1,\$f29
+[ 0-9a-f]+: 54be 303b mfhc1 a1,\$f30
+[ 0-9a-f]+: 54bf 303b mfhc1 a1,\$f31
+[ 0-9a-f]+: 54a0 303b mfhc1 a1,\$f0
+[ 0-9a-f]+: 54a1 303b mfhc1 a1,\$f1
+[ 0-9a-f]+: 54a2 303b mfhc1 a1,\$f2
+[ 0-9a-f]+: 54a3 303b mfhc1 a1,\$f3
+[ 0-9a-f]+: 54a4 303b mfhc1 a1,\$f4
+[ 0-9a-f]+: 54a5 303b mfhc1 a1,\$f5
+[ 0-9a-f]+: 54a6 303b mfhc1 a1,\$f6
+[ 0-9a-f]+: 54a7 303b mfhc1 a1,\$f7
+[ 0-9a-f]+: 54a8 303b mfhc1 a1,\$f8
+[ 0-9a-f]+: 54a9 303b mfhc1 a1,\$f9
+[ 0-9a-f]+: 54aa 303b mfhc1 a1,\$f10
+[ 0-9a-f]+: 54ab 303b mfhc1 a1,\$f11
+[ 0-9a-f]+: 54ac 303b mfhc1 a1,\$f12
+[ 0-9a-f]+: 54ad 303b mfhc1 a1,\$f13
+[ 0-9a-f]+: 54ae 303b mfhc1 a1,\$f14
+[ 0-9a-f]+: 54af 303b mfhc1 a1,\$f15
+[ 0-9a-f]+: 54b0 303b mfhc1 a1,\$f16
+[ 0-9a-f]+: 54b1 303b mfhc1 a1,\$f17
+[ 0-9a-f]+: 54b2 303b mfhc1 a1,\$f18
+[ 0-9a-f]+: 54b3 303b mfhc1 a1,\$f19
+[ 0-9a-f]+: 54b4 303b mfhc1 a1,\$f20
+[ 0-9a-f]+: 54b5 303b mfhc1 a1,\$f21
+[ 0-9a-f]+: 54b6 303b mfhc1 a1,\$f22
+[ 0-9a-f]+: 54b7 303b mfhc1 a1,\$f23
+[ 0-9a-f]+: 54b8 303b mfhc1 a1,\$f24
+[ 0-9a-f]+: 54b9 303b mfhc1 a1,\$f25
+[ 0-9a-f]+: 54ba 303b mfhc1 a1,\$f26
+[ 0-9a-f]+: 54bb 303b mfhc1 a1,\$f27
+[ 0-9a-f]+: 54bc 303b mfhc1 a1,\$f28
+[ 0-9a-f]+: 54bd 303b mfhc1 a1,\$f29
+[ 0-9a-f]+: 54be 303b mfhc1 a1,\$f30
+[ 0-9a-f]+: 54bf 303b mfhc1 a1,\$f31
+[ 0-9a-f]+: 5401 207b mov\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 207b mov\.d \$f30,\$f31
+[ 0-9a-f]+: 5401 007b mov\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 007b mov\.s \$f30,\$f31
+[ 0-9a-f]+: 5401 407b mov\.ps \$f0,\$f1
+[ 0-9a-f]+: 57df 407b mov\.ps \$f30,\$f31
+[ 0-9a-f]+: 5443 0220 movf\.d \$f2,\$f3,\$fcc0
+[ 0-9a-f]+: 5443 2220 movf\.d \$f2,\$f3,\$fcc1
+[ 0-9a-f]+: 5443 4220 movf\.d \$f2,\$f3,\$fcc2
+[ 0-9a-f]+: 5443 6220 movf\.d \$f2,\$f3,\$fcc3
+[ 0-9a-f]+: 5443 8220 movf\.d \$f2,\$f3,\$fcc4
+[ 0-9a-f]+: 5443 a220 movf\.d \$f2,\$f3,\$fcc5
+[ 0-9a-f]+: 5443 c220 movf\.d \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 5443 e220 movf\.d \$f2,\$f3,\$fcc7
+[ 0-9a-f]+: 57df e220 movf\.d \$f30,\$f31,\$fcc7
+[ 0-9a-f]+: 5443 0020 movf\.s \$f2,\$f3,\$fcc0
+[ 0-9a-f]+: 5443 2020 movf\.s \$f2,\$f3,\$fcc1
+[ 0-9a-f]+: 5443 4020 movf\.s \$f2,\$f3,\$fcc2
+[ 0-9a-f]+: 5443 6020 movf\.s \$f2,\$f3,\$fcc3
+[ 0-9a-f]+: 5443 8020 movf\.s \$f2,\$f3,\$fcc4
+[ 0-9a-f]+: 5443 a020 movf\.s \$f2,\$f3,\$fcc5
+[ 0-9a-f]+: 5443 c020 movf\.s \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 5443 e020 movf\.s \$f2,\$f3,\$fcc7
+[ 0-9a-f]+: 57df e020 movf\.s \$f30,\$f31,\$fcc7
+[ 0-9a-f]+: 5443 0420 movf\.ps \$f2,\$f3,\$fcc0
+[ 0-9a-f]+: 5443 4420 movf\.ps \$f2,\$f3,\$fcc2
+[ 0-9a-f]+: 5443 8420 movf\.ps \$f2,\$f3,\$fcc4
+[ 0-9a-f]+: 5443 c420 movf\.ps \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 5443 c420 movf\.ps \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 57df c420 movf\.ps \$f30,\$f31,\$fcc6
+[ 0-9a-f]+: 5403 1138 movn\.d \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1138 movn\.d \$f2,\$f3,ra
+[ 0-9a-f]+: 5403 1038 movn\.s \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1038 movn\.s \$f2,\$f3,ra
+[ 0-9a-f]+: 5403 1238 movn\.ps \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1238 movn\.ps \$f2,\$f3,ra
+[ 0-9a-f]+: 5443 0460 movt\.ps \$f2,\$f3,\$fcc0
+[ 0-9a-f]+: 5443 4460 movt\.ps \$f2,\$f3,\$fcc2
+[ 0-9a-f]+: 5443 8460 movt\.ps \$f2,\$f3,\$fcc4
+[ 0-9a-f]+: 5443 c460 movt\.ps \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 5443 c460 movt\.ps \$f2,\$f3,\$fcc6
+[ 0-9a-f]+: 57df c460 movt\.ps \$f30,\$f31,\$fcc6
+[ 0-9a-f]+: 5403 1178 movz\.d \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1178 movz\.d \$f2,\$f3,ra
+[ 0-9a-f]+: 5403 1078 movz\.s \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1078 movz\.s \$f2,\$f3,ra
+[ 0-9a-f]+: 5403 1278 movz\.ps \$f2,\$f3,zero
+[ 0-9a-f]+: 57e3 1278 movz\.ps \$f2,\$f3,ra
+[ 0-9a-f]+: 5462 0069 msub\.d \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e769 msub\.d \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0061 msub\.s \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e761 msub\.s \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0071 msub\.ps \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e771 msub\.ps \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 54a0 283b mtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 283b mtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 283b mtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 283b mtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 283b mtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 283b mtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 283b mtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 283b mtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 283b mtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 283b mtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 283b mtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 283b mtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 283b mtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 283b mtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 283b mtc1 a1,\$f14
+[ 0-9a-f]+: 54af 283b mtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 283b mtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 283b mtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 283b mtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 283b mtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 283b mtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 283b mtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 283b mtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 283b mtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 283b mtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 283b mtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 283b mtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 283b mtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 283b mtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 283b mtc1 a1,\$f29
+[ 0-9a-f]+: 54be 283b mtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 283b mtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 283b mtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 283b mtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 283b mtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 283b mtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 283b mtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 283b mtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 283b mtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 283b mtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 283b mtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 283b mtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 283b mtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 283b mtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 283b mtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 283b mtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 283b mtc1 a1,\$f14
+[ 0-9a-f]+: 54af 283b mtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 283b mtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 283b mtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 283b mtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 283b mtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 283b mtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 283b mtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 283b mtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 283b mtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 283b mtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 283b mtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 283b mtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 283b mtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 283b mtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 283b mtc1 a1,\$f29
+[ 0-9a-f]+: 54be 283b mtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 283b mtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 383b mthc1 a1,\$f0
+[ 0-9a-f]+: 54a1 383b mthc1 a1,\$f1
+[ 0-9a-f]+: 54a2 383b mthc1 a1,\$f2
+[ 0-9a-f]+: 54a3 383b mthc1 a1,\$f3
+[ 0-9a-f]+: 54a4 383b mthc1 a1,\$f4
+[ 0-9a-f]+: 54a5 383b mthc1 a1,\$f5
+[ 0-9a-f]+: 54a6 383b mthc1 a1,\$f6
+[ 0-9a-f]+: 54a7 383b mthc1 a1,\$f7
+[ 0-9a-f]+: 54a8 383b mthc1 a1,\$f8
+[ 0-9a-f]+: 54a9 383b mthc1 a1,\$f9
+[ 0-9a-f]+: 54aa 383b mthc1 a1,\$f10
+[ 0-9a-f]+: 54ab 383b mthc1 a1,\$f11
+[ 0-9a-f]+: 54ac 383b mthc1 a1,\$f12
+[ 0-9a-f]+: 54ad 383b mthc1 a1,\$f13
+[ 0-9a-f]+: 54ae 383b mthc1 a1,\$f14
+[ 0-9a-f]+: 54af 383b mthc1 a1,\$f15
+[ 0-9a-f]+: 54b0 383b mthc1 a1,\$f16
+[ 0-9a-f]+: 54b1 383b mthc1 a1,\$f17
+[ 0-9a-f]+: 54b2 383b mthc1 a1,\$f18
+[ 0-9a-f]+: 54b3 383b mthc1 a1,\$f19
+[ 0-9a-f]+: 54b4 383b mthc1 a1,\$f20
+[ 0-9a-f]+: 54b5 383b mthc1 a1,\$f21
+[ 0-9a-f]+: 54b6 383b mthc1 a1,\$f22
+[ 0-9a-f]+: 54b7 383b mthc1 a1,\$f23
+[ 0-9a-f]+: 54b8 383b mthc1 a1,\$f24
+[ 0-9a-f]+: 54b9 383b mthc1 a1,\$f25
+[ 0-9a-f]+: 54ba 383b mthc1 a1,\$f26
+[ 0-9a-f]+: 54bb 383b mthc1 a1,\$f27
+[ 0-9a-f]+: 54bc 383b mthc1 a1,\$f28
+[ 0-9a-f]+: 54bd 383b mthc1 a1,\$f29
+[ 0-9a-f]+: 54be 383b mthc1 a1,\$f30
+[ 0-9a-f]+: 54bf 383b mthc1 a1,\$f31
+[ 0-9a-f]+: 54a0 383b mthc1 a1,\$f0
+[ 0-9a-f]+: 54a1 383b mthc1 a1,\$f1
+[ 0-9a-f]+: 54a2 383b mthc1 a1,\$f2
+[ 0-9a-f]+: 54a3 383b mthc1 a1,\$f3
+[ 0-9a-f]+: 54a4 383b mthc1 a1,\$f4
+[ 0-9a-f]+: 54a5 383b mthc1 a1,\$f5
+[ 0-9a-f]+: 54a6 383b mthc1 a1,\$f6
+[ 0-9a-f]+: 54a7 383b mthc1 a1,\$f7
+[ 0-9a-f]+: 54a8 383b mthc1 a1,\$f8
+[ 0-9a-f]+: 54a9 383b mthc1 a1,\$f9
+[ 0-9a-f]+: 54aa 383b mthc1 a1,\$f10
+[ 0-9a-f]+: 54ab 383b mthc1 a1,\$f11
+[ 0-9a-f]+: 54ac 383b mthc1 a1,\$f12
+[ 0-9a-f]+: 54ad 383b mthc1 a1,\$f13
+[ 0-9a-f]+: 54ae 383b mthc1 a1,\$f14
+[ 0-9a-f]+: 54af 383b mthc1 a1,\$f15
+[ 0-9a-f]+: 54b0 383b mthc1 a1,\$f16
+[ 0-9a-f]+: 54b1 383b mthc1 a1,\$f17
+[ 0-9a-f]+: 54b2 383b mthc1 a1,\$f18
+[ 0-9a-f]+: 54b3 383b mthc1 a1,\$f19
+[ 0-9a-f]+: 54b4 383b mthc1 a1,\$f20
+[ 0-9a-f]+: 54b5 383b mthc1 a1,\$f21
+[ 0-9a-f]+: 54b6 383b mthc1 a1,\$f22
+[ 0-9a-f]+: 54b7 383b mthc1 a1,\$f23
+[ 0-9a-f]+: 54b8 383b mthc1 a1,\$f24
+[ 0-9a-f]+: 54b9 383b mthc1 a1,\$f25
+[ 0-9a-f]+: 54ba 383b mthc1 a1,\$f26
+[ 0-9a-f]+: 54bb 383b mthc1 a1,\$f27
+[ 0-9a-f]+: 54bc 383b mthc1 a1,\$f28
+[ 0-9a-f]+: 54bd 383b mthc1 a1,\$f29
+[ 0-9a-f]+: 54be 383b mthc1 a1,\$f30
+[ 0-9a-f]+: 54bf 383b mthc1 a1,\$f31
+[ 0-9a-f]+: 5441 00b0 mul\.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e8b0 mul\.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e8b0 mul\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e8b0 mul\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 01b0 mul\.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e9b0 mul\.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e9b0 mul\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e9b0 mul\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 02b0 mul\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe eab0 mul\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd eab0 mul\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd eab0 mul\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5401 0b7b neg\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 0b7b neg\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 0b7b neg\.s \$f2,\$f2
+[ 0-9a-f]+: 5442 0b7b neg\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 2b7b neg\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 2b7b neg\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 2b7b neg\.d \$f2,\$f2
+[ 0-9a-f]+: 5442 2b7b neg\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 4b7b neg\.ps \$f0,\$f1
+[ 0-9a-f]+: 57df 4b7b neg\.ps \$f30,\$f31
+[ 0-9a-f]+: 5442 4b7b neg\.ps \$f2,\$f2
+[ 0-9a-f]+: 5442 4b7b neg\.ps \$f2,\$f2
+[ 0-9a-f]+: 5462 004a nmadd\.d \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e74a nmadd\.d \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0042 nmadd\.s \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e742 nmadd\.s \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0052 nmadd\.ps \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e752 nmadd\.ps \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 006a nmsub\.d \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e76a nmsub\.d \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0062 nmsub\.s \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e762 nmsub\.s \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5462 0072 nmsub\.ps \$f0,\$f1,\$f2,\$f3
+[ 0-9a-f]+: 57fe e772 nmsub\.ps \$f28,\$f29,\$f30,\$f31
+[ 0-9a-f]+: 5441 0080 pll\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e880 pll\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e880 pll\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e880 pll\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 00c0 plu\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e8c0 plu\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e8c0 plu\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e8c0 plu\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0100 pul\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e900 pul\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e900 pul\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e900 pul\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0140 puu\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e940 puu\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e940 puu\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e940 puu\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5401 123b recip\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 123b recip\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 123b recip\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 523b recip\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 523b recip\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 523b recip\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 333b round\.l\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 333b round\.l\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 333b round\.l\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 733b round\.l\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 733b round\.l\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 733b round\.l\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 3b3b round\.w\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 3b3b round\.w\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 3b3b round\.w\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 7b3b round\.w\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 7b3b round\.w\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 7b3b round\.w\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 023b rsqrt\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 023b rsqrt\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 023b rsqrt\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 423b rsqrt\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 423b rsqrt\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 423b rsqrt\.d \$f2,\$f2
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 ffff sdc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0001 sdc1 \$f3,1\(at\)
+[ 0-9a-f]+: b864 8001 sdc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 ffff sdc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 5678 sdc1 \$f3,22136\(at\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 ffff sdc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0001 sdc1 \$f3,1\(at\)
+[ 0-9a-f]+: b864 8001 sdc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 ffff sdc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 5678 sdc1 \$f3,22136\(at\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 5400 0108 sdxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 0108 sdxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 0108 sdxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 0108 sdxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 0108 sdxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 0908 sdxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 1108 sdxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f908 sdxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 5401 0a3b sqrt\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 0a3b sqrt\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 0a3b sqrt\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 4a3b sqrt\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 4a3b sqrt\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 4a3b sqrt\.d \$f2,\$f2
+[ 0-9a-f]+: 5441 0070 sub\.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e870 sub\.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e870 sub\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e870 sub\.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0170 sub\.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e970 sub\.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e970 sub\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e970 sub\.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0270 sub\.ps \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe ea70 sub\.ps \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd ea70 sub\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd ea70 sub\.ps \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5400 0188 suxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 0188 suxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 0188 suxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 0188 suxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 0188 suxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 0988 suxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 1188 suxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f988 suxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 5400 0048 lwxc1 \$f0,zero\(zero\)
+[ 0-9a-f]+: 5402 0048 lwxc1 \$f0,zero\(v0\)
+[ 0-9a-f]+: 541f 0048 lwxc1 \$f0,zero\(ra\)
+[ 0-9a-f]+: 545f 0048 lwxc1 \$f0,v0\(ra\)
+[ 0-9a-f]+: 57ff 0048 lwxc1 \$f0,ra\(ra\)
+[ 0-9a-f]+: 57ff 0848 lwxc1 \$f1,ra\(ra\)
+[ 0-9a-f]+: 57ff 1048 lwxc1 \$f2,ra\(ra\)
+[ 0-9a-f]+: 57ff f848 lwxc1 \$f31,ra\(ra\)
+[ 0-9a-f]+: 5401 233b trunc\.l\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 233b trunc\.l\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 233b trunc\.l\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 633b trunc\.l\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 633b trunc\.l\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 633b trunc\.l\.d \$f2,\$f2
+[ 0-9a-f]+: 5401 2b3b trunc\.w\.s \$f0,\$f1
+[ 0-9a-f]+: 57df 2b3b trunc\.w\.s \$f30,\$f31
+[ 0-9a-f]+: 5442 2b3b trunc\.w\.s \$f2,\$f2
+[ 0-9a-f]+: 5401 6b3b trunc\.w\.d \$f0,\$f1
+[ 0-9a-f]+: 57df 6b3b trunc\.w\.d \$f30,\$f31
+[ 0-9a-f]+: 5442 6b3b trunc\.w\.d \$f2,\$f2
+[ 0-9a-f]+: 5443 017b movf v0,v1,\$fcc0
+[ 0-9a-f]+: 57df 017b movf s8,ra,\$fcc0
+[ 0-9a-f]+: 57df 217b movf s8,ra,\$fcc1
+[ 0-9a-f]+: 57df 417b movf s8,ra,\$fcc2
+[ 0-9a-f]+: 57df 617b movf s8,ra,\$fcc3
+[ 0-9a-f]+: 57df 817b movf s8,ra,\$fcc4
+[ 0-9a-f]+: 57df a17b movf s8,ra,\$fcc5
+[ 0-9a-f]+: 57df c17b movf s8,ra,\$fcc6
+[ 0-9a-f]+: 57df e17b movf s8,ra,\$fcc7
+[ 0-9a-f]+: 5443 097b movt v0,v1,\$fcc0
+[ 0-9a-f]+: 57df 097b movt s8,ra,\$fcc0
+[ 0-9a-f]+: 57df 297b movt s8,ra,\$fcc1
+[ 0-9a-f]+: 57df 497b movt s8,ra,\$fcc2
+[ 0-9a-f]+: 57df 697b movt s8,ra,\$fcc3
+[ 0-9a-f]+: 57df 897b movt s8,ra,\$fcc4
+[ 0-9a-f]+: 57df a97b movt s8,ra,\$fcc5
+[ 0-9a-f]+: 57df c97b movt s8,ra,\$fcc6
+[ 0-9a-f]+: 57df e97b movt s8,ra,\$fcc7
+[ 0-9a-f]+: 43a4 fffe bc1t \$fcc1,[0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <fp_test\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4388 fffe bc1f \$fcc2,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 9400 fffe b [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0107 3150 addu a2,a3,t0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 438c fffe bc1f \$fcc3,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 05d8 addu v1,a0,a1
+[ 0-9a-f]+: 43b0 fffe bc1t \$fcc4,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0107 3150 addu a2,a3,t0
+
+[0-9a-f]+ <test_mips64>:
+[ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <test_mips64>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c43 move v0,v1
+[ 0-9a-f]+: 5860 1190 dneg v0,v1
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 5840 1190 dneg v0,v0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4042 fffe bgez v0,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 5840 1190 dneg v0,v0
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 5883 1110 dadd v0,v1,a0
+[ 0-9a-f]+: 5bfe e910 dadd sp,s8,ra
+[ 0-9a-f]+: 5862 1110 dadd v0,v0,v1
+[ 0-9a-f]+: 5862 1110 dadd v0,v0,v1
+[ 0-9a-f]+: 5843 001c daddi v0,v1,0
+[ 0-9a-f]+: 5843 005c daddi v0,v1,1
+[ 0-9a-f]+: 5843 801c daddi v0,v1,-512
+[ 0-9a-f]+: 5843 7fdc daddi v0,v1,511
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5821 8000 dsll at,at,0x10
+[ 0-9a-f]+: 5021 8765 ori at,at,0x8765
+[ 0-9a-f]+: 5821 8000 dsll at,at,0x10
+[ 0-9a-f]+: 5021 4321 ori at,at,0x4321
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 5843 001c daddi v0,v1,0
+[ 0-9a-f]+: 5843 005c daddi v0,v1,1
+[ 0-9a-f]+: 5843 801c daddi v0,v1,-512
+[ 0-9a-f]+: 5843 7fdc daddi v0,v1,511
+[ 0-9a-f]+: 5842 7fdc daddi v0,v0,511
+[ 0-9a-f]+: 5842 7fdc daddi v0,v0,511
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 1110 dadd v0,v1,at
+[ 0-9a-f]+: 5c43 0000 daddiu v0,v1,0
+[ 0-9a-f]+: 5c43 8000 daddiu v0,v1,-32768
+[ 0-9a-f]+: 5c43 7fff daddiu v0,v1,32767
+[ 0-9a-f]+: 5c42 7fff daddiu v0,v0,32767
+[ 0-9a-f]+: 5c42 7fff daddiu v0,v0,32767
+[ 0-9a-f]+: 5883 1150 daddu v0,v1,a0
+[ 0-9a-f]+: 5bfe e950 daddu sp,s8,ra
+[ 0-9a-f]+: 5862 1150 daddu v0,v0,v1
+[ 0-9a-f]+: 5862 1150 daddu v0,v0,v1
+[ 0-9a-f]+: 5803 1150 move v0,v1
+[ 0-9a-f]+: 5c43 0000 daddiu v0,v1,0
+[ 0-9a-f]+: 5c43 0001 daddiu v0,v1,1
+[ 0-9a-f]+: 5c43 7fff daddiu v0,v1,32767
+[ 0-9a-f]+: 5c43 8000 daddiu v0,v1,-32768
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 5823 1150 daddu v0,v1,at
+[ 0-9a-f]+: 5843 4b3c dclo v0,v1
+[ 0-9a-f]+: 5862 4b3c dclo v1,v0
+[ 0-9a-f]+: 5843 5b3c dclz v0,v1
+[ 0-9a-f]+: 5862 5b3c dclz v1,v0
+[ 0-9a-f]+: 5862 ab3c ddiv zero,v0,v1
+[ 0-9a-f]+: 5bfe ab3c ddiv zero,s8,ra
+[ 0-9a-f]+: 5860 ab3c ddiv zero,zero,v1
+[ 0-9a-f]+: 5be0 ab3c ddiv zero,zero,ra
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: b404 fffe bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 5883 ab3c ddiv zero,v1,a0
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b424 fffe bne a0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 5821 f808 dsll32 at,at,0x1f
+[ 0-9a-f]+: b423 fffe bne v1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 5880 1990 dneg v1,a0
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 5824 ab3c ddiv zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 5862 bb3c ddivu zero,v0,v1
+[ 0-9a-f]+: 5bfe bb3c ddivu zero,s8,ra
+[ 0-9a-f]+: 5860 bb3c ddivu zero,zero,v1
+[ 0-9a-f]+: 5be0 bb3c ddivu zero,zero,ra
+[ 0-9a-f]+: b400 fffe bnez zero,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 5803 bb3c ddivu zero,v1,zero
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: b404 fffe bnez a0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 5883 bb3c ddivu zero,v1,a0
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 0c64 move v1,a0
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 5824 bb3c ddivu zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 5824 bb3c ddivu zero,a0,at
+[ 0-9a-f]+: 4643 mflo v1
+[ 0-9a-f]+: 5843 07ec dext v0,v1,0x1f,0x1
+[ 0-9a-f]+: 5843 f82c dext v0,v1,0x0,0x20
+[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa
+[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa
+[ 0-9a-f]+: 5843 ffcc dins v0,v1,0x1f,0x1
+[ 0-9a-f]+: 5843 f80c dins v0,v1,0x0,0x20
+[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa
+[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa
+[ 0-9a-f]+: 41a2 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 41a2 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 3040 7fff li v0,32767
+[ 0-9a-f]+: 5040 ffff li v0,0xffff
+[ 0-9a-f]+: 41a2 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5678 ori v0,v0,0x5678
+[ 0-9a-f]+: 5840 00fc dmfc0 v0,c0_index
+[ 0-9a-f]+: 5841 00fc dmfc0 v0,c0_random
+[ 0-9a-f]+: 5842 00fc dmfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5843 00fc dmfc0 v0,c0_entrylo1
+[ 0-9a-f]+: 5844 00fc dmfc0 v0,c0_context
+[ 0-9a-f]+: 5845 00fc dmfc0 v0,c0_pagemask
+[ 0-9a-f]+: 5846 00fc dmfc0 v0,c0_wired
+[ 0-9a-f]+: 5847 00fc dmfc0 v0,c0_hwrena
+[ 0-9a-f]+: 5848 00fc dmfc0 v0,c0_badvaddr
+[ 0-9a-f]+: 5849 00fc dmfc0 v0,c0_count
+[ 0-9a-f]+: 584a 00fc dmfc0 v0,c0_entryhi
+[ 0-9a-f]+: 584b 00fc dmfc0 v0,c0_compare
+[ 0-9a-f]+: 584c 00fc dmfc0 v0,c0_status
+[ 0-9a-f]+: 584d 00fc dmfc0 v0,c0_cause
+[ 0-9a-f]+: 584e 00fc dmfc0 v0,c0_epc
+[ 0-9a-f]+: 584f 00fc dmfc0 v0,c0_prid
+[ 0-9a-f]+: 5850 00fc dmfc0 v0,c0_config
+[ 0-9a-f]+: 5851 00fc dmfc0 v0,c0_lladdr
+[ 0-9a-f]+: 5852 00fc dmfc0 v0,c0_watchlo
+[ 0-9a-f]+: 5853 00fc dmfc0 v0,c0_watchhi
+[ 0-9a-f]+: 5854 00fc dmfc0 v0,c0_xcontext
+[ 0-9a-f]+: 5855 00fc dmfc0 v0,\$21
+[ 0-9a-f]+: 5856 00fc dmfc0 v0,\$22
+[ 0-9a-f]+: 5857 00fc dmfc0 v0,c0_debug
+[ 0-9a-f]+: 5858 00fc dmfc0 v0,c0_depc
+[ 0-9a-f]+: 5859 00fc dmfc0 v0,c0_perfcnt
+[ 0-9a-f]+: 585a 00fc dmfc0 v0,c0_errctl
+[ 0-9a-f]+: 585b 00fc dmfc0 v0,c0_cacheerr
+[ 0-9a-f]+: 585c 00fc dmfc0 v0,c0_taglo
+[ 0-9a-f]+: 585d 00fc dmfc0 v0,c0_taghi
+[ 0-9a-f]+: 585e 00fc dmfc0 v0,c0_errorepc
+[ 0-9a-f]+: 585f 00fc dmfc0 v0,c0_desave
+[ 0-9a-f]+: 5840 00fc dmfc0 v0,c0_index
+[ 0-9a-f]+: 5840 08fc dmfc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 5840 10fc dmfc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 5840 18fc dmfc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 5840 20fc dmfc0 v0,\$0,4
+[ 0-9a-f]+: 5840 28fc dmfc0 v0,\$0,5
+[ 0-9a-f]+: 5840 30fc dmfc0 v0,\$0,6
+[ 0-9a-f]+: 5840 38fc dmfc0 v0,\$0,7
+[ 0-9a-f]+: 5841 00fc dmfc0 v0,c0_random
+[ 0-9a-f]+: 5841 08fc dmfc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 5841 10fc dmfc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 5841 18fc dmfc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 5841 20fc dmfc0 v0,c0_yqmask
+[ 0-9a-f]+: 5841 28fc dmfc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 5841 30fc dmfc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 5841 38fc dmfc0 v0,\$1,7
+[ 0-9a-f]+: 5842 00fc dmfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5842 08fc dmfc0 v0,c0_tcstatus
+[ 0-9a-f]+: 5842 10fc dmfc0 v0,c0_tcbind
+[ 0-9a-f]+: 5842 18fc dmfc0 v0,c0_tcrestart
+[ 0-9a-f]+: 5842 20fc dmfc0 v0,c0_tchalt
+[ 0-9a-f]+: 5842 28fc dmfc0 v0,c0_tccontext
+[ 0-9a-f]+: 5842 30fc dmfc0 v0,c0_tcschedule
+[ 0-9a-f]+: 5842 38fc dmfc0 v0,c0_tcschefback
+[ 0-9a-f]+: 5840 02fc dmtc0 v0,c0_index
+[ 0-9a-f]+: 5841 02fc dmtc0 v0,c0_random
+[ 0-9a-f]+: 5842 02fc dmtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5843 02fc dmtc0 v0,c0_entrylo1
+[ 0-9a-f]+: 5844 02fc dmtc0 v0,c0_context
+[ 0-9a-f]+: 5845 02fc dmtc0 v0,c0_pagemask
+[ 0-9a-f]+: 5846 02fc dmtc0 v0,c0_wired
+[ 0-9a-f]+: 5847 02fc dmtc0 v0,c0_hwrena
+[ 0-9a-f]+: 5848 02fc dmtc0 v0,c0_badvaddr
+[ 0-9a-f]+: 5849 02fc dmtc0 v0,c0_count
+[ 0-9a-f]+: 584a 02fc dmtc0 v0,c0_entryhi
+[ 0-9a-f]+: 584b 02fc dmtc0 v0,c0_compare
+[ 0-9a-f]+: 584c 02fc dmtc0 v0,c0_status
+[ 0-9a-f]+: 584d 02fc dmtc0 v0,c0_cause
+[ 0-9a-f]+: 584e 02fc dmtc0 v0,c0_epc
+[ 0-9a-f]+: 584f 02fc dmtc0 v0,c0_prid
+[ 0-9a-f]+: 5850 02fc dmtc0 v0,c0_config
+[ 0-9a-f]+: 5851 02fc dmtc0 v0,c0_lladdr
+[ 0-9a-f]+: 5852 02fc dmtc0 v0,c0_watchlo
+[ 0-9a-f]+: 5853 02fc dmtc0 v0,c0_watchhi
+[ 0-9a-f]+: 5854 02fc dmtc0 v0,c0_xcontext
+[ 0-9a-f]+: 5855 02fc dmtc0 v0,\$21
+[ 0-9a-f]+: 5856 02fc dmtc0 v0,\$22
+[ 0-9a-f]+: 5857 02fc dmtc0 v0,c0_debug
+[ 0-9a-f]+: 5858 02fc dmtc0 v0,c0_depc
+[ 0-9a-f]+: 5859 02fc dmtc0 v0,c0_perfcnt
+[ 0-9a-f]+: 585a 02fc dmtc0 v0,c0_errctl
+[ 0-9a-f]+: 585b 02fc dmtc0 v0,c0_cacheerr
+[ 0-9a-f]+: 585c 02fc dmtc0 v0,c0_taglo
+[ 0-9a-f]+: 585d 02fc dmtc0 v0,c0_taghi
+[ 0-9a-f]+: 585e 02fc dmtc0 v0,c0_errorepc
+[ 0-9a-f]+: 585f 02fc dmtc0 v0,c0_desave
+[ 0-9a-f]+: 5840 02fc dmtc0 v0,c0_index
+[ 0-9a-f]+: 5840 0afc dmtc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 5840 12fc dmtc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 5840 1afc dmtc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 5840 22fc dmtc0 v0,\$0,4
+[ 0-9a-f]+: 5840 2afc dmtc0 v0,\$0,5
+[ 0-9a-f]+: 5840 32fc dmtc0 v0,\$0,6
+[ 0-9a-f]+: 5840 3afc dmtc0 v0,\$0,7
+[ 0-9a-f]+: 5841 02fc dmtc0 v0,c0_random
+[ 0-9a-f]+: 5841 0afc dmtc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 5841 12fc dmtc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 5841 1afc dmtc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 5841 22fc dmtc0 v0,c0_yqmask
+[ 0-9a-f]+: 5841 2afc dmtc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 5841 32fc dmtc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 5841 3afc dmtc0 v0,\$1,7
+[ 0-9a-f]+: 5842 02fc dmtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5842 0afc dmtc0 v0,c0_tcstatus
+[ 0-9a-f]+: 5842 12fc dmtc0 v0,c0_tcbind
+[ 0-9a-f]+: 5842 1afc dmtc0 v0,c0_tcrestart
+[ 0-9a-f]+: 5842 22fc dmtc0 v0,c0_tchalt
+[ 0-9a-f]+: 5842 2afc dmtc0 v0,c0_tccontext
+[ 0-9a-f]+: 5842 32fc dmtc0 v0,c0_tcschedule
+[ 0-9a-f]+: 5842 3afc dmtc0 v0,c0_tcschefback
+[ 0-9a-f]+: 54a0 243b dmfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 243b dmfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 243b dmfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 243b dmfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 243b dmfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 243b dmfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 243b dmfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 243b dmfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 243b dmfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 243b dmfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 243b dmfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 243b dmfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 243b dmfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 243b dmfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 243b dmfc1 a1,\$f14
+[ 0-9a-f]+: 54af 243b dmfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 243b dmfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 243b dmfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 243b dmfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 243b dmfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 243b dmfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 243b dmfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 243b dmfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 243b dmfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 243b dmfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 243b dmfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 243b dmfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 243b dmfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 243b dmfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
+[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 243b dmfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 243b dmfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 243b dmfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 243b dmfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 243b dmfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 243b dmfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 243b dmfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 243b dmfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 243b dmfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 243b dmfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 243b dmfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 243b dmfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 243b dmfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 243b dmfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 243b dmfc1 a1,\$f14
+[ 0-9a-f]+: 54af 243b dmfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 243b dmfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 243b dmfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 243b dmfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 243b dmfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 243b dmfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 243b dmfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 243b dmfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 243b dmfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 243b dmfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 243b dmfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 243b dmfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 243b dmfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 243b dmfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
+[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31
+[ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0
+[ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1
+[ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2
+[ 0-9a-f]+: 0043 6d3c dmfc2 v0,\$3
+[ 0-9a-f]+: 0044 6d3c dmfc2 v0,\$4
+[ 0-9a-f]+: 0045 6d3c dmfc2 v0,\$5
+[ 0-9a-f]+: 0046 6d3c dmfc2 v0,\$6
+[ 0-9a-f]+: 0047 6d3c dmfc2 v0,\$7
+[ 0-9a-f]+: 0048 6d3c dmfc2 v0,\$8
+[ 0-9a-f]+: 0049 6d3c dmfc2 v0,\$9
+[ 0-9a-f]+: 004a 6d3c dmfc2 v0,\$10
+[ 0-9a-f]+: 004b 6d3c dmfc2 v0,\$11
+[ 0-9a-f]+: 004c 6d3c dmfc2 v0,\$12
+[ 0-9a-f]+: 004d 6d3c dmfc2 v0,\$13
+[ 0-9a-f]+: 004e 6d3c dmfc2 v0,\$14
+[ 0-9a-f]+: 004f 6d3c dmfc2 v0,\$15
+[ 0-9a-f]+: 0050 6d3c dmfc2 v0,\$16
+[ 0-9a-f]+: 0051 6d3c dmfc2 v0,\$17
+[ 0-9a-f]+: 0052 6d3c dmfc2 v0,\$18
+[ 0-9a-f]+: 0053 6d3c dmfc2 v0,\$19
+[ 0-9a-f]+: 0054 6d3c dmfc2 v0,\$20
+[ 0-9a-f]+: 0055 6d3c dmfc2 v0,\$21
+[ 0-9a-f]+: 0056 6d3c dmfc2 v0,\$22
+[ 0-9a-f]+: 0057 6d3c dmfc2 v0,\$23
+[ 0-9a-f]+: 0058 6d3c dmfc2 v0,\$24
+[ 0-9a-f]+: 0059 6d3c dmfc2 v0,\$25
+[ 0-9a-f]+: 005a 6d3c dmfc2 v0,\$26
+[ 0-9a-f]+: 005b 6d3c dmfc2 v0,\$27
+[ 0-9a-f]+: 005c 6d3c dmfc2 v0,\$28
+[ 0-9a-f]+: 005d 6d3c dmfc2 v0,\$29
+[ 0-9a-f]+: 005e 6d3c dmfc2 v0,\$30
+[ 0-9a-f]+: 005f 6d3c dmfc2 v0,\$31
+[ 0-9a-f]+: 0040 7d3c dmtc2 v0,\$0
+[ 0-9a-f]+: 0041 7d3c dmtc2 v0,\$1
+[ 0-9a-f]+: 0042 7d3c dmtc2 v0,\$2
+[ 0-9a-f]+: 0043 7d3c dmtc2 v0,\$3
+[ 0-9a-f]+: 0044 7d3c dmtc2 v0,\$4
+[ 0-9a-f]+: 0045 7d3c dmtc2 v0,\$5
+[ 0-9a-f]+: 0046 7d3c dmtc2 v0,\$6
+[ 0-9a-f]+: 0047 7d3c dmtc2 v0,\$7
+[ 0-9a-f]+: 0048 7d3c dmtc2 v0,\$8
+[ 0-9a-f]+: 0049 7d3c dmtc2 v0,\$9
+[ 0-9a-f]+: 004a 7d3c dmtc2 v0,\$10
+[ 0-9a-f]+: 004b 7d3c dmtc2 v0,\$11
+[ 0-9a-f]+: 004c 7d3c dmtc2 v0,\$12
+[ 0-9a-f]+: 004d 7d3c dmtc2 v0,\$13
+[ 0-9a-f]+: 004e 7d3c dmtc2 v0,\$14
+[ 0-9a-f]+: 004f 7d3c dmtc2 v0,\$15
+[ 0-9a-f]+: 0050 7d3c dmtc2 v0,\$16
+[ 0-9a-f]+: 0051 7d3c dmtc2 v0,\$17
+[ 0-9a-f]+: 0052 7d3c dmtc2 v0,\$18
+[ 0-9a-f]+: 0053 7d3c dmtc2 v0,\$19
+[ 0-9a-f]+: 0054 7d3c dmtc2 v0,\$20
+[ 0-9a-f]+: 0055 7d3c dmtc2 v0,\$21
+[ 0-9a-f]+: 0056 7d3c dmtc2 v0,\$22
+[ 0-9a-f]+: 0057 7d3c dmtc2 v0,\$23
+[ 0-9a-f]+: 0058 7d3c dmtc2 v0,\$24
+[ 0-9a-f]+: 0059 7d3c dmtc2 v0,\$25
+[ 0-9a-f]+: 005a 7d3c dmtc2 v0,\$26
+[ 0-9a-f]+: 005b 7d3c dmtc2 v0,\$27
+[ 0-9a-f]+: 005c 7d3c dmtc2 v0,\$28
+[ 0-9a-f]+: 005d 7d3c dmtc2 v0,\$29
+[ 0-9a-f]+: 005e 7d3c dmtc2 v0,\$30
+[ 0-9a-f]+: 005f 7d3c dmtc2 v0,\$31
+[ 0-9a-f]+: 5862 8b3c dmult v0,v1
+[ 0-9a-f]+: 5862 9b3c dmultu v0,v1
+[ 0-9a-f]+: 5883 9b3c dmultu v1,a0
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 8b3c dmult v1,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 5883 8b3c dmult v1,a0
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 5842 f888 dsra32 v0,v0,0x1f
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 9422 fffe beq v0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 3020 0004 li at,4
+[ 0-9a-f]+: 5823 8b3c dmult v1,at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 5842 f888 dsra32 v0,v0,0x1f
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 9422 fffe beq v0,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 5883 9b3c dmultu v1,a0
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 0004 li at,4
+[ 0-9a-f]+: 5823 9b3c dmultu v1,at
+[ 0-9a-f]+: 4601 mfhi at
+[ 0-9a-f]+: 4642 mflo v0
+[ 0-9a-f]+: 9401 fffe beqz at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 5824 ab3c ddiv zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 5862 ab3c ddiv zero,v0,v1
+[ 0-9a-f]+: 5bfe ab3c ddiv zero,s8,ra
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 5860 ab3c ddiv zero,zero,v1
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b423 fffe bne v1,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 5821 f808 dsll32 at,at,0x1f
+[ 0-9a-f]+: b420 fffe bne zero,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: b41f fffe bnez ra,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 5be0 ab3c ddiv zero,zero,ra
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: b43f fffe bne ra,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 3020 0001 li at,1
+[ 0-9a-f]+: 5821 f808 dsll32 at,at,0x1f
+[ 0-9a-f]+: b420 fffe bne zero,at,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4686 break 0x6
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 5824 ab3c ddiv zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 5862 bb3c ddivu zero,v0,v1
+[ 0-9a-f]+: 5bfe bb3c ddivu zero,s8,ra
+[ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 5860 bb3c ddivu zero,zero,v1
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: b41f fffe bnez ra,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[ 0-9a-f]+: 5be0 bb3c ddivu zero,zero,ra
+[ 0-9a-f]+: 4687 break 0x7
+
+[0-9a-f]+ <.*>:
+[ 0-9a-f]+: 4600 mfhi zero
+[ 0-9a-f]+: 4687 break 0x7
+[ 0-9a-f]+: 0c60 move v1,zero
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 5824 bb3c ddivu zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 3020 0002 li at,2
+[ 0-9a-f]+: 5824 bb3c ddivu zero,a0,at
+[ 0-9a-f]+: 4603 mfhi v1
+[ 0-9a-f]+: 5880 11d0 dnegu v0,a0
+[ 0-9a-f]+: 5862 10d0 drorv v0,v1,v0
+[ 0-9a-f]+: 5880 09d0 dnegu at,a0
+[ 0-9a-f]+: 5841 10d0 drorv v0,v0,at
+[ 0-9a-f]+: 5843 e0c8 dror32 v0,v1,0x1c
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c0 dror v0,v1,0x4
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5880 11d0 dnegu v0,a0
+[ 0-9a-f]+: 5862 10d0 drorv v0,v1,v0
+[ 0-9a-f]+: 5880 09d0 dnegu at,a0
+[ 0-9a-f]+: 5841 10d0 drorv v0,v0,at
+[ 0-9a-f]+: 5843 e0c8 dror32 v0,v1,0x1c
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c0 dror v0,v1,0x4
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5843 7b3c dsbh v0,v1
+[ 0-9a-f]+: 5842 7b3c dsbh v0,v0
+[ 0-9a-f]+: 5842 7b3c dsbh v0,v0
+[ 0-9a-f]+: 5843 fb3c dshd v0,v1
+[ 0-9a-f]+: 5842 fb3c dshd v0,v0
+[ 0-9a-f]+: 5842 fb3c dshd v0,v0
+[ 0-9a-f]+: 5864 1010 dsllv v0,v1,a0
+[ 0-9a-f]+: 5843 f808 dsll32 v0,v1,0x1f
+[ 0-9a-f]+: 5864 1010 dsllv v0,v1,a0
+[ 0-9a-f]+: 5843 f808 dsll32 v0,v1,0x1f
+[ 0-9a-f]+: 5843 f800 dsll v0,v1,0x1f
+[ 0-9a-f]+: 5864 1090 dsrav v0,v1,a0
+[ 0-9a-f]+: 5843 2088 dsra32 v0,v1,0x4
+[ 0-9a-f]+: 5864 1090 dsrav v0,v1,a0
+[ 0-9a-f]+: 5843 2088 dsra32 v0,v1,0x4
+[ 0-9a-f]+: 5843 2080 dsra v0,v1,0x4
+[ 0-9a-f]+: 5864 1050 dsrlv v0,v1,a0
+[ 0-9a-f]+: 5843 f848 dsrl32 v0,v1,0x1f
+[ 0-9a-f]+: 5864 1050 dsrlv v0,v1,a0
+[ 0-9a-f]+: 5843 2048 dsrl32 v0,v1,0x4
+[ 0-9a-f]+: 5843 2040 dsrl v0,v1,0x4
+[ 0-9a-f]+: 5883 1190 dsub v0,v1,a0
+[ 0-9a-f]+: 5bfe e990 dsub sp,s8,ra
+[ 0-9a-f]+: 5862 1190 dsub v0,v0,v1
+[ 0-9a-f]+: 5862 1190 dsub v0,v0,v1
+[ 0-9a-f]+: 5883 11d0 dsubu v0,v1,a0
+[ 0-9a-f]+: 5bfe e9d0 dsubu sp,s8,ra
+[ 0-9a-f]+: 5862 11d0 dsubu v0,v0,v1
+[ 0-9a-f]+: 5862 11d0 dsubu v0,v0,v1
+[ 0-9a-f]+: 5c43 edcc daddiu v0,v1,-4660
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 11d0 dsubu v0,v1,at
+[ 0-9a-f]+: 5843 001c daddi v0,v1,0
+[ 0-9a-f]+: 5843 ffdc daddi v0,v1,-1
+[ 0-9a-f]+: 5843 801c daddi v0,v1,-512
+[ 0-9a-f]+: 5843 7fdc daddi v0,v1,511
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 5823 1190 dsub v0,v1,at
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 5823 1190 dsub v0,v1,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 5823 1190 dsub v0,v1,at
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 1190 dsub v0,v1,at
+[ 0-9a-f]+: 41a1 8888 lui at,0x8888
+[ 0-9a-f]+: 5021 1111 ori at,at,0x1111
+[ 0-9a-f]+: 5821 8000 dsll at,at,0x10
+[ 0-9a-f]+: 5021 1234 ori at,at,0x1234
+[ 0-9a-f]+: 5821 8000 dsll at,at,0x10
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 1190 dsub v0,v1,at
+[ 0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ 0-9a-f]+: dc40 0004 ld v0,4\(zero\)
+[ 0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ 0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ 0-9a-f]+: dc40 0004 ld v0,4\(zero\)
+[ 0-9a-f]+: dc43 0004 ld v0,4\(v1\)
+[ 0-9a-f]+: dc43 8000 ld v0,-32768\(v1\)
+[ 0-9a-f]+: dc43 7fff ld v0,32767\(v1\)
+[ 0-9a-f]+: 6040 4000 ldl v0,0\(zero\)
+[ 0-9a-f]+: 6040 4004 ldl v0,4\(zero\)
+[ 0-9a-f]+: 6040 4000 ldl v0,0\(zero\)
+[ 0-9a-f]+: 6040 4000 ldl v0,0\(zero\)
+[ 0-9a-f]+: 6040 4004 ldl v0,4\(zero\)
+[ 0-9a-f]+: 6043 4004 ldl v0,4\(v1\)
+[ 0-9a-f]+: 6043 4e00 ldl v0,-512\(v1\)
+[ 0-9a-f]+: 6043 41ff ldl v0,511\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 4000 ldl v0,0\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 4678 ldl v0,1656\(at\)
+[ 0-9a-f]+: 6040 5000 ldr v0,0\(zero\)
+[ 0-9a-f]+: 6040 5004 ldr v0,4\(zero\)
+[ 0-9a-f]+: 6040 5000 ldr v0,0\(zero\)
+[ 0-9a-f]+: 6040 5000 ldr v0,0\(zero\)
+[ 0-9a-f]+: 6040 5004 ldr v0,4\(zero\)
+[ 0-9a-f]+: 6043 5004 ldr v0,4\(v1\)
+[ 0-9a-f]+: 6043 5e00 ldr v0,-512\(v1\)
+[ 0-9a-f]+: 6043 51ff ldr v0,511\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 5000 ldr v0,0\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 5678 ldr v0,1656\(at\)
+[ 0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ 0-9a-f]+: 6040 7004 lld v0,4\(zero\)
+[ 0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ 0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ 0-9a-f]+: 6040 7004 lld v0,4\(zero\)
+[ 0-9a-f]+: 6043 7004 lld v0,4\(v1\)
+[ 0-9a-f]+: 6043 7e00 lld v0,-512\(v1\)
+[ 0-9a-f]+: 6043 71ff lld v0,511\(v1\)
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ 0-9a-f]+: 6042 7000 lld v0,0\(v0\)
+[ 0-9a-f]+: 41a2 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5000 ori v0,v0,0x5000
+[ 0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ 0-9a-f]+: 6042 7678 lld v0,1656\(v0\)
+[ 0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ 0-9a-f]+: 6040 e004 lwu v0,4\(zero\)
+[ 0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ 0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ 0-9a-f]+: 6040 e004 lwu v0,4\(zero\)
+[ 0-9a-f]+: 6043 e004 lwu v0,4\(v1\)
+[ 0-9a-f]+: 6043 ee00 lwu v0,-512\(v1\)
+[ 0-9a-f]+: 6043 e1ff lwu v0,511\(v1\)
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ 0-9a-f]+: 6042 e000 lwu v0,0\(v0\)
+[ 0-9a-f]+: 41a2 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5000 ori v0,v0,0x5000
+[ 0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ 0-9a-f]+: 6042 e678 lwu v0,1656\(v0\)
+[ 0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ 0-9a-f]+: 6040 f004 scd v0,4\(zero\)
+[ 0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ 0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ 0-9a-f]+: 6040 f004 scd v0,4\(zero\)
+[ 0-9a-f]+: 6043 f004 scd v0,4\(v1\)
+[ 0-9a-f]+: 6043 fe00 scd v0,-512\(v1\)
+[ 0-9a-f]+: 6043 f1ff scd v0,511\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 f000 scd v0,0\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 f678 scd v0,1656\(at\)
+[ 0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ 0-9a-f]+: d840 0004 sd v0,4\(zero\)
+[ 0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ 0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ 0-9a-f]+: d840 0004 sd v0,4\(zero\)
+[ 0-9a-f]+: d843 0004 sd v0,4\(v1\)
+[ 0-9a-f]+: d843 8000 sd v0,-32768\(v1\)
+[ 0-9a-f]+: d843 7fff sd v0,32767\(v1\)
+[ 0-9a-f]+: 6040 c000 sdl v0,0\(zero\)
+[ 0-9a-f]+: 6040 c004 sdl v0,4\(zero\)
+[ 0-9a-f]+: 6040 c000 sdl v0,0\(zero\)
+[ 0-9a-f]+: 6040 c000 sdl v0,0\(zero\)
+[ 0-9a-f]+: 6040 c004 sdl v0,4\(zero\)
+[ 0-9a-f]+: 6043 c004 sdl v0,4\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 c000 sdl v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 cfff sdl v0,-1\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 c678 sdl v0,1656\(at\)
+[ 0-9a-f]+: 6040 d000 sdr v0,0\(zero\)
+[ 0-9a-f]+: 6040 d004 sdr v0,4\(zero\)
+[ 0-9a-f]+: 6040 d000 sdr v0,0\(zero\)
+[ 0-9a-f]+: 6040 d000 sdr v0,0\(zero\)
+[ 0-9a-f]+: 6040 d004 sdr v0,4\(zero\)
+[ 0-9a-f]+: 6043 d004 sdr v0,4\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 d000 sdr v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 dfff sdr v0,-1\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 d678 sdr v0,1656\(at\)
+[ 0-9a-f]+: 2020 7000 ldm s0,0\(zero\)
+[ 0-9a-f]+: 2020 7004 ldm s0,4\(zero\)
+[ 0-9a-f]+: 2025 7000 ldm s0,0\(a1\)
+[ 0-9a-f]+: 2025 77ff ldm s0,2047\(a1\)
+[ 0-9a-f]+: 2045 77ff ldm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 77ff ldm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 77ff ldm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 77ff ldm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 77ff ldm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 77ff ldm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 77ff ldm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 77ff ldm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 77ff ldm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 7000 ldm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 7000 ldm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 7000 ldm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 7000 ldm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 7000 ldm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 7000 ldm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 7000 ldm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 7000 ldm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 7000 ldm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ 0-9a-f]+: 2020 7000 ldm s0,0\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ 0-9a-f]+: 203d 7000 ldm s0,0\(sp\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 7678 ldm s0,1656\(at\)
+[ 0-9a-f]+: 2040 4000 ldp v0,0\(zero\)
+[ 0-9a-f]+: 2040 4004 ldp v0,4\(zero\)
+[ 0-9a-f]+: 205d 4000 ldp v0,0\(sp\)
+[ 0-9a-f]+: 205d 4000 ldp v0,0\(sp\)
+[ 0-9a-f]+: 2043 4800 ldp v0,-2048\(v1\)
+[ 0-9a-f]+: 2043 47ff ldp v0,2047\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 4000 ldp v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 4fff ldp v0,-1\(at\)
+[ 0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 4fff ldp v0,-1\(at\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
+[ 0-9a-f]+: 5060 8000 li v1,0x8000
+[ 0-9a-f]+: 2043 4fff ldp v0,-1\(v1\)
+[ 0-9a-f]+: 41a3 0001 lui v1,0x1
+[ 0-9a-f]+: 2043 4fff ldp v0,-1\(v1\)
+[ 0-9a-f]+: 41a3 1234 lui v1,0x1234
+[ 0-9a-f]+: 5063 5000 ori v1,v1,0x5000
+[ 0-9a-f]+: 2043 4678 ldp v0,1656\(v1\)
+[ 0-9a-f]+: 2020 f000 sdm s0,0\(zero\)
+[ 0-9a-f]+: 2020 f004 sdm s0,4\(zero\)
+[ 0-9a-f]+: 2025 f000 sdm s0,0\(a1\)
+[ 0-9a-f]+: 2025 f7ff sdm s0,2047\(a1\)
+[ 0-9a-f]+: 2045 f7ff sdm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 f7ff sdm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 f7ff sdm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 f7ff sdm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 f7ff sdm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 f7ff sdm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 f7ff sdm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 f7ff sdm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 f7ff sdm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 f000 sdm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 f000 sdm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 f000 sdm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 f000 sdm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 f000 sdm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 f000 sdm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 f000 sdm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 f000 sdm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 f000 sdm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ 0-9a-f]+: 2020 f000 sdm s0,0\(zero\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ 0-9a-f]+: 203d f000 sdm s0,0\(sp\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 f678 sdm s0,1656\(at\)
+[ 0-9a-f]+: 2040 c000 sdp v0,0\(zero\)
+[ 0-9a-f]+: 2040 c004 sdp v0,4\(zero\)
+[ 0-9a-f]+: 205d c000 sdp v0,0\(sp\)
+[ 0-9a-f]+: 205d c000 sdp v0,0\(sp\)
+[ 0-9a-f]+: 2043 c800 sdp v0,-2048\(v1\)
+[ 0-9a-f]+: 2043 c7ff sdp v0,2047\(v1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ 0-9a-f]+: 2043 c000 sdp v0,0\(v1\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ 0-9a-f]+: 5020 8000 li at,0x8000
+[ 0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ 0-9a-f]+: 41a1 0001 lui at,0x1
+[ 0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 2041 c678 sdp v0,1656\(at\)
+[ 0-9a-f]+: 6060 4000 ldl v1,0\(zero\)
+[ 0-9a-f]+: 6060 5007 ldr v1,7\(zero\)
+[ 0-9a-f]+: 6060 4000 ldl v1,0\(zero\)
+[ 0-9a-f]+: 6060 5007 ldr v1,7\(zero\)
+[ 0-9a-f]+: 6060 4004 ldl v1,4\(zero\)
+[ 0-9a-f]+: 6060 500b ldr v1,11\(zero\)
+[ 0-9a-f]+: 6060 4004 ldl v1,4\(zero\)
+[ 0-9a-f]+: 6060 500b ldr v1,11\(zero\)
+[ 0-9a-f]+: 3020 07ff li at,2047
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 6060 4800 ldl v1,-2048\(zero\)
+[ 0-9a-f]+: 6060 5807 ldr v1,-2041\(zero\)
+[ 0-9a-f]+: 3020 0800 li at,2048
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 f7ff li at,-2049
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 7ff1 li at,32753
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 6064 4000 ldl v1,0\(a0\)
+[ 0-9a-f]+: 6064 5007 ldr v1,7\(a0\)
+[ 0-9a-f]+: 6064 4004 ldl v1,4\(a0\)
+[ 0-9a-f]+: 6064 500b ldr v1,11\(a0\)
+[ 0-9a-f]+: 3024 07ff addiu at,a0,2047
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 6064 4800 ldl v1,-2048\(a0\)
+[ 0-9a-f]+: 6064 5807 ldr v1,-2041\(a0\)
+[ 0-9a-f]+: 3024 0800 addiu at,a0,2048
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3024 f7ff addiu at,a0,-2049
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3024 7ff1 addiu at,a0,32753
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 4000 ldl v1,0\(at\)
+[ 0-9a-f]+: 6061 5007 ldr v1,7\(at\)
+[ 0-9a-f]+: 6060 c000 sdl v1,0\(zero\)
+[ 0-9a-f]+: 6060 d007 sdr v1,7\(zero\)
+[ 0-9a-f]+: 6060 c000 sdl v1,0\(zero\)
+[ 0-9a-f]+: 6060 d007 sdr v1,7\(zero\)
+[ 0-9a-f]+: 6060 c004 sdl v1,4\(zero\)
+[ 0-9a-f]+: 6060 d00b sdr v1,11\(zero\)
+[ 0-9a-f]+: 6060 c004 sdl v1,4\(zero\)
+[ 0-9a-f]+: 6060 d00b sdr v1,11\(zero\)
+[ 0-9a-f]+: 3020 07ff li at,2047
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 6060 c800 sdl v1,-2048\(zero\)
+[ 0-9a-f]+: 6060 d807 sdr v1,-2041\(zero\)
+[ 0-9a-f]+: 3020 0800 li at,2048
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 f7ff li at,-2049
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 7ff1 li at,32753
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 6064 c000 sdl v1,0\(a0\)
+[ 0-9a-f]+: 6064 d007 sdr v1,7\(a0\)
+[ 0-9a-f]+: 6064 c004 sdl v1,4\(a0\)
+[ 0-9a-f]+: 6064 d00b sdr v1,11\(a0\)
+[ 0-9a-f]+: 3024 07ff addiu at,a0,2047
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 6064 c800 sdl v1,-2048\(a0\)
+[ 0-9a-f]+: 6064 d807 sdr v1,-2041\(a0\)
+[ 0-9a-f]+: 3024 0800 addiu at,a0,2048
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3024 f7ff addiu at,a0,-2049
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3024 7ff1 addiu at,a0,32753
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 41a1 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 c000 sdl v1,0\(at\)
+[ 0-9a-f]+: 6061 d007 sdr v1,7\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 4000 ldl s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 5000 ldr s0,0\(at\)
+[ 0-9a-f]+: 3203 0000 addiu s0,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6210 7000 lld s0,0\(s0\)
+[ 0-9a-f]+: 3203 0000 addiu s0,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6210 e000 lwu s0,0\(s0\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 f000 scd s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 c000 sdl s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 d000 sdr s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 3223 0000 addiu s1,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2211 4000 ldp s0,0\(s1\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 c000 sdp s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 2000 ldc2 \$16,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 a000 sdc2 \$16,0\(at\)
+
+[0-9a-f]+ <test_delay_slot>:
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <test_delay_slot>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4063 fffe bgezal v1,[0-9a-f]+ <test_delay_slot\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4023 fffe bltzal v1,[0-9a-f]+ <test_delay_slot\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4263 fffe bgezals v1,[0-9a-f]+ <test_delay_slot\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4223 fffe bltzals v1,[0-9a-f]+ <test_delay_slot\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: f400 0000 jal [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test_delay_slot
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: f000 0000 jalx [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test_delay_slot
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 45c2 jalr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e2 0f3c jalr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4582 jr v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0002 0f3c jr v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 03e2 1f3c jalr\.hb v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0002 1f3c jr\.hb v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 7400 0000 jals [0-9a-f]+ <test>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 test_delay_slot
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 45e2 jalrs v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 03e2 4f3c jalrs v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0002 4f3c jrs v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 03e2 5f3c jalrs\.hb v0
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 0002 5f3c jrs\.hb v0
+[ 0-9a-f]+: 0c00 nop
+
+[0-9a-f]+ <test_spec102>:
+[ 0-9a-f]+: 6540 lw v0,-256\(gp\)
+[ 0-9a-f]+: 65c0 lw v1,-256\(gp\)
+[ 0-9a-f]+: 6640 lw a0,-256\(gp\)
+[ 0-9a-f]+: 66c0 lw a1,-256\(gp\)
+[ 0-9a-f]+: 6740 lw a2,-256\(gp\)
+[ 0-9a-f]+: 67c0 lw a3,-256\(gp\)
+[ 0-9a-f]+: 6440 lw s0,-256\(gp\)
+[ 0-9a-f]+: 64c0 lw s1,-256\(gp\)
+[ 0-9a-f]+: 64c1 lw s1,-252\(gp\)
+[ 0-9a-f]+: 64ff lw s1,-4\(gp\)
+[ 0-9a-f]+: 6480 lw s1,0\(gp\)
+[ 0-9a-f]+: 6481 lw s1,4\(gp\)
+[ 0-9a-f]+: 64be lw s1,248\(gp\)
+[ 0-9a-f]+: 64bf lw s1,252\(gp\)
+[ 0-9a-f]+: fe3c 0100 lw s1,256\(gp\)
+[ 0-9a-f]+: fe3c fefc lw s1,-260\(gp\)
+[ 0-9a-f]+: fe3c 0001 lw s1,1\(gp\)
+[ 0-9a-f]+: fe3c 0002 lw s1,2\(gp\)
+[ 0-9a-f]+: fe3c 0003 lw s1,3\(gp\)
+[ 0-9a-f]+: fe3c ffff lw s1,-1\(gp\)
+[ 0-9a-f]+: fe3c fffe lw s1,-2\(gp\)
+[ 0-9a-f]+: fe3c fffd lw s1,-3\(gp\)
+[ 0-9a-f]+: fe3b 0000 lw s1,0\(k1\)
+[ 0-9a-f]+: 7900 0000 addiu v0,\$pc,0
+[ 0-9a-f]+: 7980 0000 addiu v1,\$pc,0
+[ 0-9a-f]+: 7a00 0000 addiu a0,\$pc,0
+[ 0-9a-f]+: 7a80 0000 addiu a1,\$pc,0
+[ 0-9a-f]+: 7b00 0000 addiu a2,\$pc,0
+[ 0-9a-f]+: 7b80 0000 addiu a3,\$pc,0
+[ 0-9a-f]+: 7800 0000 addiu s0,\$pc,0
+[ 0-9a-f]+: 7880 0000 addiu s1,\$pc,0
+[ 0-9a-f]+: 78bf ffff addiu s1,\$pc,16777212
+[ 0-9a-f]+: 78c0 0000 addiu s1,\$pc,-16777216
+[ 0-9a-f]+: 7900 0000 addiu v0,\$pc,0
+[ 0-9a-f]+: 7980 0000 addiu v1,\$pc,0
+[ 0-9a-f]+: 7a00 0000 addiu a0,\$pc,0
+[ 0-9a-f]+: 7a80 0000 addiu a1,\$pc,0
+[ 0-9a-f]+: 7b00 0000 addiu a2,\$pc,0
+[ 0-9a-f]+: 7b80 0000 addiu a3,\$pc,0
+[ 0-9a-f]+: 7800 0000 addiu s0,\$pc,0
+[ 0-9a-f]+: 7880 0000 addiu s1,\$pc,0
+[ 0-9a-f]+: 78bf ffff addiu s1,\$pc,16777212
+[ 0-9a-f]+: 78c0 0000 addiu s1,\$pc,-16777216
+
+[0-9a-f]+ <test_spec107>:
+[ 0-9a-f]+: 8400 movep a1,a2,zero,zero
+[ 0-9a-f]+: 8480 movep a1,a3,zero,zero
+[ 0-9a-f]+: 8500 movep a2,a3,zero,zero
+[ 0-9a-f]+: 8580 movep a0,s5,zero,zero
+[ 0-9a-f]+: 8600 movep a0,s6,zero,zero
+[ 0-9a-f]+: 8680 movep a0,a1,zero,zero
+[ 0-9a-f]+: 8700 movep a0,a2,zero,zero
+[ 0-9a-f]+: 8780 movep a0,a3,zero,zero
+[ 0-9a-f]+: 8782 movep a0,a3,s1,zero
+[ 0-9a-f]+: 8784 movep a0,a3,v0,zero
+[ 0-9a-f]+: 8786 movep a0,a3,v1,zero
+[ 0-9a-f]+: 8788 movep a0,a3,s0,zero
+[ 0-9a-f]+: 878a movep a0,a3,s2,zero
+[ 0-9a-f]+: 878c movep a0,a3,s3,zero
+[ 0-9a-f]+: 878e movep a0,a3,s4,zero
+[ 0-9a-f]+: 879e movep a0,a3,s4,s1
+[ 0-9a-f]+: 87ae movep a0,a3,s4,v0
+[ 0-9a-f]+: 87be movep a0,a3,s4,v1
+[ 0-9a-f]+: 87ce movep a0,a3,s4,s0
+[ 0-9a-f]+: 87de movep a0,a3,s4,s2
+[ 0-9a-f]+: 87ee movep a0,a3,s4,s3
+[ 0-9a-f]+: 87fe movep a0,a3,s4,s4
+[ 0-9a-f]+: 4260 fffe bals [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4262 fffe bgezals v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4222 fffe bltzals v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0c00 nop
+[ 0-9a-f]+: 4060 fffe bal [0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4062 fffe bgezal v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 4022 fffe bltzal v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
+[ 0-9a-f]+: 0000 0000 nop
+#pass
--- /dev/null
+.*: Assembler messages:
+.*:560: Warning: Divide by zero.
+.*:563: Warning: Divide by zero.
+.*:576: Warning: Divide by zero.
+.*:1541: Warning: Divide by zero.
+.*:1544: Warning: Divide by zero.
+.*:1557: Warning: Divide by zero.
+.*:2604: Warning: Branch bge is always true
+.*:2607: Warning: Branch bgeu is always true
+.*:2616: Warning: Branch bgeu is always true
+.*:2691: Warning: Branch ble is always true
+.*:2706: Warning: Branch bleu is always true
+.*:2712: Warning: Branch bleu is always true
+.*:2715: Warning: Branch bleu is always true
+.*:2814: Warning: Branch bgel is always true
+.*:2817: Warning: Branch bgeul is always true
+.*:2826: Warning: Branch bgeul is always true
+.*:2901: Warning: Branch blel is always true
+.*:2916: Warning: Branch bleul is always true
+.*:2922: Warning: Branch bleul is always true
+.*:2925: Warning: Branch bleul is always true
+.*:4739: Warning: Divide by zero.
+.*:4742: Warning: Divide by zero.
+.*:4755: Warning: Divide by zero.
+.*:5160: Warning: Divide by zero.
+.*:5170: Warning: Divide by zero.
+.*:5180: Warning: Divide by zero.
--- /dev/null
+ .text
+ .align 3
+ .set micromips
+ .ent test
+ .globl test
+test:
+ pref 0, 0
+ pref 0, 2047
+ pref 0, -2048
+ pref 0, 2048
+ pref 0, -2049
+ pref 0, ($0)
+ pref 0, 0($0)
+ pref 1, 0($0)
+ pref 2, 0($0)
+ pref 3, 0($0)
+ pref 4, 0($0)
+ pref 5, 0($0)
+ pref 6, 0($0)
+ pref 7, 0($0)
+ pref 7, 511($0)
+ pref 7, -512($0)
+ pref 31, 2047($0)
+ pref 31, -2048($0)
+ pref 31, 2048($0)
+ pref 31, -2049($0)
+ pref 3, 32767($0)
+ pref 3, -32768($0)
+
+ pref 31, 2047($2)
+ pref 31, -2048($2)
+ pref 31, 2048($2)
+ pref 31, -2049($2)
+ pref 3, 32767($2)
+ pref 3, -32768($2)
+
+ nop
+ nop16
+ nop32
+ ssnop
+ ehb
+ pause
+
+ li $2, -1
+ li $3, -1
+ li $4, -1
+ li $5, -1
+ li $6, -1
+ li $7, -1
+ li $16, -1
+ li $17, -1
+ li $17, 0
+ li $17, 125
+ li $17, 126
+ li $17, 127
+
+ li32 $2, 0
+ li32 $2, 1
+ li $2, 32767
+ li $2, -32768
+ li $2, 65535
+
+ li $2, 65536
+ li $2, 0xffff8000
+ li $2, 0xffff8001
+ li $2, 0xffffffff
+ li $2, 0x12345678
+
+ move $0, $22
+ move $2, $22
+ move $3, $22
+ move $4, $22
+ move $5, $22
+ move $6, $22
+ move $7, $22
+ move $8, $22
+ move $9, $22
+ move $10, $22
+ move $30, $22
+ move $31, $22
+ move $0, $0
+ move $0, $2
+ move $0, $3
+ move $0, $4
+ move $0, $5
+ move $0, $6
+ move $0, $7
+ move $0, $8
+ move $0, $9
+ move $0, $10
+ move $0, $30
+ move $0, $31
+
+ move $22, $2
+ move16 $2, $22
+ move16 $22, $2
+ move32 $2, $22
+ move32 $22, $2
+
+ b test
+ b16 test
+ b32 test
+ b 1f
+ b16 1f
+ b32 1f
+1:
+ b 1b
+ b16 1b
+ b32 1b
+
+ abs $2, $3
+ abs $2, $4
+ abs $2, $2
+ abs $2
+
+ add $2, $3, $4
+ add $29, $30, $31
+ add $2, $2, $4
+ add $2, $4
+ add $2, $2, 0
+ add $2, $2, 1
+ add $2, $2, 32767
+ add $2, $2, -32768
+ add $2, $2, 65535
+
+ addi $3, $4, -32768
+ addi $3, $4, 0
+ addi $3, $4, 32767
+ addi $3, $4, 65535
+ addi $3, $3, 65535
+ addi $3, 65535
+
+ addiu $0, -8
+ addiu $2, -8
+ addiu $3, -8
+ addiu $4, -8
+ addiu $5, -8
+ addiu $6, -8
+ addiu $7, -8
+ addiu $8, -8
+ addiu $9, -8
+ addiu $10, -8
+ addiu $30, -8
+ addiu $31, -8
+ addiu $31, -7
+ addiu $31, 0
+ addiu $31, 1
+ addiu $31, 6
+ addiu $31, 7
+ addiu $31, 8
+ addiu $29, -258 << 2
+ addiu $29, -257 << 2
+ addiu $29, -256 << 2
+ addiu $29, 255 << 2
+ addiu $29, 256 << 2
+ addiu $29, 257 << 2
+ addiu $29, $29, 257 << 2
+ addiu $29, $29, 258 << 2
+
+ addiu $2, $2, -1
+ addiu $2, $3, -1
+ addiu $2, $4, -1
+ addiu $2, $5, -1
+ addiu $2, $6, -1
+ addiu $2, $7, -1
+ addiu $2, $16, -1
+ addiu $2, $17, -1
+ addiu $2, $17, 1
+ addiu $2, $17, 4
+ addiu $2, $17, 8
+ addiu $2, $17, 12
+ addiu $2, $17, 16
+ addiu $2, $17, 20
+ addiu $2, $17, 24
+ addiu $3, $17, 24
+ addiu $4, $17, 24
+ addiu $5, $17, 24
+ addiu $6, $17, 24
+ addiu $7, $17, 24
+ addiu $16, $17, 24
+ addiu $17, $17, 24
+
+ addiu $2, $29, 0 << 2
+ addiu $2, $29, 1 << 2
+ addiu $2, $29, 62 << 2
+ addiu $2, $29, 63 << 2
+ addiu $2, $29, 64 << 2
+ addiu $2, $29, 63 << 2
+ addiu $3, $29, 63 << 2
+ addiu $4, $29, 63 << 2
+ addiu $5, $29, 63 << 2
+ addiu $6, $29, 63 << 2
+ addiu $7, $29, 63 << 2
+ addiu $16, $29, 63 << 2
+ addiu $17, $29, 63 << 2
+
+ addiu $3, $4, -32768
+ addiu $3, $4, 0
+ addiu $3, $4, 32767
+ addiu $3, $4, 65535
+ addiu $3, $3, 65535
+ addiu $3, 65535
+
+ addu $2, $22, $0
+ addu $22, $2, $0
+ addu $2, $0, $22
+ addu $22, $0, $2
+
+ addu $2, $3, $2
+ addu $2, $3, $3
+ addu $2, $3, $4
+ addu $2, $3, $5
+ addu $2, $3, $6
+ addu $2, $3, $7
+ addu $2, $3, $16
+ addu $2, $3, $17
+
+ addu $2, $2, $17
+ addu $2, $3, $17
+ addu $2, $4, $17
+ addu $2, $5, $17
+ addu $2, $6, $17
+ addu $2, $7, $17
+ addu $2, $16, $17
+ addu $2, $17, $17
+
+ addu $2, $2, $17
+ addu $3, $2, $17
+ addu $4, $2, $17
+ addu $5, $2, $17
+ addu $6, $2, $17
+ addu $7, $2, $17
+ addu $16, $2, $17
+ addu $17, $2, $17
+
+ addu $7, $7, $2
+ addu $7, $2
+ addu $7, $2, $7
+
+ addu $29, $30, $31
+ addu $2, $2, 0
+ addu $2, $2, 1
+ addu $2, $2, 32767
+ addu $2, $2, -32768
+ addu $2, $2, 65535
+
+ and $2, $2
+ and $2, $3
+ and $2, $4
+ and $2, $5
+ and $2, $6
+ and $2, $7
+ and $2, $16
+ and $2, $17
+ and $3, $2
+ and $4, $2
+ and $5, $2
+ and $6, $2
+ and $7, $2
+ and $16, $2
+ and $17, $2
+
+ and $2, $3
+ and $2, $2, $3
+ and $2, $3, $2
+ and16 $2, $2, $3
+ and32 $2, $2, $3
+
+ andi $2,$2,1
+ andi $2,$2,2
+ andi $2,$2,3
+ andi $2,$2,4
+ andi $2,$2,7
+ andi $2,$2,8
+ andi $2,$2,15
+ andi $2,$2,16
+ andi $2,$2,31
+ andi $2,$2,32
+ andi $2,$2,63
+ andi $2,$2,64
+ andi $2,$2,128
+ andi $2,$2,255
+ andi $2,$2,32768
+ andi $2,$2,65535
+ andi $2,$3,65535
+ andi $2,$4,65535
+ andi $2,$5,65535
+ andi $2,$6,65535
+ andi $2,$7,65535
+ andi $2,$16,65535
+ andi $2,$17,65535
+ andi $3,$17,65535
+ andi $4,$17,65535
+ andi $5,$17,65535
+ andi $6,$17,65535
+ andi $7,$17,65535
+ andi $16,$17,65535
+ andi $17,$17,65535
+
+ andi $7,$7,65535
+ andi $7,65535
+ andi16 $7,65535
+ andi32 $7,65535
+
+ and32 $2, $3, $4
+ and32 $2, $2, $4
+ and32 $2, $4
+ and $2, $3, 0
+ and $2, $3, 65535
+ and $2, $3, 65536
+ and $2, $3, 0xffff0001
+
+ bc2f test
+ bc2f $cc0, test
+ bc2f $cc1, test
+ bc2f $cc2, test
+ bc2f $cc3, test
+ bc2f $cc4, test
+ bc2f $cc5, test
+ bc2f $cc6, test
+ bc2f $cc7, test
+
+ bc2t test
+ bc2t $cc0, test
+ bc2t $cc1, test
+ bc2t $cc2, test
+ bc2t $cc3, test
+ bc2t $cc4, test
+ bc2t $cc5, test
+ bc2t $cc6, test
+ bc2t $cc7, test
+
+ .set noreorder
+ bc2fl $cc1, test
+ addu $3, $4, $5
+ bc2tl $cc2, test
+ addu $6, $7, $8
+ .set reorder
+
+ bc2fl $cc3, test
+ addu $3, $4, $5
+ bc2tl $cc4, test
+ addu $6, $7, $8
+
+
+test2:
+ beqz $2, test2
+ beqz $3, test2
+ beqz $4, test2
+ beqz $5, test2
+ beqz $6, test2
+ beqz $7, test2
+ beqz $16, test2
+ beqz $17, test2
+ beq $2, $0, test2
+ beq $3, $0, test2
+ beq $4, $0, test2
+ beq $5, $0, test2
+ beq $6, $0, test2
+ beq $7, $0, test2
+ beq $16, $0, test2
+ beq $17, $0, test2
+ beq $0, $2, test2
+ beq $0, $3, test2
+ beq $0, $4, test2
+ beq $0, $5, test2
+ beq $0, $6, test2
+ beq $0, $7, test2
+ beq $0, $16, test2
+ beq $0, $17, test2
+
+ beqz16 $16, test2
+ beqz32 $16, test2
+ beqz $17, test2
+ beqz32 $17, test2
+
+ beqzc $17, test2
+
+ beq $16, 0, test2
+ beq $16, 10, test2
+ beq $16, 32767, test2
+ beq $16, 65536, test2
+
+ .set noreorder
+ beql $16, $17, test2
+ addu $3, $4, $5
+ beql $16, $17, 1f
+ addu $3, $4, $5
+ beql $16, 0, test2
+ addu $3, $4, $5
+ beql $16, 0, 1f
+ addu $3, $4, $5
+ beql $16, 10, test2
+ addu $3, $4, $5
+ beql $16, 10, 1f
+ addu $3, $4, $5
+ beql $16, 32767, test2
+ addu $3, $4, $5
+ beql $16, 32767, 1f
+ addu $3, $4, $5
+ beql $16, 65535, test2
+ addu $3, $4, $5
+ beql $16, 65535, 1f
+ addu $3, $4, $5
+
+ beql $16, $17, test2
+ addu $3, $4, $29
+ beql $16, $17, 1f
+ addu $3, $4, $29
+ beql $16, 0, test2
+ addu $3, $4, $29
+ beql $16, 0, 1f
+ addu $3, $4, $29
+ beql $16, 10, test2
+ addu $3, $4, $29
+ beql $16, 10, 1f
+ addu $3, $4, $29
+ beql $16, 32767, test2
+ addu $3, $4, $29
+ beql $16, 32767, 1f
+ addu $3, $4, $29
+ beql $16, 65535, test2
+ addu $3, $4, $29
+ beql $16, 65535, 1f
+ addu $3, $4, $29
+1:
+ .set reorder
+
+ beql $16, $17, test2
+
+ beqzl $17, test2
+
+ bnez $2, test3
+ bnez $3, test3
+ bnez $4, test3
+ bnez $5, test3
+ bnez $6, test3
+ bnez $7, test3
+ bnez $16, test3
+ bnez $17, test3
+ bne $2, $0, test3
+ bne $3, $0, test3
+ bne $4, $0, test3
+ bne $5, $0, test3
+ bne $6, $0, test3
+ bne $7, $0, test3
+ bne $16, $0, test3
+ bne $17, $0, test3
+ bne $0, $2, test3
+ bne $0, $3, test3
+ bne $0, $4, test3
+ bne $0, $5, test3
+ bne $0, $6, test3
+ bne $0, $7, test3
+ bne $0, $16, test3
+ bne $0, $17, test3
+
+ bnez16 $16, test3
+ bnez32 $16, test3
+ bnez $17, test2
+ bnez32 $17, test2
+test3:
+ bnezc $17, test2
+
+ break
+ break 0
+ break 1
+ break 2
+ break 3
+ break 4
+ break 5
+ break 6
+ break 7
+ break 8
+ break 9
+ break 10
+ break 11
+ break 12
+ break 13
+ break 14
+ break 15
+ break 63
+ break 64
+ break 1023
+ break 1023,1023
+
+ break32
+ break32 0
+ break32 1
+ break32 2
+ break32 15
+ break32 63
+ break32 64
+ break32 1023
+ break32 1023,1023
+
+ cache 0, 0
+ cache 0, -2048
+ cache 0, 2047
+ cache 0, -2049
+ cache 0, 2048
+ cache 0, 0($2)
+ cache 0, -2048($2)
+ cache 0, 2047($2)
+ cache 0, -2049($2)
+ cache 0, 2048($2)
+
+ cache 0, ($0)
+ cache 0, 0($0)
+ cache 1, 0($0)
+ cache 2, 0($0)
+ cache 3, 0($0)
+ cache 4, 0($0)
+ cache 5, 0($0)
+ cache 6, 0($0)
+ cache 31, 0($0)
+ cache 31, 2047($0)
+ cache 31, -2048($0)
+ cache 0, 2047($0)
+ cache 0, -2048($0)
+
+ cache 31, 65536($3)
+ cache 31, 2048($3)
+ cache 31, -2049($3)
+ cache 31, 65537($3)
+ cache 31, 0xffffffff($3)
+ cache 31, 0xffff0000($3)
+ cache 31, 0xffff0001($3)
+ cache 31, 0xffff($3)
+
+ cache 31, 65536($0)
+ cache 31, 2048($0)
+ cache 31, -2049($0)
+ cache 31, 65537($0)
+ cache 31, 0xffffffff($0)
+ cache 31, 0xffff0000($0)
+ cache 31, 0xffff0001($0)
+ cache 31, 0xffff($0)
+
+
+ clo $2, $3
+ clo $3, $2
+ clz $2, $3
+ clz $3, $2
+
+ deret
+
+ di
+ di $0
+ di $2
+ di $3
+ di $30
+ di $31
+
+ div $0, $2, $3
+ div $0, $30, $31
+ div $0, $3
+ div $0, $31
+
+ div $2, $3, $0
+ div $2, $3, $4
+
+ div $3, $4, 0
+ div $3, $4, 1
+ div $3, $4, -1
+ div $3, $4, 2
+
+ divu $0, $2, $3
+ divu $0, $30, $31
+ divu $0, $3
+ divu $0, $31
+
+ divu $2, $3, $0
+ divu $2, $3, $4
+
+ divu $3, $4, 0
+ divu $3, $4, 1
+ divu $3, $4, -1
+ divu $3, $4, 2
+
+ ei
+ ei $0
+ ei $2
+ ei $3
+ ei $30
+ ei $31
+
+ eret
+
+ ext $2, $3, 5, 15
+ ext $2, $3, 0, 32
+ ext $2, $3, 31, 1
+ ext $31, $30, 31, 1
+
+ ins $2, $3, 5, 15
+ ins $2, $3, 0, 32
+ ins $2, $3, 31, 1
+ ins $31, $30, 31, 1
+
+ jr $0
+ jr $2
+ jr $3
+ jr $4
+ jr $5
+ jr $6
+ jr $7
+ jr $8
+ jr $30
+ jr $31
+
+ jr32 $0
+ jr32 $2
+ jr32 $3
+ jr32 $4
+ jr32 $5
+ jr32 $6
+ jr32 $7
+ jr32 $8
+ jr32 $30
+ jr32 $31
+
+ jrc $0
+ jrc $2
+ jrc $3
+ jrc $4
+ jrc $5
+ jrc $6
+ jrc $7
+ jrc $8
+ jrc $30
+ jrc $31
+
+ jr.hb $0
+ jr.hb $2
+ jr.hb $3
+ jr.hb $4
+ jr.hb $5
+ jr.hb $6
+ jr.hb $7
+ jr.hb $8
+ jr.hb $30
+ jr.hb $31
+
+ j $0
+ j $2
+ j $3
+ j $4
+ j $5
+ j $6
+ j $7
+ j $8
+ j $30
+ j $31
+
+ jalr $31, $0
+ jalr $2
+ jalr $3
+ jalr $4
+ jalr $5
+ jalr $6
+ jalr $7
+ jalr $8
+ jalr $30
+
+ jalr32 $31, $0
+ jalr32 $2
+ jalr32 $3
+ jalr32 $4
+ jalr32 $5
+ jalr32 $6
+ jalr32 $7
+ jalr32 $8
+ jalr32 $30
+
+ jalr $31, $0
+ jalr $31, $2
+ jalr $31, $3
+ jalr $31, $4
+ jalr $31, $5
+ jalr $31, $6
+ jalr $31, $7
+ jalr $31, $8
+ jalr $31, $30
+ jalr $30, $31
+
+ jalr $2, $0
+ jalr $3, $2
+ jalr $2, $3
+ jalr $2, $4
+ jalr $2, $5
+ jalr $2, $6
+ jalr $2, $7
+ jalr $2, $8
+ jalr $2, $30
+ jalr $2, $31
+
+ jalr.hb $31, $0
+ jalr.hb $2
+ jalr.hb $3
+ jalr.hb $4
+ jalr.hb $5
+ jalr.hb $6
+ jalr.hb $7
+ jalr.hb $8
+ jalr.hb $30
+ #jalr.hb $31
+
+ jalr.hb $31, $0
+ jalr.hb $31, $2
+ jalr.hb $31, $3
+ jalr.hb $31, $4
+ jalr.hb $31, $5
+ jalr.hb $31, $6
+ jalr.hb $31, $7
+ jalr.hb $31, $8
+ jalr.hb $31, $30
+ jalr.hb $30, $31
+
+ jalr.hb $2, $0
+ jalr.hb $3, $2
+ jalr.hb $2, $3
+ jalr.hb $2, $4
+ jalr.hb $2, $5
+ jalr.hb $2, $6
+ jalr.hb $2, $7
+ jalr.hb $2, $8
+ jalr.hb $2, $30
+ jalr.hb $2, $31
+
+ jal $2, $3
+ jal $30, $31
+
+ jal $3
+ jal $31
+
+ jal test
+ jal test2
+
+ jalx test
+ jalx test2
+
+ la $2, test
+ lca $2, test
+
+ lb $3, 0
+ lb $3, 4
+ lb $3, 0($0)
+ lb $3, 4($0)
+ lb $3, 32767($0)
+ lb $3, -32768($0)
+ lb $3, 65535($0)
+ lb $3, 0xffff0000($0)
+ lb $3, 0xffff8000($0)
+ lb $3, 0xffff0001($0)
+ lb $3, 0xffff8001($0)
+ lb $3, 0xf0000000($0)
+ lb $3, 0xffffffff($0)
+ lb $3, 0x12345678($0)
+ lb $3, ($4)
+ lb $3, 0($4)
+ lb $3, 4($4)
+ lb $3, 32767($4)
+ lb $3, -32768($4)
+ lb $3, 65535($4)
+ lb $3, 0xffff0000($4)
+ lb $3, 0xffff8000($4)
+ lb $3, 0xffff0001($4)
+ lb $3, 0xffff8001($4)
+ lb $3, 0xf0000000($4)
+ lb $3, 0xffffffff($4)
+ lb $3, 0x12345678($4)
+
+ lbu $2, -1($3)
+ lbu $2, 0($3)
+ lbu $2, ($3)
+ lbu $2, 1($3)
+ lbu $2, 2($3)
+ lbu $2, 3($3)
+ lbu $2, 4($3)
+ lbu $2, 5($3)
+ lbu $2, 6($3)
+ lbu $2, 7($3)
+ lbu $2, 8($3)
+ lbu $2, 9($3)
+ lbu $2, 10($3)
+ lbu $2, 11($3)
+ lbu $2, 12($3)
+ lbu $2, 13($3)
+ lbu $2, 14($3)
+ lbu $2, 14($2)
+ lbu $2, 14($4)
+ lbu $2, 14($5)
+ lbu $2, 14($6)
+ lbu $2, 14($7)
+ lbu $2, 14($16)
+ lbu $2, 14($17)
+ lbu $3, 14($17)
+ lbu $4, 14($17)
+ lbu $5, 14($17)
+ lbu $6, 14($17)
+ lbu $7, 14($17)
+ lbu $16, 14($17)
+ lbu $17, 14($17)
+
+ lbu $3, 0
+ lbu $3, 4
+ lbu $3, 0($0)
+ lbu $3, 4($0)
+ lbu $3, 32767($0)
+ lbu $3, -32768($0)
+ lbu $3, 65535($0)
+ lbu $3, 0xffff0000($0)
+ lbu $3, 0xffff8000($0)
+ lbu $3, 0xffff0001($0)
+ lbu $3, 0xffff8001($0)
+ lbu $3, 0xf0000000($0)
+ lbu $3, 0xffffffff($0)
+ lbu $3, 0x12345678($0)
+
+ lbu $3, ($4)
+ lbu $3, 0($4)
+ lbu $3, 4($4)
+ lbu $3, 32767($4)
+ lbu $3, -32768($4)
+ lbu $3, 65535($4)
+ lbu $3, 0xffff0000($4)
+ lbu $3, 0xffff8000($4)
+ lbu $3, 0xffff0001($4)
+ lbu $3, 0xffff8001($4)
+ lbu $3, 0xf0000000($4)
+ lbu $3, 0xffffffff($4)
+ lbu $3, 0x12345678($4)
+
+ lh $3, 0
+ lh $3, 4
+ lh $3, 0($0)
+ lh $3, 4($0)
+ lh $3, 32767($0)
+ lh $3, -32768($0)
+ lh $3, 65535($0)
+ lh $3, 0xffff0000($0)
+ lh $3, 0xffff8000($0)
+ lh $3, 0xffff0001($0)
+ lh $3, 0xffff8001($0)
+ lh $3, 0xf0000000($0)
+ lh $3, 0xffffffff($0)
+ lh $3, 0x12345678($0)
+ lh $3, ($4)
+ lh $3, 0($4)
+ lh $3, 4($4)
+ lh $3, 32767($4)
+ lh $3, -32768($4)
+ lh $3, 65535($4)
+ lh $3, 0xffff0000($4)
+ lh $3, 0xffff8000($4)
+ lh $3, 0xffff0001($4)
+ lh $3, 0xffff8001($4)
+ lh $3, 0xf0000000($4)
+ lh $3, 0xffffffff($4)
+ lh $3, 0x12345678($4)
+
+ lhu $2, ($3)
+ lhu $2, 0<<1($3)
+ lhu $2, 1<<1($3)
+ lhu $2, 2<<1($3)
+ lhu $2, 3<<1($3)
+ lhu $2, 4<<1($3)
+ lhu $2, 5<<1($3)
+ lhu $2, 6<<1($3)
+ lhu $2, 7<<1($3)
+ lhu $2, 8<<1($3)
+ lhu $2, 9<<1($3)
+ lhu $2, 10<<1($3)
+ lhu $2, 11<<1($3)
+ lhu $2, 12<<1($3)
+ lhu $2, 13<<1($3)
+ lhu $2, 14<<1($3)
+ lhu $2, 15<<1($3)
+ lhu $2, 15<<1($4)
+ lhu $2, 15<<1($5)
+ lhu $2, 15<<1($6)
+ lhu $2, 15<<1($7)
+ lhu $2, 15<<1($2)
+ lhu $2, 15<<1($16)
+ lhu $2, 15<<1($17)
+ lhu $3, 15<<1($17)
+ lhu $4, 15<<1($17)
+ lhu $5, 15<<1($17)
+ lhu $6, 15<<1($17)
+ lhu $7, 15<<1($17)
+ lhu $16, 15<<1($17)
+ lhu $17, 15<<1($17)
+
+ lhu $3, 0
+ lhu $3, 4
+ lhu $3, 0($0)
+ lhu $3, 4($0)
+ lhu $3, 32767($0)
+ lhu $3, -32768($0)
+ lhu $3, 65535($0)
+ lhu $3, 0xffff0000($0)
+ lhu $3, 0xffff8000($0)
+ lhu $3, 0xffff0001($0)
+ lhu $3, 0xffff8001($0)
+ lhu $3, 0xf0000000($0)
+ lhu $3, 0xffffffff($0)
+ lhu $3, 0x12345678($0)
+ lhu $3, ($4)
+ lhu $3, 0($4)
+ lhu $3, 4($4)
+ lhu $3, 32767($4)
+ lhu $3, -32768($4)
+ lhu $3, 65535($4)
+ lhu $3, 0xffff0000($4)
+ lhu $3, 0xffff8000($4)
+ lhu $3, 0xffff0001($4)
+ lhu $3, 0xffff8001($4)
+ lhu $3, 0xf0000000($4)
+ lhu $3, 0xffffffff($4)
+ lhu $3, 0x12345678($4)
+
+ ll $3, 0
+ ll $3, 0($0)
+ ll $3, 4
+ ll $3, 4($0)
+ ll $3, 32767($0)
+ ll $3, -32768($0)
+ ll $3, 65535($0)
+ ll $3, 0xffff0000($0)
+ ll $3, 0xffff8000($0)
+ ll $3, 0xffff0001($0)
+ ll $3, 0xffff8001($0)
+ ll $3, 0xf0000000($0)
+ ll $3, 0xffffffff($0)
+ ll $3, 0x12345678($0)
+ ll $3, ($4)
+ ll $3, 0($4)
+ ll $3, 4($4)
+ ll $3, 32767($4)
+ ll $3, -32768($4)
+ ll $3, 65535($4)
+ ll $3, 0xffff0000($4)
+ ll $3, 0xffff8000($4)
+ ll $3, 0xffff0001($4)
+ ll $3, 0xffff8001($4)
+ ll $3, 0xf0000000($4)
+ ll $3, 0xffffffff($4)
+ ll $3, 0x12345678($4)
+
+ lui $3, 0
+ lui $3, 32767
+ lui $3, 65535
+
+ lw $2, ($4)
+ lw $2, 0($4)
+ lw $2, 1<<2($4)
+ lw $2, 2<<2($4)
+ lw $2, 3<<2($4)
+ lw $2, 4<<2($4)
+ lw $2, 5<<2($4)
+ lw $2, 6<<2($4)
+ lw $2, 7<<2($4)
+ lw $2, 8<<2($4)
+ lw $2, 9<<2($4)
+ lw $2, 10<<2($4)
+ lw $2, 11<<2($4)
+ lw $2, 12<<2($4)
+ lw $2, 13<<2($4)
+ lw $2, 14<<2($4)
+ lw $2, 15<<2($4)
+ lw $2, 15<<2($5)
+ lw $2, 15<<2($6)
+ lw $2, 15<<2($7)
+ lw $2, 15<<2($2)
+ lw $2, 15<<2($3)
+ lw $2, 15<<2($16)
+ lw $2, 15<<2($17)
+ lw $3, 15<<2($17)
+ lw $4, 15<<2($17)
+ lw $5, 15<<2($17)
+ lw $6, 15<<2($17)
+ lw $7, 15<<2($17)
+ lw $16, 15<<2($17)
+ lw $17, 15<<2($17)
+
+ lw $4, ($29)
+ lw $4, 0($29)
+ lw $4, 1<<2($29)
+ lw $4, 2<<2($29)
+ lw $4, 3<<2($29)
+ lw $4, 4<<2($29)
+ lw $4, 5<<2($29)
+ lw $4, 31<<2($29)
+ lw $2, 31<<2($29)
+ lw $2, 31<<2($29)
+ lw $3, 31<<2($29)
+ lw $4, 31<<2($29)
+ lw $5, 31<<2($29)
+ lw $6, 31<<2($29)
+ lw $7, 31<<2($29)
+ lw $8, 31<<2($29)
+ lw $9, 31<<2($29)
+ lw $10, 31<<2($29)
+ lw $30, 31<<2($29)
+ lw $31, 31<<2($29)
+
+ lw $4, 126<<2($29)
+ lw $4, 127<<2($29)
+ lw $16, 127<<2($29)
+ lw $17, 127<<2($29)
+ lw $18, 127<<2($29)
+ lw $19, 127<<2($29)
+ lw $20, 127<<2($29)
+ lw $21, 127<<2($29)
+ lw $31, 127<<2($29)
+
+ lw $3, 0
+ lw $3, 4
+ lw $3, ($0)
+ lw $3, 0($0)
+ lw $3, 0($0)
+ lw $3, 4($0)
+ lw $3, 32767($0)
+ lw $3, -32768($0)
+ lw $3, 65535($0)
+ lw $3, 0xffff0000($0)
+ lw $3, 0xffff8000($0)
+ lw $3, 0xffff0001($0)
+ lw $3, 0xffff8001($0)
+ lw $3, 0xf0000000($0)
+ lw $3, 0xffffffff($0)
+ lw $3, 0x12345678($0)
+ lw $3, ($4)
+ lw $3, 0($4)
+ lw $3, 4($4)
+ lw $3, 32767($4)
+ lw $3, -32768($4)
+ lw $3, 65535($4)
+ lw $3, 0xffff0000($4)
+ lw $3, 0xffff8000($4)
+ lw $3, 0xffff0001($4)
+ lw $3, 0xffff8001($4)
+ lw $3, 0xf0000000($4)
+ lw $3, 0xffffffff($4)
+ lw $3, 0x12345678($4)
+
+ lwm $s0, $ra, 12<<2($29)
+ lwm $s0, $s1, $ra, 12<<2($29)
+ lwm $s0-$s1, $ra, 12<<2($29)
+ lwm $s0, $s1, $s2, $ra, 12<<2($29)
+ lwm $s0-$s2, $ra, 12<<2($29)
+ lwm $s0, $s1, $s2, $s3, $ra, 12<<2($29)
+ lwm $s0-$s3, $ra, 12<<2($29)
+ lwm $s0, $ra, ($29)
+ lwm $s0, $ra, 0($29)
+ lwm $s0, $ra, 1<<2($29)
+ lwm $s0, $ra, 2<<2($29)
+ lwm $s0, $ra, 3<<2($29)
+ lwm $s0, $ra, 4<<2($29)
+ lwm $s0, $ra, 5<<2($29)
+ lwm $s0, $ra, 6<<2($29)
+ lwm $s0, $ra, 7<<2($29)
+ lwm $s0, $ra, 8<<2($29)
+ lwm $s0, $ra, 9<<2($29)
+ lwm $s0, $ra, 10<<2($29)
+ lwm $s0, $ra, 11<<2($29)
+ lwm $s0, $ra, 12<<2($29)
+ lwm $s0, $ra, 13<<2($29)
+ lwm $s0, $ra, 14<<2($29)
+ lwm $s0, $ra, 15<<2($29)
+
+ lwm $s0, 0
+ lwm $s0, 4
+ lwm $s0, ($5)
+ lwm $s0, 2047($5)
+ lwm $s0-$s1, 2047($5)
+ lwm $s0-$s2, 2047($5)
+ lwm $s0-$s3, 2047($5)
+ lwm $s0-$s4, 2047($5)
+ lwm $s0-$s5, 2047($5)
+ lwm $s0-$s6, 2047($5)
+ lwm $s0-$s7, 2047($5)
+ lwm $s0-$s8, 2047($5)
+ lwm $ra, 2047($5)
+ lwm $s0,$ra, ($5)
+ lwm $s0-$s1,$ra, ($5)
+ lwm $s0-$s2,$ra, ($5)
+ lwm $s0-$s3,$ra, ($5)
+ lwm $s0-$s4,$ra, ($5)
+ lwm $s0-$s5,$ra, ($5)
+ lwm $s0-$s6,$ra, ($5)
+ lwm $s0-$s7,$ra, ($5)
+ lwm $s0-$s8,$ra, ($5)
+ lwm $s0, -32768($0)
+ lwm $s0, 32767($0)
+ lwm $s0, 0($0)
+ lwm $s0, 65535($0)
+ lwm $s0, -32768($29)
+ lwm $s0, 32767($29)
+ lwm $s0, 0($29)
+ lwm $s0, 65535($29)
+
+ lwp $2, 0
+ lwp $2, 4
+ lwp $2, ($29)
+ lwp $2, 0($29)
+ lwp $2, -2048($3)
+ lwp $2, 2047($3)
+ lwp $2, -32768($3)
+ lwp $2, 32767($3)
+ lwp $2, 0($3)
+ lwp $2, 65535($3)
+ lwp $2, -32768($0)
+ lwp $2, 32767($0)
+ lwp $2, 65535($0)
+
+ lwl $3, 4
+ lwl $3, 4($0)
+ lwl $3, ($0)
+ lwl $3, 0($0)
+ lwl $3, 2047($0)
+ lwl $3, -2048($0)
+ lwl $3, 32767($0)
+ lwl $3, -32768($0)
+ lwl $3, 65535($0)
+ lwl $3, 0xffff0000($0)
+ lwl $3, 0xffff8000($0)
+ lwl $3, 0xffff0001($0)
+ lwl $3, 0xffff8001($0)
+ lwl $3, 0xf0000000($0)
+ lwl $3, 0xffffffff($0)
+ lwl $3, 0x12345678($0)
+ lwl $3, ($4)
+ lwl $3, 0($4)
+ lwl $3, 2047($4)
+ lwl $3, -2048($4)
+ lwl $3, 32767($4)
+ lwl $3, -32768($4)
+ lwl $3, 65535($4)
+ lwl $3, 0xffff0000($4)
+ lwl $3, 0xffff8000($4)
+ lwl $3, 0xffff0001($4)
+ lwl $3, 0xffff8001($4)
+ lwl $3, 0xf0000000($4)
+ lwl $3, 0xffffffff($4)
+ lwl $3, 0x12345678($4)
+
+ lcache $3, 4
+ lcache $3, 4($0)
+ lcache $3, ($0)
+ lcache $3, 0($0)
+ lcache $3, 2047($0)
+ lcache $3, -2048($0)
+ lcache $3, 32767($0)
+ lcache $3, -32768($0)
+ lcache $3, 65535($0)
+ lcache $3, 0xffff0000($0)
+ lcache $3, 0xffff8000($0)
+ lcache $3, 0xffff0001($0)
+ lcache $3, 0xffff8001($0)
+ lcache $3, 0xf0000000($0)
+ lcache $3, 0xffffffff($0)
+ lcache $3, 0x12345678($0)
+ lcache $3, ($4)
+ lcache $3, 0($4)
+ lcache $3, 2047($4)
+ lcache $3, -2048($4)
+ lcache $3, 32767($4)
+ lcache $3, -32768($4)
+ lcache $3, 65535($4)
+ lcache $3, 0xffff0000($4)
+ lcache $3, 0xffff8000($4)
+ lcache $3, 0xffff0001($4)
+ lcache $3, 0xffff8001($4)
+ lcache $3, 0xf0000000($4)
+ lcache $3, 0xffffffff($4)
+ lcache $3, 0x12345678($4)
+
+ lwr $3, 4
+ lwr $3, 4($0)
+ lwr $3, ($0)
+ lwr $3, 0($0)
+ lwr $3, 2047($0)
+ lwr $3, -2048($0)
+ lwr $3, 32767($0)
+ lwr $3, -32768($0)
+ lwr $3, 65535($0)
+ lwr $3, 0xffff0000($0)
+ lwr $3, 0xffff8000($0)
+ lwr $3, 0xffff0001($0)
+ lwr $3, 0xffff8001($0)
+ lwr $3, 0xf0000000($0)
+ lwr $3, 0xffffffff($0)
+ lwr $3, 0x12345678($0)
+ lwr $3, ($4)
+ lwr $3, 0($4)
+ lwr $3, 2047($4)
+ lwr $3, -2048($4)
+ lwr $3, 32767($4)
+ lwr $3, -32768($4)
+ lwr $3, 65535($4)
+ lwr $3, 0xffff0000($4)
+ lwr $3, 0xffff8000($4)
+ lwr $3, 0xffff0001($4)
+ lwr $3, 0xffff8001($4)
+ lwr $3, 0xf0000000($4)
+ lwr $3, 0xffffffff($4)
+ lwr $3, 0x12345678($4)
+
+ flush $3, 4
+ flush $3, 4($0)
+ flush $3, ($0)
+ flush $3, 0($0)
+ flush $3, 2047($0)
+ flush $3, -2048($0)
+ flush $3, 32767($0)
+ flush $3, -32768($0)
+ flush $3, 65535($0)
+ flush $3, 0xffff0000($0)
+ flush $3, 0xffff8000($0)
+ flush $3, 0xffff0001($0)
+ flush $3, 0xffff8001($0)
+ flush $3, 0xf0000000($0)
+ flush $3, 0xffffffff($0)
+ flush $3, 0x12345678($0)
+ flush $3, ($4)
+ flush $3, 0($4)
+ flush $3, 2047($4)
+ flush $3, -2048($4)
+ flush $3, 32767($4)
+ flush $3, -32768($4)
+ flush $3, 65535($4)
+ flush $3, 0xffff0000($4)
+ flush $3, 0xffff8000($4)
+ flush $3, 0xffff0001($4)
+ flush $3, 0xffff8001($4)
+ flush $3, 0xf0000000($4)
+ flush $3, 0xffffffff($4)
+ flush $3, 0x12345678($4)
+
+ lwxs $3, $4($5)
+ madd $4,$5
+ maddu $4,$5
+
+ mfc0 $2, $0
+ mfc0 $2, $1
+ mfc0 $2, $2
+ mfc0 $2, $3
+ mfc0 $2, $4
+ mfc0 $2, $5
+ mfc0 $2, $6
+ mfc0 $2, $7
+ mfc0 $2, $8
+ mfc0 $2, $9
+ mfc0 $2, $10
+ mfc0 $2, $11
+ mfc0 $2, $12
+ mfc0 $2, $13
+ mfc0 $2, $14
+ mfc0 $2, $15
+ mfc0 $2, $16
+ mfc0 $2, $17
+ mfc0 $2, $18
+ mfc0 $2, $19
+ mfc0 $2, $20
+ mfc0 $2, $21
+ mfc0 $2, $22
+ mfc0 $2, $23
+ mfc0 $2, $24
+ mfc0 $2, $25
+ mfc0 $2, $26
+ mfc0 $2, $27
+ mfc0 $2, $28
+ mfc0 $2, $29
+ mfc0 $2, $30
+ mfc0 $2, $31
+
+ mfc0 $2, $0, 0
+ mfc0 $2, $0, 1
+ mfc0 $2, $0, 2
+ mfc0 $2, $0, 3
+ mfc0 $2, $0, 4
+ mfc0 $2, $0, 5
+ mfc0 $2, $0, 6
+ mfc0 $2, $0, 7
+ mfc0 $2, $1, 0
+ mfc0 $2, $1, 1
+ mfc0 $2, $1, 2
+ mfc0 $2, $1, 3
+ mfc0 $2, $1, 4
+ mfc0 $2, $1, 5
+ mfc0 $2, $1, 6
+ mfc0 $2, $1, 7
+ mfc0 $2, $2, 0
+ mfc0 $2, $2, 1
+ mfc0 $2, $2, 2
+ mfc0 $2, $2, 3
+ mfc0 $2, $2, 4
+ mfc0 $2, $2, 5
+ mfc0 $2, $2, 6
+ mfc0 $2, $2, 7
+
+ mfhi $0
+ mfhi $2
+ mfhi $3
+ mfhi $4
+ mfhi $29
+ mfhi $30
+ mfhi $31
+
+ mfhi32 $0
+ mfhi32 $2
+ mfhi32 $3
+ mfhi32 $4
+ mfhi32 $29
+ mfhi32 $30
+ mfhi32 $31
+
+ mflo $0
+ mflo $2
+ mflo $3
+ mflo $4
+ mflo $29
+ mflo $30
+ mflo $31
+
+ mflo32 $0
+ mflo32 $2
+ mflo32 $3
+ mflo32 $4
+ mflo32 $29
+ mflo32 $30
+ mflo32 $31
+
+ movn $2, $3
+ movn $2, $2, $3
+ movn $2, $3, $4
+
+ movz $2, $3
+ movz $2, $2, $3
+ movz $2, $3, $4
+
+ msub $4,$5
+ msubu $4,$5
+
+ mtc0 $2, $0
+ mtc0 $2, $1
+ mtc0 $2, $2
+ mtc0 $2, $3
+ mtc0 $2, $4
+ mtc0 $2, $5
+ mtc0 $2, $6
+ mtc0 $2, $7
+ mtc0 $2, $8
+ mtc0 $2, $9
+ mtc0 $2, $10
+ mtc0 $2, $11
+ mtc0 $2, $12
+ mtc0 $2, $13
+ mtc0 $2, $14
+ mtc0 $2, $15
+ mtc0 $2, $16
+ mtc0 $2, $17
+ mtc0 $2, $18
+ mtc0 $2, $19
+ mtc0 $2, $20
+ mtc0 $2, $21
+ mtc0 $2, $22
+ mtc0 $2, $23
+ mtc0 $2, $24
+ mtc0 $2, $25
+ mtc0 $2, $26
+ mtc0 $2, $27
+ mtc0 $2, $28
+ mtc0 $2, $29
+ mtc0 $2, $30
+ mtc0 $2, $31
+
+ mtc0 $2, $0, 0
+ mtc0 $2, $0, 1
+ mtc0 $2, $0, 2
+ mtc0 $2, $0, 3
+ mtc0 $2, $0, 4
+ mtc0 $2, $0, 5
+ mtc0 $2, $0, 6
+ mtc0 $2, $0, 7
+ mtc0 $2, $1, 0
+ mtc0 $2, $1, 1
+ mtc0 $2, $1, 2
+ mtc0 $2, $1, 3
+ mtc0 $2, $1, 4
+ mtc0 $2, $1, 5
+ mtc0 $2, $1, 6
+ mtc0 $2, $1, 7
+ mtc0 $2, $2, 0
+ mtc0 $2, $2, 1
+ mtc0 $2, $2, 2
+ mtc0 $2, $2, 3
+ mtc0 $2, $2, 4
+ mtc0 $2, $2, 5
+ mtc0 $2, $2, 6
+ mtc0 $2, $2, 7
+
+ mthi $0
+ mthi $2
+ mthi $3
+ mthi $4
+ mthi $29
+ mthi $30
+ mthi $31
+
+ mtlo $0
+ mtlo $2
+ mtlo $3
+ mtlo $4
+ mtlo $29
+ mtlo $30
+ mtlo $31
+
+ mul $2, $3, $4
+ mul $29, $30, $31
+ mul $2, $2, $4
+ mul $2, $4
+ mul $2, $2, 0
+ mul $2, $2, 1
+ mul $2, $2, 32767
+ mul $2, $2, -32768
+ mul $2, $2, 65535
+
+ mulo $2, $3, $4
+ mulo $2, $3, 4
+ mulou $2, $3, $4
+ mulou $2, $3, 4
+
+ mult $2, $3
+ multu $2, $3
+
+ neg $2, $3
+ neg $2, $2
+ neg $2
+ negu $2, $3
+ negu $2, $2
+ negu $2
+ negu32 $2, $3
+ negu32 $2, $2
+ negu32 $2
+
+ not $2, $2
+ not $2, $2
+ not $2, $3
+ not $2, $4
+ not $2, $5
+ not $2, $6
+ not $2, $7
+ not $2, $16
+ not $2, $17
+ not $3, $17
+ not $4, $17
+ not $5, $17
+ not $6, $17
+ not $7, $17
+ not $16, $17
+ not $17, $17
+
+ nor $2, $7, $0
+ nor $2, $0, $7
+
+ nor32 $2, $3, $4
+ nor32 $29, $30, $31
+ nor32 $2, $2, $4
+ nor32 $2, $4
+
+ nor $2, $3, 32768
+ nor $2, $3, 65535
+ nor $2, $3, 65536
+ nor $2, $3, -32768
+ nor $2, $3, -32769
+
+ or $2, $22, $0
+ or $22, $2, $0
+ or $2, $0, $22
+ or $22, $0, $2
+
+ or $2, $2
+ or $2, $3
+ or $2, $4
+ or $2, $5
+ or $2, $6
+ or $2, $7
+ or $2, $16
+ or $2, $17
+ or $3, $2
+ or $4, $2
+ or $5, $2
+ or $6, $2
+ or $7, $2
+ or $16, $2
+ or $17, $2
+ or $2, $2
+ or $2, $2, $3
+ or $2, $3, $2
+
+ or32 $2, $3, $4
+ or32 $29, $30, $31
+ or32 $2, $2, $4
+ or32 $2, $4
+
+ or $2, $3, 32768
+ or $2, $3, 65535
+ or $2, $3, 65536
+ or $2, $3, -32768
+ or $2, $3, -32769
+
+ ori $3, $4, 0
+ ori $3, $4, 32767
+ ori $3, $4, 65535
+ ori $3, $3, 65535
+ ori $3, 65535
+
+ rdhwr $2, $0
+ rdhwr $2, $1
+ rdhwr $2, $2
+ rdhwr $2, $3
+ rdhwr $2, $4
+ rdhwr $2, $5
+ rdhwr $2, $6
+ rdhwr $2, $7
+ rdhwr $2, $8
+ rdhwr $2, $9
+ rdhwr $2, $10
+
+ rdpgpr $2, $3
+ rdpgpr $2, $2
+ rdpgpr $2
+
+ rem $0, $2, $3
+ rem $0, $30, $31
+ rem $0, $3
+ rem $0, $31
+
+ rem $2, $3, $0
+ rem $2, $3, $4
+
+ rem $3, $4, 0
+ rem $3, $4, 1
+ rem $3, $4, -1
+ rem $3, $4, 2
+
+ remu $0, $2, $3
+ remu $0, $30, $31
+ remu $0, $3
+ remu $0, $31
+
+ remu $2, $3, $0
+ remu $2, $3, $4
+
+ remu $3, $4, 0
+ remu $3, $4, 1
+ remu $3, $4, -1
+ remu $3, $4, 2
+
+ rol $2, $3, $4
+ rol $2, $2, $4
+ rol $2, $3, $3
+ rol $2, $3, $2
+
+ rol $2, $3, 0
+ rol $2, $3, 1
+ rol $2, $3, 31
+ rol $2, $2, 31
+ rol $2, 31
+
+ ror $2, $3, 0
+ ror $2, $3, 1
+ ror $2, $3, 31
+ ror $2, $2, 31
+ ror $2, 31
+
+ ror $2, $3, $4
+ ror $2, $2, $4
+
+ rotr $2, $3, $4
+ rotr $2, $2, $4
+
+ rorv $2, $3, $4
+ rorv $2, $2, $4
+
+ rotrv $2, $3, $4
+ rotrv $2, $2, $4
+
+ sb $0, ($3)
+ sb $0, 0($3)
+ sb $0, 1($3)
+ sb $0, 2($3)
+ sb $0, 3($3)
+ sb $0, 4($3)
+ sb $0, 5($3)
+ sb $0, 6($3)
+ sb $0, 7($3)
+ sb $0, 8($3)
+ sb $0, 9($3)
+ sb $0, 10($3)
+ sb $0, 11($3)
+ sb $0, 12($3)
+ sb $0, 13($3)
+ sb $0, 14($3)
+ sb $0, 15($3)
+ sb $2, 15($3)
+ sb $3, 15($3)
+ sb $4, 15($3)
+ sb $5, 15($3)
+ sb $6, 15($3)
+ sb $7, 15($3)
+ sb $17, 15($3)
+ sb $17, 15($4)
+ sb $17, 15($5)
+ sb $17, 15($6)
+ sb $17, 15($7)
+ sb $17, 15($2)
+ sb $17, 15($16)
+ sb $17, 15($17)
+
+ sb32 $3, 4
+ sb32 $3, 4($0)
+ sb32 $3, 32767($0)
+ sb32 $3, -32768($0)
+ sb $3, 65535($0)
+ sb $3, 0xffff0000($0)
+ sb $3, 0xffff8000($0)
+ sb $3, 0xffff0001($0)
+ sb $3, 0xffff8001($0)
+ sb $3, 0xf0000000($0)
+ sb $3, 0xffffffff($0)
+ sb $3, 0x12345678($0)
+ sb32 $3, ($4)
+ sb32 $3, 0($4)
+ sb32 $3, 32767($4)
+ sb32 $3, -32768($4)
+ sb $3, 65535($4)
+ sb $3, 0xffff0000($4)
+ sb $3, 0xffff8000($4)
+ sb $3, 0xffff0001($4)
+ sb $3, 0xffff8001($4)
+ sb $3, 0xf0000000($4)
+ sb $3, 0xffffffff($4)
+ sb $3, 0x12345678($4)
+
+ sc $3, 4
+ sc $3, 4($0)
+ sc $3, 2047($0)
+ sc $3, -2048($0)
+ sc $3, 32767($0)
+ sc $3, -32768($0)
+ sc $3, 65535($0)
+ sc $3, 0xffff0000($0)
+ sc $3, 0xffff8000($0)
+ sc $3, 0xffff0001($0)
+ sc $3, 0xffff8001($0)
+ sc $3, 0xf0000000($0)
+ sc $3, 0xffffffff($0)
+ sc $3, 0x12345678($0)
+ sc $3, ($4)
+ sc $3, 0($4)
+ sc $3, 2047($4)
+ sc $3, -2048($4)
+ sc $3, 32767($4)
+ sc $3, -32768($4)
+ sc $3, 65535($4)
+ sc $3, 0xffff0000($4)
+ sc $3, 0xffff8000($4)
+ sc $3, 0xffff0001($4)
+ sc $3, 0xffff8001($4)
+ sc $3, 0xf0000000($4)
+ sc $3, 0xffffffff($4)
+ sc $3, 0x12345678($4)
+
+ sdbbp
+ sdbbp 0
+ sdbbp 1
+ sdbbp 2
+ sdbbp 3
+ sdbbp 4
+ sdbbp 5
+ sdbbp 6
+ sdbbp 7
+ sdbbp 8
+ sdbbp 9
+ sdbbp 10
+ sdbbp 11
+ sdbbp 12
+ sdbbp 13
+ sdbbp 14
+ sdbbp 15
+
+ sdbbp32
+ sdbbp32 0
+ sdbbp32 1
+ sdbbp32 2
+ sdbbp32 255
+
+ seb $2, $3
+ seb $2, $2
+ seb $2
+
+ seh $2, $3
+ seh $2, $2
+ seh $2
+
+ seq $2, $3, $4
+ seq $2, $3, $0
+ seq $2, $0, $4
+
+ seq $2, $3, 0
+ seq $2, $3, 1
+ seq $2, $3, -1
+ seq $2, $3, -32769
+
+ sge $2, $3, $4
+ sge $2, $2, $4
+ sge $2, $4
+ sge $2, $3, 0
+ sge $2, $3, -32768
+ sge $2, $3, 0
+ sge $2, $3, 32767
+ sge $2, $3, 65535
+ sge $2, $3, 65536
+ sge $2, $3, -32769
+
+ sgeu $2, $3, $4
+ sgeu $2, $2, $4
+ sgeu $2, $4
+ sgeu $2, $3, 0
+ sgeu $2, $3, -32768
+ sgeu $2, $3, 0
+ sgeu $2, $3, 32767
+ sgeu $2, $3, 65535
+ sgeu $2, $3, 65536
+ sgeu $2, $3, -32769
+
+ sgt $2, $3, $4
+ sgt $2, $2, $4
+ sgt $2, $4
+ sgt $2, $3, 0
+ sgt $2, $3, -32768
+ sgt $2, $3, 0
+ sgt $2, $3, 32767
+ sgt $2, $3, 65535
+ sgt $2, $3, 65536
+ sgt $2, $3, -32769
+
+ sgtu $2, $3, $4
+ sgtu $2, $2, $4
+ sgtu $2, $4
+ sgtu $2, $3, 0
+ sgtu $2, $3, -32768
+ sgtu $2, $3, 0
+ sgtu $2, $3, 32767
+ sgtu $2, $3, 65535
+ sgtu $2, $3, 65536
+ sgtu $2, $3, -32769
+
+ sh $2, ($3)
+ sh $2, 0<<1($3)
+ sh $2, 1<<1($3)
+ sh $2, 2<<1($3)
+ sh $2, 3<<1($3)
+ sh $2, 4<<1($3)
+ sh $2, 5<<1($3)
+ sh $2, 6<<1($3)
+ sh $2, 7<<1($3)
+ sh $2, 8<<1($3)
+ sh $2, 9<<1($3)
+ sh $2, 10<<1($3)
+ sh $2, 11<<1($3)
+ sh $2, 12<<1($3)
+ sh $2, 13<<1($3)
+ sh $2, 14<<1($3)
+ sh $2, 15<<1($3)
+ sh $2, 15<<1($4)
+ sh $2, 15<<1($5)
+ sh $2, 15<<1($6)
+ sh $2, 15<<1($7)
+ sh $2, 15<<1($2)
+ sh $2, 15<<1($16)
+ sh $2, 15<<1($17)
+ sh $3, 15<<1($17)
+ sh $4, 15<<1($17)
+ sh $5, 15<<1($17)
+ sh $6, 15<<1($17)
+ sh $7, 15<<1($17)
+ sh $17, 15<<1($17)
+ sh $0, 15<<1($17)
+
+ sh32 $3, 4
+ sh32 $3, 4($0)
+ sh32 $3, 32767($0)
+ sh32 $3, -32768($0)
+ sh $3, 65535($0)
+ sh $3, 0xffff0000($0)
+ sh $3, 0xffff8000($0)
+ sh $3, 0xffff0001($0)
+ sh $3, 0xffff8001($0)
+ sh $3, 0xf0000000($0)
+ sh $3, 0xffffffff($0)
+ sh $3, 0x12345678($0)
+ sh32 $3, ($4)
+ sh32 $3, 0($4)
+ sh32 $3, 32767($4)
+ sh32 $3, -32768($4)
+ sh $3, 65535($4)
+ sh $3, 0xffff0000($4)
+ sh $3, 0xffff8000($4)
+ sh $3, 0xffff0001($4)
+ sh $3, 0xffff8001($4)
+ sh $3, 0xf0000000($4)
+ sh $3, 0xffffffff($4)
+ sh $3, 0x12345678($4)
+
+ sle $2, $3, $4
+ sle $2, $2, $4
+ sle $2, $4
+ sle $2, $3, 0
+ sle $2, $3, -32768
+ sle $2, $3, 0
+ sle $2, $3, 32767
+ sle $2, $3, 65535
+ sle $2, $3, 65536
+ sle $2, $3, -32769
+
+ sleu $2, $3, $4
+ sleu $2, $2, $4
+ sleu $2, $4
+ sleu $2, $3, 0
+ sleu $2, $3, -32768
+ sleu $2, $3, 0
+ sleu $2, $3, 32767
+ sleu $2, $3, 65535
+ sleu $2, $3, 65536
+ sleu $2, $3, -32769
+
+ sll $2, $2, 1
+ sll $2, $2, 2
+ sll $2, $2, 3
+ sll $2, $2, 4
+ sll $2, $2, 5
+ sll $2, $2, 6
+ sll $2, $2, 7
+ sll $2, $2, 8
+ sll $2, $3, 8
+ sll $2, $4, 8
+ sll $2, $5, 8
+ sll $2, $6, 8
+ sll $2, $7, 8
+ sll $2, $16, 8
+ sll $2, $17, 8
+ sll $3, $2, 8
+ sll $4, $2, 8
+ sll $5, $2, 8
+ sll $6, $2, 8
+ sll $7, $2, 8
+ sll $16, $2, 8
+ sll $17, $2, 8
+ sll $2, $2, 1
+ sll $3, 1
+
+ sllv $2, $3, $4
+ sllv $2, $2, $4
+ sll $2, $2, $4
+ sll $2, $4
+ sll32 $2, $4, 0
+ sll32 $2, $4, 1
+ sll32 $2, $4, 31
+ sll32 $2, $2, 31
+ sll32 $2, 31
+
+ slt $2, $3, $4
+ slt $2, $2, $4
+ slt $2, $4
+ slt $2, $3, 0
+ slt $2, $3, -32768
+ slt $2, $3, 0
+ slt $2, $3, 32767
+ slt $2, $3, 65535
+ slt $2, $3, 65536
+ slt $2, $3, -32769
+
+ slti $3, $4, -32768
+ slti $3, $4, 0
+ slti $3, $4, 32767
+ slti $3, $4, 65535
+ slti $3, $3, 65535
+ slti $3, 65535
+
+ sltiu $3, $4, -32768
+ sltiu $3, $4, 0
+ sltiu $3, $4, 32767
+ sltiu $3, $4, 65535
+ sltiu $3, $3, 65535
+ sltiu $3, 65535
+
+ sltu $2, $3, $4
+ sltu $2, $2, $4
+ sltu $2, $4
+ sltu $2, $3, 0
+ sltu $2, $3, -32768
+ sltu $2, $3, 0
+ sltu $2, $3, 32767
+ sltu $2, $3, 65535
+ sltu $2, $3, 65536
+ sltu $2, $3, -32769
+
+ sne $2, $3, $4
+ sne $2, $0, $4
+ sne $2, $3, $0
+
+ sne $2, $3, 0
+ sne $2, $3, 1
+ sne $2, $3, -1
+ sne $2, $3, -32769
+
+ srav $2, $3, $4
+ srav $2, $2, $4
+ sra $2, $2, $4
+ sra $2, $4
+ sra $2, $4, 0
+ sra $2, $4, 1
+ sra $2, $4, 31
+ sra $2, $2, 31
+ sra $2, 31
+
+ srlv $2, $3, $4
+ srlv $2, $2, $4
+ srl $2, $2, $4
+ srl $2, $4
+ srl $2, $4, 0
+ srl $2, $4, 1
+ srl $2, $4, 31
+ srl $2, $2, 31
+ srl $2, 31
+
+ srl $2, $2, 1
+ srl $2, $2, 2
+ srl $2, $2, 3
+ srl $2, $2, 4
+ srl $2, $2, 5
+ srl $2, $2, 6
+ srl $2, $2, 7
+ srl $2, $2, 8
+ srl $2, $3, 8
+ srl $2, $4, 8
+ srl $2, $5, 8
+ srl $2, $6, 8
+ srl $2, $7, 8
+ srl $2, $16, 8
+ srl $2, $17, 8
+ srl $2, $2, 8
+ srl $3, $2, 8
+ srl $4, $2, 8
+ srl $5, $2, 8
+ srl $6, $2, 8
+ srl $7, $2, 8
+ srl $16, $2, 8
+ srl $17, $2, 8
+ srl $3, $3, 1
+ srl $3, 1
+
+ sub $2, $3, $4
+ sub $29, $30, $31
+ sub $2, $2, $4
+ sub $2, $4
+ sub $2, $2, 0
+ sub $2, $2, 1
+ sub $2, $2, 32767
+ sub $2, $2, -32768
+ sub $2, $2, 65535
+
+ subu $2, $3, $2
+ subu $2, $3, $3
+ subu $2, $3, $4
+ subu $2, $3, $5
+ subu $2, $3, $6
+ subu $2, $3, $7
+ subu $2, $3, $16
+ subu $2, $3, $17
+ subu $2, $2, $17
+ subu $2, $4, $17
+ subu $2, $5, $17
+ subu $2, $6, $17
+ subu $2, $7, $17
+ subu $2, $16, $17
+ subu $2, $17, $17
+ subu $2, $2, $17
+ subu $3, $2, $17
+ subu $4, $2, $17
+ subu $5, $2, $17
+ subu $6, $2, $17
+ subu $7, $2, $17
+ subu $16, $2, $17
+ subu $17, $2, $17
+ subu $7, $7, $2
+ subu $7, $2
+
+ subu32 $2, $3, $4
+ subu32 $29, $30, $31
+ subu32 $2, $2, $4
+ subu32 $2, $4
+ subu $2, $2, 0
+ subu $2, $2, 1
+ subu $2, $2, 32767
+ subu $2, $2, -32768
+ subu $2, $2, 65535
+
+ sw $2, ($4)
+ sw $2, 0($4)
+ sw $2, 1<<2($4)
+ sw $2, 2<<2($4)
+ sw $2, 3<<2($4)
+ sw $2, 4<<2($4)
+ sw $2, 5<<2($4)
+ sw $2, 6<<2($4)
+ sw $2, 7<<2($4)
+ sw $2, 8<<2($4)
+ sw $2, 9<<2($4)
+ sw $2, 10<<2($4)
+ sw $2, 11<<2($4)
+ sw $2, 12<<2($4)
+ sw $2, 13<<2($4)
+ sw $2, 14<<2($4)
+ sw $2, 15<<2($4)
+ sw $2, 15<<2($5)
+ sw $2, 15<<2($6)
+ sw $2, 15<<2($7)
+ sw $2, 15<<2($16)
+ sw $2, 15<<2($17)
+ sw $2, 15<<2($2)
+ sw $2, 15<<2($3)
+ sw $3, 15<<2($3)
+ sw $4, 15<<2($3)
+ sw $5, 15<<2($3)
+ sw $6, 15<<2($3)
+ sw $7, 15<<2($3)
+ sw $17, 15<<2($3)
+ sw $0, 15<<2($3)
+
+ sw $0, ($29)
+ sw $0, 0($29)
+ sw $0, 1<<2($29)
+ sw $0, 2<<2($29)
+ sw $0, 3<<2($29)
+ sw $0, 4<<2($29)
+ sw $0, 5<<2($29)
+ sw $0, 30<<2($29)
+ sw $0, 31<<2($29)
+ sw $2, 31<<2($29)
+ sw $17, 31<<2($29)
+ sw $3, 31<<2($29)
+ sw $4, 31<<2($29)
+ sw $5, 31<<2($29)
+ sw $6, 31<<2($29)
+ sw $7, 31<<2($29)
+ sw $31, 31<<2($29)
+
+ sw32 $3, 4
+ sw32 $3, 4($0)
+ sw32 $3, 32767($0)
+ sw32 $3, -32768($0)
+ sw $3, 65535($0)
+ sw $3, 0xffff0000($0)
+ sw $3, 0xffff8000($0)
+ sw $3, 0xffff0001($0)
+ sw $3, 0xffff8001($0)
+ sw $3, 0xf0000000($0)
+ sw $3, 0xffffffff($0)
+ sw $3, 0x12345678($0)
+ sw32 $3, ($4)
+ sw32 $3, 0($4)
+ sw32 $3, 32767($4)
+ sw32 $3, -32768($4)
+ sw $3, 65535($4)
+ sw $3, 0xffff0000($4)
+ sw $3, 0xffff8000($4)
+ sw $3, 0xffff0001($4)
+ sw $3, 0xffff8001($4)
+ sw $3, 0xf0000000($4)
+ sw $3, 0xffffffff($4)
+ sw $3, 0x12345678($4)
+
+ swl $3, 4
+ swl $3, 4($0)
+ swl $3, 2047($0)
+ swl $3, -2048($0)
+ swl $3, 32767($0)
+ swl $3, -32768($0)
+ swl $3, 65535($0)
+ swl $3, 0xffff0000($0)
+ swl $3, 0xffff8000($0)
+ swl $3, 0xffff0001($0)
+ swl $3, 0xffff8001($0)
+ swl $3, 0xf0000000($0)
+ swl $3, 0xffffffff($0)
+ swl $3, 0x12345678($0)
+ swl $3, ($4)
+ swl $3, 0($4)
+ swl $3, 2047($4)
+ swl $3, -2048($4)
+ swl $3, 32767($4)
+ swl $3, -32768($4)
+ swl $3, 65535($4)
+ swl $3, 0xffff0000($4)
+ swl $3, 0xffff8000($4)
+ swl $3, 0xffff0001($4)
+ swl $3, 0xffff8001($4)
+ swl $3, 0xf0000000($4)
+ swl $3, 0xffffffff($4)
+ swl $3, 0x12345678($4)
+
+ swr $3, 4
+ swr $3, 4($0)
+ swr $3, 2047($0)
+ swr $3, -2048($0)
+ swr $3, 32767($0)
+ swr $3, -32768($0)
+ swr $3, 65535($0)
+ swr $3, 0xffff0000($0)
+ swr $3, 0xffff8000($0)
+ swr $3, 0xffff0001($0)
+ swr $3, 0xffff8001($0)
+ swr $3, 0xf0000000($0)
+ swr $3, 0xffffffff($0)
+ swr $3, 0x12345678($0)
+ swr $3, ($4)
+ swr $3, 0($4)
+ swr $3, 2047($4)
+ swr $3, -2048($4)
+ swr $3, 32767($4)
+ swr $3, -32768($4)
+ swr $3, 65535($4)
+ swr $3, 0xffff0000($4)
+ swr $3, 0xffff8000($4)
+ swr $3, 0xffff0001($4)
+ swr $3, 0xffff8001($4)
+ swr $3, 0xf0000000($4)
+ swr $3, 0xffffffff($4)
+ swr $3, 0x12345678($4)
+
+ scache $3, 4
+ scache $3, 4($0)
+ scache $3, 2047($0)
+ scache $3, -2048($0)
+ scache $3, 32767($0)
+ scache $3, -32768($0)
+ scache $3, 65535($0)
+ scache $3, 0xffff0000($0)
+ scache $3, 0xffff8000($0)
+ scache $3, 0xffff0001($0)
+ scache $3, 0xffff8001($0)
+ scache $3, 0xf0000000($0)
+ scache $3, 0xffffffff($0)
+ scache $3, 0x12345678($0)
+ scache $3, ($4)
+ scache $3, 0($4)
+ scache $3, 2047($4)
+ scache $3, -2048($4)
+ scache $3, 32767($4)
+ scache $3, -32768($4)
+ scache $3, 65535($4)
+ scache $3, 0xffff0000($4)
+ scache $3, 0xffff8000($4)
+ scache $3, 0xffff0001($4)
+ scache $3, 0xffff8001($4)
+ scache $3, 0xf0000000($4)
+ scache $3, 0xffffffff($4)
+ scache $3, 0x12345678($4)
+
+ invalidate $3, 4
+ invalidate $3, 4($0)
+ invalidate $3, 2047($0)
+ invalidate $3, -2048($0)
+ invalidate $3, 32767($0)
+ invalidate $3, -32768($0)
+ invalidate $3, 65535($0)
+ invalidate $3, 0xffff0000($0)
+ invalidate $3, 0xffff8000($0)
+ invalidate $3, 0xffff0001($0)
+ invalidate $3, 0xffff8001($0)
+ invalidate $3, 0xf0000000($0)
+ invalidate $3, 0xffffffff($0)
+ invalidate $3, 0x12345678($0)
+ invalidate $3, ($4)
+ invalidate $3, 0($4)
+ invalidate $3, 2047($4)
+ invalidate $3, -2048($4)
+ invalidate $3, 32767($4)
+ invalidate $3, -32768($4)
+ invalidate $3, 65535($4)
+ invalidate $3, 0xffff0000($4)
+ invalidate $3, 0xffff8000($4)
+ invalidate $3, 0xffff0001($4)
+ invalidate $3, 0xffff8001($4)
+ invalidate $3, 0xf0000000($4)
+ invalidate $3, 0xffffffff($4)
+ invalidate $3, 0x12345678($4)
+
+ swm $s0, $ra, 12<<2($29)
+ swm $s0, $s1, $ra, 12<<2($29)
+ swm $s0-$s1, $ra, 12<<2($29)
+ swm $s0, $s1, $s2, $ra, 12<<2($29)
+ swm $s0-$s2, $ra, 12<<2($29)
+ swm $s0, $s1, $s2, $s3, $ra, 12<<2($29)
+ swm $s0-$s3, $ra, 12<<2($29)
+ swm $s0, $ra, ($29)
+ swm $s0, $ra, 0($29)
+ swm $s0, $ra, 1<<2($29)
+ swm $s0, $ra, 2<<2($29)
+ swm $s0, $ra, 3<<2($29)
+ swm $s0, $ra, 4<<2($29)
+ swm $s0, $ra, 5<<2($29)
+ swm $s0, $ra, 6<<2($29)
+ swm $s0, $ra, 7<<2($29)
+ swm $s0, $ra, 8<<2($29)
+ swm $s0, $ra, 9<<2($29)
+ swm $s0, $ra, 10<<2($29)
+ swm $s0, $ra, 11<<2($29)
+ swm $s0, $ra, 12<<2($29)
+ swm $s0, $ra, 13<<2($29)
+ swm $s0, $ra, 14<<2($29)
+ swm $s0, $ra, 15<<2($29)
+
+ swm $s0, 0
+ swm $s0, 4
+ swm $s0, 2047
+ swm $s0, -2048
+ swm $s0, 2048
+ swm $s0, -2049
+ swm $s0, ($5)
+ swm $s0, 2047($5)
+ swm $s0, -2048($5)
+ swm $s0, 2048($5)
+ swm $s0, -2049($5)
+ swm $s0-$s1, 2047($5)
+ swm $s0-$s2, 2047($5)
+ swm $s0-$s3, 2047($5)
+ swm $s0-$s4, 2047($5)
+ swm $s0-$s5, 2047($5)
+ swm $s0-$s6, 2047($5)
+ swm $s0-$s7, 2047($5)
+ swm $s0-$s8, 2047($5)
+ swm $ra, 2047($5)
+ swm $s0,$ra, ($5)
+ swm $s0-$s1,$ra, ($5)
+ swm $s0-$s2,$ra, ($5)
+ swm $s0-$s3,$ra, ($5)
+ swm $s0-$s4,$ra, ($5)
+ swm $s0-$s5,$ra, ($5)
+ swm $s0-$s6,$ra, ($5)
+ swm $s0-$s7,$ra, ($5)
+ swm $s0-$s8,$ra, ($5)
+ swm $s0, -32768($29)
+ swm $s0, 32767($29)
+ swm $s0, 0($29)
+ swm $s0, 65535($29)
+
+ swp $2, 0
+ swp $2, 4
+ swp $2, 2047
+ swp $2, -2048
+ swp $2, 2048
+ swp $2, -2049
+ swp $2, ($29)
+ swp $2, 0($29)
+ swp $2, 2047($3)
+ swp $2, -2048($3)
+ swp $2, 2048($3)
+ swp $2, -2049($3)
+ swp $2, 32767($3)
+ swp $2, -32768($3)
+ swp $2, 0($3)
+ swp $2, 65535($3)
+
+ sync
+ sync 0
+ sync 1
+ sync 2
+ sync 3
+ sync 4
+ sync 30
+ sync 31
+
+ synci 0
+ synci ($0)
+ synci 0($0)
+ synci 2047($0)
+ synci -2048($0)
+ synci 2048($0)
+ synci -2049($0)
+ synci 32767($0)
+ synci -32768($0)
+ synci 0($2)
+ synci 0($3)
+ synci 2047($3)
+ synci -2048($3)
+ synci 2048($3)
+ synci -2049($3)
+ synci 32767($3)
+ synci -32768($3)
+
+ syscall
+ syscall 0
+ syscall 1
+ syscall 2
+ syscall 255
+
+ teqi $2, 0
+ teqi $2, -32768
+ teqi $2, 32767
+ teqi $2, 65535
+ teq $2, $3
+ teq $3, $2
+ teq $2, $3, 0
+ teq $2, $3, 1
+ teq $2, $3, 15
+ teq $2, 0
+ teq $2, -32768
+ teq $2, 32767
+ teq $2, 65535
+
+ tgei $2, 0
+ tgei $2, -32768
+ tgei $2, 32767
+ tgei $2, 65535
+ tge $2, $3
+ tge $3, $2
+ tge $2, $3, 0
+ tge $2, $3, 1
+ tge $2, $3, 15
+ tge $2, 0
+ tge $2, -32768
+ tge $2, 32767
+ tge $2, 65535
+
+ tgeiu $2, 0
+ tgeiu $2, -32768
+ tgeiu $2, 32767
+ tgeiu $2, 65535
+ tgeu $2, $3
+ tgeu $3, $2
+ tgeu $2, $3, 0
+ tgeu $2, $3, 1
+ tgeu $2, $3, 15
+ tgeu $2, 0
+ tgeu $2, -32768
+ tgeu $2, 32767
+ tgeu $2, 65535
+
+ tlbp
+ tlbr
+ tlbwi
+ tlbwr
+
+ tlti $2, 0
+ tlti $2, -32768
+ tlti $2, 32767
+ tlti $2, 65535
+ tlt $2, $3
+ tlt $3, $2
+ tlt $2, $3, 0
+ tlt $2, $3, 1
+ tlt $2, $3, 15
+ tlt $2, 0
+ tlt $2, -32768
+ tlt $2, 32767
+ tlt $2, 65535
+
+ tltiu $2, 0
+ tltiu $2, -32768
+ tltiu $2, 32767
+ tltiu $2, 65535
+ tltu $2, $3
+ tltu $3, $2
+ tltu $2, $3, 0
+ tltu $2, $3, 1
+ tltu $2, $3, 15
+ tltu $2, 0
+ tltu $2, -32768
+ tltu $2, 32767
+ tltu $2, 65535
+ tltu $2, 65536
+ tltu $2, 0xffffffff
+
+ tnei $2, 0
+ tnei $2, -32768
+ tnei $2, 32767
+ tnei $2, 65535
+ tne $2, $3
+ tne $3, $2
+ tne $2, $3, 0
+ tne $2, $3, 1
+ tne $2, $3, 15
+ tne $2, 0
+ tne $2, -32768
+ tne $2, 32767
+ tne $2, 65535
+ tne $2, 65536
+ tne $2, 0xffffffff
+
+ ulh $3, 4
+ ulh $3, 4($0)
+ ulh $3, ($4)
+ ulh $3, 0($4)
+ ulh $3, 32763($4)
+ ulh $3, -32768($4)
+ ulh $3, 65535($4)
+ ulh $3, 0xffff0000($4)
+ ulh $3, 0xffff8000($4)
+ ulh $3, 0xffff0001($4)
+ ulh $3, 0xffff8001($4)
+ ulh $3, 0xf0000000($4)
+ ulh $3, 0xffffffff($4)
+
+ ulhu $3, 4
+ ulhu $3, 4($0)
+ ulhu $3, ($4)
+ ulhu $3, 0($4)
+ ulhu $3, 32763($4)
+ ulhu $3, -32768($4)
+ ulhu $3, 65535($4)
+ ulhu $3, 0xffff0000($4)
+ ulhu $3, 0xffff8000($4)
+ ulhu $3, 0xffff0001($4)
+ ulhu $3, 0xffff8001($4)
+ ulhu $3, 0xf0000000($4)
+ ulhu $3, 0xffffffff($4)
+
+ ulw $3, 0
+ ulw $3, ($0)
+ ulw $3, 4
+ ulw $3, 4($0)
+ ulw $3, 2047
+ ulw $3, -2048
+ ulw $3, 2048
+ ulw $3, -2049
+ ulw $3, 32763($0)
+ ulw $3, -32768($0)
+ ulw $3, 65535($0)
+ ulw $3, 0xffff0000($0)
+ ulw $3, 0xffff8000($0)
+ ulw $3, 0xffff0001($0)
+ ulw $3, 0xffff8001($0)
+ ulw $3, 0xf0000000($0)
+ ulw $3, 0xffffffff($0)
+ ulw $3, 0x12345678($0)
+ ulw $3, 0($4)
+ ulw $3, 4($4)
+ ulw $3, 2047($4)
+ ulw $3, -2048($4)
+ ulw $3, 2048($4)
+ ulw $3, -2049($4)
+ ulw $3, 32763($4)
+ ulw $3, -32768($4)
+ ulw $3, 65535($4)
+ ulw $3, 0xffff0000($4)
+ ulw $3, 0xffff8000($4)
+ ulw $3, 0xffff0001($4)
+ ulw $3, 0xffff8001($4)
+ ulw $3, 0xf0000000($4)
+ ulw $3, 0xffffffff($4)
+ ulw $3, 0x12345678($4)
+
+ ush $3, 4
+ ush $3, 4($0)
+ ush $3, ($4)
+ ush $3, 0($4)
+ ush $3, 32763($4)
+ ush $3, -32768($4)
+ ush $3, 65535($4)
+ ush $3, 0xffff0000($4)
+ ush $3, 0xffff8000($4)
+ ush $3, 0xffff0001($4)
+ ush $3, 0xffff8001($4)
+ ush $3, 0xf0000000($4)
+ ush $3, 0xffffffff($4)
+
+ usw $3, 0
+ usw $3, ($0)
+ usw $3, 4
+ usw $3, 4($0)
+ usw $3, 2047
+ usw $3, -2048
+ usw $3, 2048
+ usw $3, -2049
+ usw $3, 32763($0)
+ usw $3, -32768($0)
+ usw $3, 65535($0)
+ usw $3, 0xffff0000($0)
+ usw $3, 0xffff8000($0)
+ usw $3, 0xffff0001($0)
+ usw $3, 0xffff8001($0)
+ usw $3, 0xf0000000($0)
+ usw $3, 0xffffffff($0)
+ usw $3, 0x12345678($0)
+ usw $3, 0($4)
+ usw $3, 4($4)
+ usw $3, 2047($4)
+ usw $3, -2048($4)
+ usw $3, 2048($4)
+ usw $3, -2049($4)
+ usw $3, 32763($4)
+ usw $3, -32768($4)
+ usw $3, 65535($4)
+ usw $3, 0xffff0000($4)
+ usw $3, 0xffff8000($4)
+ usw $3, 0xffff0001($4)
+ usw $3, 0xffff8001($4)
+ usw $3, 0xf0000000($4)
+ usw $3, 0xffffffff($4)
+ usw $3, 0x12345678($4)
+
+ wait
+ wait 0
+ wait 1
+ wait 255
+
+ wrpgpr $2, $3
+ wrpgpr $2, $4
+ wrpgpr $2, $2
+ wrpgpr $2
+
+ wsbh $2, $3
+ wsbh $2, $4
+ wsbh $2, $2
+ wsbh $2
+
+ xor $2, $2
+ xor $2, $3
+ xor $2, $4
+ xor $2, $5
+ xor $2, $6
+ xor $2, $7
+ xor $2, $16
+ xor $2, $17
+ xor $3, $17
+ xor $4, $17
+ xor $5, $17
+ xor $6, $17
+ xor $7, $17
+ xor $16, $17
+ xor $17, $17
+ xor $2, $3
+ xor $2, $2, $3
+ xor $2, $3, $2
+
+ xor32 $2, $3, $4
+ xor32 $29, $30, $31
+ xor32 $2, $2, $4
+ xor32 $2, $4
+
+ xor $2, $3, 32768
+ xor $2, $3, 65535
+ xor $2, $3, 65536
+ xor $2, $3, -32768
+ xor $2, $3, -32769
+
+ xori $3, $4, 0
+ xori $3, $4, 32767
+ xori $3, $4, 65535
+ xori $3, $3, 65535
+ xori $3, 65535
+
+ .set noreorder
+
+ beqz $9, test
+ addu $3, $4, $5
+
+ beq $9, $10, test
+ addu $3, $4, $5
+
+ beq $9, 0, test
+ addu $3, $4, $5
+
+ beq $9, 1, test
+ addu $3, $4, $5
+
+ bge $10, $0, test
+ addu $3, $4, $5
+
+ bge $10, $0, test
+ addu $3, $4, $5
+
+ bge $0, $10, test
+ addu $3, $4, $5
+
+ bge $10, $11, test
+ addu $3, $4, $5
+
+ bge $10, 0, test
+ addu $3, $4, $5
+
+ bge $10, 1, test
+ addu $3, $4, $5
+
+ bge $10, 2, test
+ addu $3, $4, $5
+
+ bge $10, 0x80000000, test
+ addu $3, $4, $5
+
+ bgeu $2, $0, test
+ addu $3, $4, $5
+
+ bgeu $0, $2, test
+ addu $3, $4, $5
+
+ bgeu $2, $3, test
+ addu $3, $4, $5
+
+ bgeu $2, 0, test
+ addu $3, $4, $5
+
+ bgeu $2, 1, test
+ addu $3, $4, $5
+
+ bgeu $2, 2, test
+ addu $3, $4, $5
+
+ bgez $2, test
+ addu $3, $4, $5
+
+ bgezal $2, test
+ addu $3, $4, $5
+
+ bgt $2, $0, test
+ addu $3, $4, $5
+
+ bgt $0, $2, test
+ addu $3, $4, $5
+
+ bgt $9, $10, test
+ addu $3, $4, $5
+
+ bgt $9, 0x7fffffff, test
+ addu $3, $4, $5
+
+ bgt $9, -1, test
+ addu $3, $4, $5
+
+ bgt $9, 0, test
+ addu $3, $4, $5
+
+ bgt $9, 1, test
+ addu $3, $4, $5
+
+ bgt $9, 0x80000000, test
+ addu $3, $4, $5
+
+ bgtu $9, $0, test
+ addu $3, $4, $5
+
+ bgtu $0, $9, test
+ addu $3, $4, $5
+
+ bgtu $9, $10, test
+ addu $3, $4, $5
+
+ bgtu $0, 0, test
+ addu $3, $4, $5
+
+ bgtu $9, 0xffffffff, test
+ addu $3, $4, $5
+
+ bgtu $9, -1, test
+ addu $3, $4, $5
+
+ bgtu $9, 0, test
+ addu $3, $4, $5
+
+ bgtu $9, 1, test
+ addu $3, $4, $5
+
+ bgtz $9, test
+ addu $3, $4, $5
+
+ ble $9, $0, test
+ addu $3, $4, $5
+
+ ble $0, $10, test
+ addu $3, $4, $5
+
+ ble $9, $10, test
+ addu $3, $4, $5
+
+ ble $9, 0x7fffffff, test
+ addu $3, $4, $5
+
+ ble $9, -1, test
+ addu $3, $4, $5
+
+ ble $9, 0, test
+ addu $3, $4, $5
+
+ ble $9, 1, test
+ addu $3, $4, $5
+
+ bleu $9, $0, test
+ addu $3, $4, $5
+
+ bleu $0, $10, test
+ addu $3, $4, $5
+
+ bleu $9, $10, test
+ addu $3, $4, $5
+
+ bleu $0, $10, test
+ addu $3, $4, $5
+
+ bleu $9, 0xffffffff, test
+ addu $3, $4, $5
+
+ bleu $9, 0, test
+ addu $3, $4, $5
+
+ bleu $9, 1, test
+ addu $3, $4, $5
+
+ blez $9, test
+ addu $3, $4, $5
+
+ blt $9, $0, test
+ addu $3, $4, $5
+
+ blt $0, $10, test
+ addu $3, $4, $5
+
+ blt $9, $10, test
+ addu $3, $4, $5
+
+ blt $9, 0, test
+ addu $3, $4, $5
+
+ blt $9, 1, test
+ addu $3, $4, $5
+
+ blt $9, 2, test
+ addu $3, $4, $5
+
+ bltu $9, $0, test
+ addu $3, $4, $5
+
+ bltu $0, $10, test
+ addu $3, $4, $5
+
+ bltu $9, $10, test
+ addu $3, $4, $5
+
+ bltu $9, 0, test
+ addu $3, $4, $5
+
+ bltu $9, 1, test
+ addu $3, $4, $5
+
+ bltu $9, 2, test
+ addu $3, $4, $5
+
+ bltz $9, test
+ addu $3, $4, $5
+
+ bltzal $9, test
+ addu $3, $4, $5
+
+ bnez $9, test
+ addu $3, $4, $5
+
+ bne $9, $10, test
+ addu $3, $4, $5
+
+ bne $9, 0, test
+ addu $3, $4, $5
+
+ bne $9, 1, test
+ addu $3, $4, $5
+
+ beqzl $9, test
+ addu $3, $4, $5
+
+ beql $9, $10, test
+ addu $3, $4, $5
+
+ beql $9, 0, test
+ addu $3, $4, $5
+
+ beql $9, 1, test
+ addu $3, $4, $5
+
+ bgel $10, $0, test
+ addu $3, $4, $5
+
+ bgel $10, $0, test
+ addu $3, $4, $5
+
+ bgel $0, $10, test
+ addu $3, $4, $5
+
+ bgel $10, $11, test
+ addu $3, $4, $5
+
+ bgel $10, 0, test
+ addu $3, $4, $5
+
+ bgel $10, 1, test
+ addu $3, $4, $5
+
+ bgel $10, 2, test
+ addu $3, $4, $5
+
+ bgel $10, 0x80000000, test
+ addu $3, $4, $5
+
+ bgeul $2, $0, test
+ addu $3, $4, $5
+
+ bgeul $0, $2, test
+ addu $3, $4, $5
+
+ bgeul $2, $3, test
+ addu $3, $4, $5
+
+ bgeul $2, 0, test
+ addu $3, $4, $5
+
+ bgeul $2, 1, test
+ addu $3, $4, $5
+
+ bgeul $2, 2, test
+ addu $3, $4, $5
+
+ bgezl $2, test
+ addu $3, $4, $5
+
+ bgezall $2, test
+ addu $3, $4, $5
+
+ bgtl $2, $0, test
+ addu $3, $4, $5
+
+ bgtl $0, $2, test
+ addu $3, $4, $5
+
+ bgtl $9, $10, test
+ addu $3, $4, $5
+
+ bgtl $9, 0x7fffffff, test
+ addu $3, $4, $5
+
+ bgtl $9, -1, test
+ addu $3, $4, $5
+
+ bgtl $9, 0, test
+ addu $3, $4, $5
+
+ bgtl $9, 1, test
+ addu $3, $4, $5
+
+ bgtl $9, 0x80000000, test
+ addu $3, $4, $5
+
+ bgtul $9, $0, test
+ addu $3, $4, $5
+
+ bgtul $0, $9, test
+ addu $3, $4, $5
+
+ bgtul $9, $10, test
+ addu $3, $4, $5
+
+ bgtul $0, 0, test
+ addu $3, $4, $5
+
+ bgtul $9, 0xffffffff, test
+ addu $3, $4, $5
+
+ bgtul $9, -1, test
+ addu $3, $4, $5
+
+ bgtul $9, 0, test
+ addu $3, $4, $5
+
+ bgtul $9, 1, test
+ addu $3, $4, $5
+
+ bgtzl $9, test
+ addu $3, $4, $5
+
+ blel $9, $0, test
+ addu $3, $4, $5
+
+ blel $0, $10, test
+ addu $3, $4, $5
+
+ blel $9, $10, test
+ addu $3, $4, $5
+
+ blel $9, 0x7fffffff, test
+ addu $3, $4, $5
+
+ blel $9, -1, test
+ addu $3, $4, $5
+
+ blel $9, 0, test
+ addu $3, $4, $5
+
+ blel $9, 1, test
+ addu $3, $4, $5
+
+ bleul $9, $0, test
+ addu $3, $4, $5
+
+ bleul $0, $10, test
+ addu $3, $4, $5
+
+ bleul $9, $10, test
+ addu $3, $4, $5
+
+ bleul $0, $10, test
+ addu $3, $4, $5
+
+ bleul $9, 0xffffffff, test
+ addu $3, $4, $5
+
+ bleul $9, 0, test
+ addu $3, $4, $5
+
+ bleul $9, 1, test
+ addu $3, $4, $5
+
+ blezl $9, test
+ addu $3, $4, $5
+
+ bltl $9, $0, test
+ addu $3, $4, $5
+
+ bltl $0, $10, test
+ addu $3, $4, $5
+
+ bltl $9, $10, test
+ addu $3, $4, $5
+
+ bltl $9, 0, test
+ addu $3, $4, $5
+
+ bltl $9, 1, test
+ addu $3, $4, $5
+
+ bltl $9, 2, test
+ addu $3, $4, $5
+
+ bltul $9, $0, test
+ addu $3, $4, $5
+
+ bltul $0, $10, test
+ addu $3, $4, $5
+
+ bltul $9, $10, test
+ addu $3, $4, $5
+
+ bltul $9, 0, test
+ addu $3, $4, $5
+
+ bltul $9, 1, test
+ addu $3, $4, $5
+
+ bltul $9, 2, test
+ addu $3, $4, $5
+
+ bltzl $9, test
+ addu $3, $4, $5
+
+ bltzall $9, test
+ addu $3, $4, $5
+
+ bnezl $9, test
+ addu $3, $4, $5
+
+ bnel $9, $10, test
+ addu $3, $4, $5
+
+ bnel $9, 0, test
+ addu $3, $4, $5
+
+ bnel $9, 1, test
+ addu $3, $4, $5
+
+ addiur1sp $2, 0
+ addiur1sp $2, 1<<2
+ addiur1sp $2, 2<<2
+ addiur1sp $2, 3<<2
+ addiur1sp $2, 4<<2
+ addiur1sp $2, 63<<2
+ addiur1sp $3, 63<<2
+ addiur1sp $4, 63<<2
+ addiur1sp $5, 63<<2
+ addiur1sp $6, 63<<2
+ addiur1sp $7, 63<<2
+ addiur1sp $16, 63<<2
+ addiur1sp $17, 63<<2
+
+ addiur2 $2, $2, -1
+ addiur2 $2, $3, -1
+ addiur2 $2, $4, -1
+ addiur2 $2, $5, -1
+ addiur2 $2, $6, -1
+ addiur2 $2, $7, -1
+ addiur2 $2, $16, -1
+ addiur2 $2, $17, -1
+ addiur2 $3, $17, -1
+ addiur2 $4, $17, -1
+ addiur2 $5, $17, -1
+ addiur2 $6, $17, -1
+ addiur2 $7, $17, -1
+ addiur2 $16, $17, -1
+ addiur2 $17, $17, -1
+ addiur2 $17, $17, 1
+ addiur2 $17, $17, 4
+ addiur2 $17, $17, 8
+ addiur2 $17, $17, 12
+ addiur2 $17, $17, 16
+ addiur2 $17, $17, 20
+ addiur2 $17, $17, 24
+
+ addiusp 2 << 2
+ addiusp 3 << 2
+ addiusp 254 << 2
+ addiusp 255 << 2
+ addiusp 256 << 2
+ addiusp 257 << 2
+ addiusp -3 << 2
+ addiusp -4 << 2
+ addiusp -255 << 2
+ addiusp -256 << 2
+ addiusp -257 << 2
+ addiusp -258 << 2
+
+ addius5 $0, 0
+ addius5 $2, 0
+ addius5 $3, 0
+ addius5 $30, 0
+ addius5 $31, 0
+ addius5 $31, 1
+ addius5 $31, 2
+ addius5 $31, 3
+ addius5 $31, 7
+ addius5 $31, -6
+ addius5 $31, -7
+ addius5 $31, -8
+
+ sd $3, 4
+ sd $3, 4($0)
+ sd $3, 32767($0)
+ sd $3, -32768($0)
+ sd $3, 65535($0)
+ sd $3, 0xffff0000($0)
+ sd $3, 0xffff8000($0)
+ sd $3, 0xffff0001($0)
+ sd $3, 0xffff8001($0)
+ sd $3, 0xf0000000($0)
+ sd $3, 0xffffffff($0)
+ sd $3, 0x12345678($0)
+ sd $3, ($4)
+ sd $3, 0($4)
+ sd $3, 32767($4)
+ sd $3, -32768($4)
+ sd $3, 65535($4)
+ sd $3, 0xffff0000($4)
+ sd $3, 0xffff8000($4)
+ sd $3, 0xffff0001($4)
+ sd $3, 0xffff8001($4)
+ sd $3, 0xf0000000($4)
+ sd $3, 0xffffffff($4)
+ sd $3, 0x12345678($4)
+
+ ld $3, 4
+ ld $3, 4($0)
+ ld $3, 32767($0)
+ ld $3, -32768($0)
+ ld $3, 65535($0)
+ ld $3, 0xffff0000($0)
+ ld $3, 0xffff8000($0)
+ ld $3, 0xffff0001($0)
+ ld $3, 0xffff8001($0)
+ ld $3, 0xf0000000($0)
+ ld $3, 0xffffffff($0)
+ ld $3, 0x12345678($0)
+ ld $3, ($4)
+ ld $3, 0($4)
+ ld $3, 32767($4)
+ ld $3, -32768($4)
+ ld $3, 65535($4)
+ ld $3, 0xffff0000($4)
+ ld $3, 0xffff8000($4)
+ ld $3, 0xffff0001($4)
+ ld $3, 0xffff8001($4)
+ ld $3, 0xf0000000($4)
+ ld $3, 0xffffffff($4)
+ ld $3, 0x12345678($4)
+
+ jraddiusp 0 << 2
+ jraddiusp 1 << 2
+ jraddiusp 2 << 2
+ jraddiusp 3 << 2
+ jraddiusp 4 << 2
+ jraddiusp 5 << 2
+ jraddiusp 6 << 2
+ jraddiusp 7 << 2
+ jraddiusp 8 << 2
+ jraddiusp 9 << 2
+ jraddiusp 10 << 2
+ jraddiusp 30 << 2
+ jraddiusp 31 << 2
+
+ ldc2 $3, 0
+ ldc2 $3, ($0)
+ ldc2 $3, 4
+ ldc2 $3, 4($0)
+ ldc2 $3, ($4)
+ ldc2 $3, 0($4)
+ ldc2 $3, 32767($4)
+ ldc2 $3, -32768($4)
+ ldc2 $3, 65535($4)
+ ldc2 $3, 0xffff0000($4)
+ ldc2 $3, 0xffff8000($4)
+ ldc2 $3, 0xffff0001($4)
+ ldc2 $3, 0xffff8001($4)
+ ldc2 $3, 0xf0000000($4)
+ ldc2 $3, 0xffffffff($4)
+ ldc2 $3, 0x12345678($4)
+
+ lwc2 $3, 0
+ lwc2 $3, ($0)
+ lwc2 $3, 4
+ lwc2 $3, 4($0)
+ lwc2 $3, ($4)
+ lwc2 $3, 0($4)
+ lwc2 $3, 32767($4)
+ lwc2 $3, -32768($4)
+ lwc2 $3, 65535($4)
+ lwc2 $3, 0xffff0000($4)
+ lwc2 $3, 0xffff8000($4)
+ lwc2 $3, 0xffff0001($4)
+ lwc2 $3, 0xffff8001($4)
+ lwc2 $3, 0xf0000000($4)
+ lwc2 $3, 0xffffffff($4)
+ lwc2 $3, 0x12345678($4)
+
+ mfc2 $5, $0
+ mfc2 $5, $1
+ mfc2 $5, $2
+ mfc2 $5, $3
+ mfc2 $5, $4
+ mfc2 $5, $5
+ mfc2 $5, $6
+ mfc2 $5, $7
+ mfc2 $5, $8
+ mfc2 $5, $9
+ mfc2 $5, $10
+ mfc2 $5, $11
+ mfc2 $5, $12
+ mfc2 $5, $13
+ mfc2 $5, $14
+ mfc2 $5, $15
+ mfc2 $5, $16
+ mfc2 $5, $17
+ mfc2 $5, $18
+ mfc2 $5, $19
+ mfc2 $5, $20
+ mfc2 $5, $21
+ mfc2 $5, $22
+ mfc2 $5, $23
+ mfc2 $5, $24
+ mfc2 $5, $25
+ mfc2 $5, $26
+ mfc2 $5, $27
+ mfc2 $5, $28
+ mfc2 $5, $29
+ mfc2 $5, $30
+ mfc2 $5, $31
+
+ mfhc2 $5, $0
+ mfhc2 $5, $1
+ mfhc2 $5, $2
+ mfhc2 $5, $3
+ mfhc2 $5, $4
+ mfhc2 $5, $5
+ mfhc2 $5, $6
+ mfhc2 $5, $7
+ mfhc2 $5, $8
+ mfhc2 $5, $9
+ mfhc2 $5, $10
+ mfhc2 $5, $11
+ mfhc2 $5, $12
+ mfhc2 $5, $13
+ mfhc2 $5, $14
+ mfhc2 $5, $15
+ mfhc2 $5, $16
+ mfhc2 $5, $17
+ mfhc2 $5, $18
+ mfhc2 $5, $19
+ mfhc2 $5, $20
+ mfhc2 $5, $21
+ mfhc2 $5, $22
+ mfhc2 $5, $23
+ mfhc2 $5, $24
+ mfhc2 $5, $25
+ mfhc2 $5, $26
+ mfhc2 $5, $27
+ mfhc2 $5, $28
+ mfhc2 $5, $29
+ mfhc2 $5, $30
+ mfhc2 $5, $31
+
+ mtc2 $5, $0
+ mtc2 $5, $1
+ mtc2 $5, $2
+ mtc2 $5, $3
+ mtc2 $5, $4
+ mtc2 $5, $5
+ mtc2 $5, $6
+ mtc2 $5, $7
+ mtc2 $5, $8
+ mtc2 $5, $9
+ mtc2 $5, $10
+ mtc2 $5, $11
+ mtc2 $5, $12
+ mtc2 $5, $13
+ mtc2 $5, $14
+ mtc2 $5, $15
+ mtc2 $5, $16
+ mtc2 $5, $17
+ mtc2 $5, $18
+ mtc2 $5, $19
+ mtc2 $5, $20
+ mtc2 $5, $21
+ mtc2 $5, $22
+ mtc2 $5, $23
+ mtc2 $5, $24
+ mtc2 $5, $25
+ mtc2 $5, $26
+ mtc2 $5, $27
+ mtc2 $5, $28
+ mtc2 $5, $29
+ mtc2 $5, $30
+ mtc2 $5, $31
+
+ mthc2 $5, $0
+ mthc2 $5, $1
+ mthc2 $5, $2
+ mthc2 $5, $3
+ mthc2 $5, $4
+ mthc2 $5, $5
+ mthc2 $5, $6
+ mthc2 $5, $7
+ mthc2 $5, $8
+ mthc2 $5, $9
+ mthc2 $5, $10
+ mthc2 $5, $11
+ mthc2 $5, $12
+ mthc2 $5, $13
+ mthc2 $5, $14
+ mthc2 $5, $15
+ mthc2 $5, $16
+ mthc2 $5, $17
+ mthc2 $5, $18
+ mthc2 $5, $19
+ mthc2 $5, $20
+ mthc2 $5, $21
+ mthc2 $5, $22
+ mthc2 $5, $23
+ mthc2 $5, $24
+ mthc2 $5, $25
+ mthc2 $5, $26
+ mthc2 $5, $27
+ mthc2 $5, $28
+ mthc2 $5, $29
+ mthc2 $5, $30
+ mthc2 $5, $31
+
+ sdc2 $3, 0
+ sdc2 $3, ($0)
+ sdc2 $3, 4
+ sdc2 $3, 4($0)
+ sdc2 $3, ($4)
+ sdc2 $3, 0($4)
+ sdc2 $3, 32767($4)
+ sdc2 $3, -32768($4)
+ sdc2 $3, 65535($4)
+ sdc2 $3, 0xffff0000($4)
+ sdc2 $3, 0xffff8000($4)
+ sdc2 $3, 0xffff0001($4)
+ sdc2 $3, 0xffff8001($4)
+ sdc2 $3, 0xf0000000($4)
+ sdc2 $3, 0xffffffff($4)
+ sdc2 $3, 0x12345678($4)
+
+ swc2 $3, 0
+ swc2 $3, ($0)
+ swc2 $3, 4
+ swc2 $3, 4($0)
+ swc2 $3, ($4)
+ swc2 $3, 0($4)
+ swc2 $3, 32767($4)
+ swc2 $3, -32768($4)
+ swc2 $3, 65535($4)
+ swc2 $3, 0xffff0000($4)
+ swc2 $3, 0xffff8000($4)
+ swc2 $3, 0xffff0001($4)
+ swc2 $3, 0xffff8001($4)
+ swc2 $3, 0xf0000000($4)
+ swc2 $3, 0xffffffff($4)
+ swc2 $3, 0x12345678($4)
+
+ cache 0, %lo(test)($3)
+ lwp $2, %lo(test)($3)
+ swp $2, %lo(test)($3)
+ ll $2, %lo(test)($3)
+ sc $2, %lo(test)($3)
+ lwl $2, %lo(test)($3)
+ lwr $2, %lo(test)($3)
+ swl $2, %lo(test)($3)
+ swr $2, %lo(test)($3)
+ lwm $16, %lo(test)($3)
+ swm $16, %lo(test)($3)
+ lwc2 $16, %lo(test)($3)
+ swc2 $16, %lo(test)($3)
+ lcache $2, %lo(test)($3)
+ flush $2, %lo(test)($3)
+ scache $2, %lo(test)($3)
+ invalidate $2, %lo(test)($3)
+
+ sdbbp 1023
+ wait 1023
+ syscall 1023
+ cop2 0x7fffff
+
+ .end test
+ .set reorder
+
+ .align 3
+ .set micromips
+ .ent fp_test
+ .globl fp_test
+fp_test:
+ prefx 0, $0($0)
+ prefx 0, $0($2)
+ prefx 0, $0($31)
+ prefx 0, $2($31)
+ prefx 0, $31($31)
+ prefx 1, $31($31)
+ prefx 2, $31($31)
+ prefx 31, $31($31)
+
+ abs.s $f0, $f1
+ abs.s $f30, $f31
+ abs.s $f2, $f2
+ abs.s $f2
+ abs.d $f0, $f1
+ abs.d $f30, $f31
+ abs.d $f2, $f2
+ abs.d $f2
+ abs.ps $f0, $f1
+ abs.ps $f30, $f31
+ abs.ps $f2, $f2
+ abs.ps $f2
+
+ add.s $f0, $f1, $f2
+ add.s $f29, $f30, $f31
+ add.s $f29, $f29, $f30
+ add.s $f29, $f30
+ add.d $f0, $f1, $f2
+ add.d $f29, $f30, $f31
+ add.d $f29, $f29, $f30
+ add.d $f29, $f30
+ add.ps $f0, $f1, $f2
+ add.ps $f29, $f30, $f31
+ add.ps $f29, $f29, $f30
+ add.ps $f29, $f30
+
+ alnv.ps $f0, $f1, $f2, $0
+ alnv.ps $f0, $f1, $f2, $2
+ alnv.ps $f0, $f1, $f2, $31
+ alnv.ps $f29, $f30, $f31, $31
+ alnv.ps $f29, $f29, $f31, $31
+
+ bc1f fp_test
+ bc1f $fcc0, fp_test
+ bc1f $fcc1, fp_test
+ bc1f $fcc2, fp_test
+ bc1f $fcc3, fp_test
+ bc1f $fcc4, fp_test
+ bc1f $fcc5, fp_test
+ bc1f $fcc6, fp_test
+ bc1f $fcc7, fp_test
+
+ bc1t fp_test
+ bc1t $fcc0, fp_test
+ bc1t $fcc1, fp_test
+ bc1t $fcc2, fp_test
+ bc1t $fcc3, fp_test
+ bc1t $fcc4, fp_test
+ bc1t $fcc5, fp_test
+ bc1t $fcc6, fp_test
+ bc1t $fcc7, fp_test
+
+ c.f.d $f0, $f1
+ c.f.d $f30, $f31
+ c.f.d $fcc0, $f30, $f31
+ c.f.d $fcc1, $f30, $f31
+ c.f.d $fcc7, $f30, $f31
+ c.f.s $f0, $f1
+ c.f.s $f30, $f31
+ c.f.s $fcc0, $f30, $f31
+ c.f.s $fcc1, $f30, $f31
+ c.f.s $fcc7, $f30, $f31
+ c.f.ps $f0, $f1
+ c.f.ps $f30, $f31
+ c.f.ps $fcc0, $f30, $f31
+ c.f.ps $fcc2, $f30, $f31
+ c.f.ps $fcc6, $f30, $f31
+
+ c.un.d $f0, $f1
+ c.un.d $f30, $f31
+ c.un.d $fcc0, $f30, $f31
+ c.un.d $fcc1, $f30, $f31
+ c.un.d $fcc7, $f30, $f31
+ c.un.s $f0, $f1
+ c.un.s $f30, $f31
+ c.un.s $fcc0, $f30, $f31
+ c.un.s $fcc1, $f30, $f31
+ c.un.s $fcc7, $f30, $f31
+ c.un.ps $f0, $f1
+ c.un.ps $f30, $f31
+ c.un.ps $fcc0, $f30, $f31
+ c.un.ps $fcc2, $f30, $f31
+ c.un.ps $fcc6, $f30, $f31
+
+ c.eq.d $f0, $f1
+ c.eq.d $f30, $f31
+ c.eq.d $fcc0, $f30, $f31
+ c.eq.d $fcc1, $f30, $f31
+ c.eq.d $fcc7, $f30, $f31
+ c.eq.s $f0, $f1
+ c.eq.s $f30, $f31
+ c.eq.s $fcc0, $f30, $f31
+ c.eq.s $fcc1, $f30, $f31
+ c.eq.s $fcc7, $f30, $f31
+ c.eq.ps $f0, $f1
+ c.eq.ps $f30, $f31
+ c.eq.ps $fcc0, $f30, $f31
+ c.eq.ps $fcc2, $f30, $f31
+ c.eq.ps $fcc6, $f30, $f31
+
+ c.ueq.d $f0, $f1
+ c.ueq.d $f30, $f31
+ c.ueq.d $fcc0, $f30, $f31
+ c.ueq.d $fcc1, $f30, $f31
+ c.ueq.d $fcc7, $f30, $f31
+ c.ueq.s $f0, $f1
+ c.ueq.s $f30, $f31
+ c.ueq.s $fcc0, $f30, $f31
+ c.ueq.s $fcc1, $f30, $f31
+ c.ueq.s $fcc7, $f30, $f31
+ c.ueq.ps $f0, $f1
+ c.ueq.ps $f30, $f31
+ c.ueq.ps $fcc0, $f30, $f31
+ c.ueq.ps $fcc2, $f30, $f31
+ c.ueq.ps $fcc6, $f30, $f31
+
+ c.olt.d $f0, $f1
+ c.olt.d $f30, $f31
+ c.olt.d $fcc0, $f30, $f31
+ c.olt.d $fcc1, $f30, $f31
+ c.olt.d $fcc7, $f30, $f31
+ c.olt.s $f0, $f1
+ c.olt.s $f30, $f31
+ c.olt.s $fcc0, $f30, $f31
+ c.olt.s $fcc1, $f30, $f31
+ c.olt.s $fcc7, $f30, $f31
+ c.olt.ps $f0, $f1
+ c.olt.ps $f30, $f31
+ c.olt.ps $fcc0, $f30, $f31
+ c.olt.ps $fcc2, $f30, $f31
+ c.olt.ps $fcc6, $f30, $f31
+
+ c.ult.d $f0, $f1
+ c.ult.d $f30, $f31
+ c.ult.d $fcc0, $f30, $f31
+ c.ult.d $fcc1, $f30, $f31
+ c.ult.d $fcc7, $f30, $f31
+ c.ult.s $f0, $f1
+ c.ult.s $f30, $f31
+ c.ult.s $fcc0, $f30, $f31
+ c.ult.s $fcc1, $f30, $f31
+ c.ult.s $fcc7, $f30, $f31
+ c.ult.ps $f0, $f1
+ c.ult.ps $f30, $f31
+ c.ult.ps $fcc0, $f30, $f31
+ c.ult.ps $fcc2, $f30, $f31
+ c.ult.ps $fcc6, $f30, $f31
+
+ c.ole.d $f0, $f1
+ c.ole.d $f30, $f31
+ c.ole.d $fcc0, $f30, $f31
+ c.ole.d $fcc1, $f30, $f31
+ c.ole.d $fcc7, $f30, $f31
+ c.ole.s $f0, $f1
+ c.ole.s $f30, $f31
+ c.ole.s $fcc0, $f30, $f31
+ c.ole.s $fcc1, $f30, $f31
+ c.ole.s $fcc7, $f30, $f31
+ c.ole.ps $f0, $f1
+ c.ole.ps $f30, $f31
+ c.ole.ps $fcc0, $f30, $f31
+ c.ole.ps $fcc2, $f30, $f31
+ c.ole.ps $fcc6, $f30, $f31
+
+ c.ule.d $f0, $f1
+ c.ule.d $f30, $f31
+ c.ule.d $fcc0, $f30, $f31
+ c.ule.d $fcc1, $f30, $f31
+ c.ule.d $fcc7, $f30, $f31
+ c.ule.s $f0, $f1
+ c.ule.s $f30, $f31
+ c.ule.s $fcc0, $f30, $f31
+ c.ule.s $fcc1, $f30, $f31
+ c.ule.s $fcc7, $f30, $f31
+ c.ule.ps $f0, $f1
+ c.ule.ps $f30, $f31
+ c.ule.ps $fcc0, $f30, $f31
+ c.ule.ps $fcc2, $f30, $f31
+ c.ule.ps $fcc6, $f30, $f31
+
+ c.sf.d $f0, $f1
+ c.sf.d $f30, $f31
+ c.sf.d $fcc0, $f30, $f31
+ c.sf.d $fcc1, $f30, $f31
+ c.sf.d $fcc7, $f30, $f31
+ c.sf.s $f0, $f1
+ c.sf.s $f30, $f31
+ c.sf.s $fcc0, $f30, $f31
+ c.sf.s $fcc1, $f30, $f31
+ c.sf.s $fcc7, $f30, $f31
+ c.sf.ps $f0, $f1
+ c.sf.ps $f30, $f31
+ c.sf.ps $fcc0, $f30, $f31
+ c.sf.ps $fcc2, $f30, $f31
+ c.sf.ps $fcc6, $f30, $f31
+
+ c.ngle.d $f0, $f1
+ c.ngle.d $f30, $f31
+ c.ngle.d $fcc0, $f30, $f31
+ c.ngle.d $fcc1, $f30, $f31
+ c.ngle.d $fcc7, $f30, $f31
+ c.ngle.s $f0, $f1
+ c.ngle.s $f30, $f31
+ c.ngle.s $fcc0, $f30, $f31
+ c.ngle.s $fcc1, $f30, $f31
+ c.ngle.s $fcc7, $f30, $f31
+ c.ngle.ps $f0, $f1
+ c.ngle.ps $f30, $f31
+ c.ngle.ps $fcc0, $f30, $f31
+ c.ngle.ps $fcc2, $f30, $f31
+ c.ngle.ps $fcc6, $f30, $f31
+
+ c.seq.d $f0, $f1
+ c.seq.d $f30, $f31
+ c.seq.d $fcc0, $f30, $f31
+ c.seq.d $fcc1, $f30, $f31
+ c.seq.d $fcc7, $f30, $f31
+ c.seq.s $f0, $f1
+ c.seq.s $f30, $f31
+ c.seq.s $fcc0, $f30, $f31
+ c.seq.s $fcc1, $f30, $f31
+ c.seq.s $fcc7, $f30, $f31
+ c.seq.ps $f0, $f1
+ c.seq.ps $f30, $f31
+ c.seq.ps $fcc0, $f30, $f31
+ c.seq.ps $fcc2, $f30, $f31
+ c.seq.ps $fcc6, $f30, $f31
+
+ c.ngl.d $f0, $f1
+ c.ngl.d $f30, $f31
+ c.ngl.d $fcc0, $f30, $f31
+ c.ngl.d $fcc1, $f30, $f31
+ c.ngl.d $fcc7, $f30, $f31
+ c.ngl.s $f0, $f1
+ c.ngl.s $f30, $f31
+ c.ngl.s $fcc0, $f30, $f31
+ c.ngl.s $fcc1, $f30, $f31
+ c.ngl.s $fcc7, $f30, $f31
+ c.ngl.ps $f0, $f1
+ c.ngl.ps $f30, $f31
+ c.ngl.ps $fcc0, $f30, $f31
+ c.ngl.ps $fcc2, $f30, $f31
+ c.ngl.ps $fcc6, $f30, $f31
+
+ c.lt.d $f0, $f1
+ c.lt.d $f30, $f31
+ c.lt.d $fcc0, $f30, $f31
+ c.lt.d $fcc1, $f30, $f31
+ c.lt.d $fcc7, $f30, $f31
+ c.lt.s $f0, $f1
+ c.lt.s $f30, $f31
+ c.lt.s $fcc0, $f30, $f31
+ c.lt.s $fcc1, $f30, $f31
+ c.lt.s $fcc7, $f30, $f31
+ c.lt.ps $f0, $f1
+ c.lt.ps $f30, $f31
+ c.lt.ps $fcc0, $f30, $f31
+ c.lt.ps $fcc2, $f30, $f31
+ c.lt.ps $fcc6, $f30, $f31
+
+ c.nge.d $f0, $f1
+ c.nge.d $f30, $f31
+ c.nge.d $fcc0, $f30, $f31
+ c.nge.d $fcc1, $f30, $f31
+ c.nge.d $fcc7, $f30, $f31
+ c.nge.s $f0, $f1
+ c.nge.s $f30, $f31
+ c.nge.s $fcc0, $f30, $f31
+ c.nge.s $fcc1, $f30, $f31
+ c.nge.s $fcc7, $f30, $f31
+ c.nge.ps $f0, $f1
+ c.nge.ps $f30, $f31
+ c.nge.ps $fcc0, $f30, $f31
+ c.nge.ps $fcc2, $f30, $f31
+ c.nge.ps $fcc6, $f30, $f31
+
+ c.le.d $f0, $f1
+ c.le.d $f30, $f31
+ c.le.d $fcc0, $f30, $f31
+ c.le.d $fcc1, $f30, $f31
+ c.le.d $fcc7, $f30, $f31
+ c.le.s $f0, $f1
+ c.le.s $f30, $f31
+ c.le.s $fcc0, $f30, $f31
+ c.le.s $fcc1, $f30, $f31
+ c.le.s $fcc7, $f30, $f31
+ c.le.ps $f0, $f1
+ c.le.ps $f30, $f31
+ c.le.ps $fcc0, $f30, $f31
+ c.le.ps $fcc2, $f30, $f31
+ c.le.ps $fcc6, $f30, $f31
+
+ c.ngt.d $f0, $f1
+ c.ngt.d $f30, $f31
+ c.ngt.d $fcc0, $f30, $f31
+ c.ngt.d $fcc1, $f30, $f31
+ c.ngt.d $fcc7, $f30, $f31
+ c.ngt.s $f0, $f1
+ c.ngt.s $f30, $f31
+ c.ngt.s $fcc0, $f30, $f31
+ c.ngt.s $fcc1, $f30, $f31
+ c.ngt.s $fcc7, $f30, $f31
+ c.ngt.ps $f0, $f1
+ c.ngt.ps $f30, $f31
+ c.ngt.ps $fcc0, $f30, $f31
+ c.ngt.ps $fcc2, $f30, $f31
+ c.ngt.ps $fcc6, $f30, $f31
+
+ ceil.l.d $f0, $f1
+ ceil.l.d $f30, $f31
+ ceil.l.d $f2, $f2
+
+ ceil.l.s $f0, $f1
+ ceil.l.s $f30, $f31
+ ceil.l.s $f2, $f2
+
+ ceil.w.d $f0, $f1
+ ceil.w.d $f30, $f31
+ ceil.w.d $f2, $f2
+
+ ceil.w.s $f0, $f1
+ ceil.w.s $f30, $f31
+ ceil.w.s $f2, $f2
+
+ cfc1 $5, $0
+ cfc1 $5, $1
+ cfc1 $5, $2
+ cfc1 $5, $3
+ cfc1 $5, $4
+ cfc1 $5, $5
+ cfc1 $5, $6
+ cfc1 $5, $7
+ cfc1 $5, $8
+ cfc1 $5, $9
+ cfc1 $5, $10
+ cfc1 $5, $11
+ cfc1 $5, $12
+ cfc1 $5, $13
+ cfc1 $5, $14
+ cfc1 $5, $15
+ cfc1 $5, $16
+ cfc1 $5, $17
+ cfc1 $5, $18
+ cfc1 $5, $19
+ cfc1 $5, $20
+ cfc1 $5, $21
+ cfc1 $5, $22
+ cfc1 $5, $23
+ cfc1 $5, $24
+ cfc1 $5, $25
+ cfc1 $5, $26
+ cfc1 $5, $27
+ cfc1 $5, $28
+ cfc1 $5, $29
+ cfc1 $5, $30
+ cfc1 $5, $31
+ cfc1 $5, $f0
+ cfc1 $5, $f1
+ cfc1 $5, $f2
+ cfc1 $5, $f3
+ cfc1 $5, $f4
+ cfc1 $5, $f5
+ cfc1 $5, $f6
+ cfc1 $5, $f7
+ cfc1 $5, $f8
+ cfc1 $5, $f9
+ cfc1 $5, $f10
+ cfc1 $5, $f11
+ cfc1 $5, $f12
+ cfc1 $5, $f13
+ cfc1 $5, $f14
+ cfc1 $5, $f15
+ cfc1 $5, $f16
+ cfc1 $5, $f17
+ cfc1 $5, $f18
+ cfc1 $5, $f19
+ cfc1 $5, $f20
+ cfc1 $5, $f21
+ cfc1 $5, $f22
+ cfc1 $5, $f23
+ cfc1 $5, $f24
+ cfc1 $5, $f25
+ cfc1 $5, $f26
+ cfc1 $5, $f27
+ cfc1 $5, $f28
+ cfc1 $5, $f29
+ cfc1 $5, $f30
+ cfc1 $5, $f31
+
+ cfc2 $5, $0
+ cfc2 $5, $1
+ cfc2 $5, $2
+ cfc2 $5, $3
+ cfc2 $5, $4
+ cfc2 $5, $5
+ cfc2 $5, $6
+ cfc2 $5, $7
+ cfc2 $5, $8
+ cfc2 $5, $9
+ cfc2 $5, $10
+ cfc2 $5, $11
+ cfc2 $5, $12
+ cfc2 $5, $13
+ cfc2 $5, $14
+ cfc2 $5, $15
+ cfc2 $5, $16
+ cfc2 $5, $17
+ cfc2 $5, $18
+ cfc2 $5, $19
+ cfc2 $5, $20
+ cfc2 $5, $21
+ cfc2 $5, $22
+ cfc2 $5, $23
+ cfc2 $5, $24
+ cfc2 $5, $25
+ cfc2 $5, $26
+ cfc2 $5, $27
+ cfc2 $5, $28
+ cfc2 $5, $29
+ cfc2 $5, $30
+ cfc2 $5, $31
+
+ ctc1 $5, $0
+ ctc1 $5, $1
+ ctc1 $5, $2
+ ctc1 $5, $3
+ ctc1 $5, $4
+ ctc1 $5, $5
+ ctc1 $5, $6
+ ctc1 $5, $7
+ ctc1 $5, $8
+ ctc1 $5, $9
+ ctc1 $5, $10
+ ctc1 $5, $11
+ ctc1 $5, $12
+ ctc1 $5, $13
+ ctc1 $5, $14
+ ctc1 $5, $15
+ ctc1 $5, $16
+ ctc1 $5, $17
+ ctc1 $5, $18
+ ctc1 $5, $19
+ ctc1 $5, $20
+ ctc1 $5, $21
+ ctc1 $5, $22
+ ctc1 $5, $23
+ ctc1 $5, $24
+ ctc1 $5, $25
+ ctc1 $5, $26
+ ctc1 $5, $27
+ ctc1 $5, $28
+ ctc1 $5, $29
+ ctc1 $5, $30
+ ctc1 $5, $31
+ ctc1 $5, $f0
+ ctc1 $5, $f1
+ ctc1 $5, $f2
+ ctc1 $5, $f3
+ ctc1 $5, $f4
+ ctc1 $5, $f5
+ ctc1 $5, $f6
+ ctc1 $5, $f7
+ ctc1 $5, $f8
+ ctc1 $5, $f9
+ ctc1 $5, $f10
+ ctc1 $5, $f11
+ ctc1 $5, $f12
+ ctc1 $5, $f13
+ ctc1 $5, $f14
+ ctc1 $5, $f15
+ ctc1 $5, $f16
+ ctc1 $5, $f17
+ ctc1 $5, $f18
+ ctc1 $5, $f19
+ ctc1 $5, $f20
+ ctc1 $5, $f21
+ ctc1 $5, $f22
+ ctc1 $5, $f23
+ ctc1 $5, $f24
+ ctc1 $5, $f25
+ ctc1 $5, $f26
+ ctc1 $5, $f27
+ ctc1 $5, $f28
+ ctc1 $5, $f29
+ ctc1 $5, $f30
+ ctc1 $5, $f31
+
+ ctc2 $5, $0
+ ctc2 $5, $1
+ ctc2 $5, $2
+ ctc2 $5, $3
+ ctc2 $5, $4
+ ctc2 $5, $5
+ ctc2 $5, $6
+ ctc2 $5, $7
+ ctc2 $5, $8
+ ctc2 $5, $9
+ ctc2 $5, $10
+ ctc2 $5, $11
+ ctc2 $5, $12
+ ctc2 $5, $13
+ ctc2 $5, $14
+ ctc2 $5, $15
+ ctc2 $5, $16
+ ctc2 $5, $17
+ ctc2 $5, $18
+ ctc2 $5, $19
+ ctc2 $5, $20
+ ctc2 $5, $21
+ ctc2 $5, $22
+ ctc2 $5, $23
+ ctc2 $5, $24
+ ctc2 $5, $25
+ ctc2 $5, $26
+ ctc2 $5, $27
+ ctc2 $5, $28
+ ctc2 $5, $29
+ ctc2 $5, $30
+ ctc2 $5, $31
+
+ cvt.d.l $f0, $f1
+ cvt.d.l $f30, $f31
+ cvt.d.l $f2, $f2
+
+ cvt.d.s $f0, $f1
+ cvt.d.s $f30, $f31
+ cvt.d.s $f2, $f2
+
+ cvt.d.w $f0, $f1
+ cvt.d.w $f30, $f31
+ cvt.d.w $f2, $f2
+
+ cvt.l.s $f0, $f1
+ cvt.l.s $f30, $f31
+ cvt.l.s $f2, $f2
+
+ cvt.l.d $f0, $f1
+ cvt.l.d $f30, $f31
+ cvt.l.d $f2, $f2
+
+ cvt.s.l $f0, $f1
+ cvt.s.l $f30, $f31
+ cvt.s.l $f2, $f2
+
+ cvt.s.d $f0, $f1
+ cvt.s.d $f30, $f31
+ cvt.s.d $f2, $f2
+
+ cvt.s.w $f0, $f1
+ cvt.s.w $f30, $f31
+ cvt.s.w $f2, $f2
+
+ cvt.s.pl $f0, $f1
+ cvt.s.pl $f30, $f31
+ cvt.s.pl $f2, $f2
+
+ cvt.s.pu $f0, $f1
+ cvt.s.pu $f30, $f31
+ cvt.s.pu $f2, $f2
+
+ cvt.w.s $f0, $f1
+ cvt.w.s $f30, $f31
+ cvt.w.s $f2, $f2
+
+ cvt.w.d $f0, $f1
+ cvt.w.d $f30, $f31
+ cvt.w.d $f2, $f2
+
+ cvt.ps.s $f0, $f1, $f2
+ cvt.ps.s $f29, $f30, $f31
+ cvt.ps.s $f29, $f29, $f31
+ cvt.ps.s $f29, $f31
+
+ div.d $f0, $f1, $f2
+ div.d $f29, $f30, $f31
+ div.d $f29, $f29, $f30
+ div.d $f29, $f30
+
+ div.s $f0, $f1, $f2
+ div.s $f29, $f30, $f31
+ div.s $f29, $f29, $f30
+ div.s $f29, $f30
+
+ floor.l.d $f0, $f1
+ floor.l.d $f30, $f31
+ floor.l.d $f2, $f2
+
+ floor.l.s $f0, $f1
+ floor.l.s $f30, $f31
+ floor.l.s $f2, $f2
+
+ floor.w.d $f0, $f1
+ floor.w.d $f30, $f31
+ floor.w.d $f2, $f2
+
+ floor.w.s $f0, $f1
+ floor.w.s $f30, $f31
+ floor.w.s $f2, $f2
+
+ ldc1 $3, 0
+ ldc1 $3, ($0)
+ ldc1 $3, 4
+ ldc1 $3, 4($0)
+ ldc1 $3, ($4)
+ ldc1 $3, 0($4)
+ ldc1 $3, 32767($4)
+ ldc1 $3, -32768($4)
+ ldc1 $3, 65535($4)
+ ldc1 $3, 0xffff0000($4)
+ ldc1 $3, 0xffff8000($4)
+ ldc1 $3, 0xffff0001($4)
+ ldc1 $3, 0xffff8001($4)
+ ldc1 $3, 0xf0000000($4)
+ ldc1 $3, 0xffffffff($4)
+ ldc1 $3, 0x12345678($4)
+ ldc1 $f3, 0
+ ldc1 $f3, ($0)
+ ldc1 $f3, 4
+ ldc1 $f3, 4($0)
+ ldc1 $f3, ($4)
+ ldc1 $f3, 0($4)
+ ldc1 $f3, 32767($4)
+ ldc1 $f3, -32768($4)
+ ldc1 $f3, 65535($4)
+ ldc1 $f3, 0xffff0000($4)
+ ldc1 $f3, 0xffff8000($4)
+ ldc1 $f3, 0xffff0001($4)
+ ldc1 $f3, 0xffff8001($4)
+ ldc1 $f3, 0xf0000000($4)
+ ldc1 $f3, 0xffffffff($4)
+ ldc1 $f3, 0x12345678($4)
+
+ l.d $f3, 0
+ l.d $f3, ($0)
+ l.d $f3, 4
+ l.d $f3, 4($0)
+ l.d $f3, ($4)
+ l.d $f3, 0($4)
+ l.d $f3, 32767($4)
+ l.d $f3, -32768($4)
+
+ ldxc1 $f0, $0($0)
+ ldxc1 $f0, $0($2)
+ ldxc1 $f0, $0($31)
+ ldxc1 $f0, $2($31)
+ ldxc1 $f0, $31($31)
+ ldxc1 $f1, $31($31)
+ ldxc1 $f2, $31($31)
+ ldxc1 $f31, $31($31)
+
+ luxc1 $f0, $0($0)
+ luxc1 $f0, $0($2)
+ luxc1 $f0, $0($31)
+ luxc1 $f0, $2($31)
+ luxc1 $f0, $31($31)
+ luxc1 $f1, $31($31)
+ luxc1 $f2, $31($31)
+ luxc1 $f31, $31($31)
+
+ lwc1 $3, 0
+ lwc1 $3, ($0)
+ lwc1 $3, 4
+ lwc1 $3, 4($0)
+ lwc1 $3, ($4)
+ lwc1 $3, 0($4)
+ lwc1 $3, 32767($4)
+ lwc1 $3, -32768($4)
+ lwc1 $3, 65535($4)
+ lwc1 $3, 0xffff0000($4)
+ lwc1 $3, 0xffff8000($4)
+ lwc1 $3, 0xffff0001($4)
+ lwc1 $3, 0xffff8001($4)
+ lwc1 $3, 0xf0000000($4)
+ lwc1 $3, 0xffffffff($4)
+ lwc1 $3, 0x12345678($4)
+ lwc1 $f3, 0
+ lwc1 $f3, ($0)
+ lwc1 $f3, 4
+ lwc1 $f3, 4($0)
+ lwc1 $f3, ($4)
+ lwc1 $f3, 0($4)
+ lwc1 $f3, 32767($4)
+ lwc1 $f3, -32768($4)
+ lwc1 $f3, 65535($4)
+ lwc1 $f3, 0xffff0000($4)
+ lwc1 $f3, 0xffff8000($4)
+ lwc1 $f3, 0xffff0001($4)
+ lwc1 $f3, 0xffff8001($4)
+ lwc1 $f3, 0xf0000000($4)
+ lwc1 $f3, 0xffffffff($4)
+ lwc1 $f3, 0x12345678($4)
+
+ l.s $f3, 0
+ l.s $f3, ($0)
+ l.s $f3, 4
+ l.s $f3, 4($0)
+ l.s $f3, ($4)
+ l.s $f3, 0($4)
+ l.s $f3, 32767($4)
+ l.s $f3, -32768($4)
+ l.s $f3, 65535($4)
+ l.s $f3, 0xffff0000($4)
+ l.s $f3, 0xffff8000($4)
+ l.s $f3, 0xffff0001($4)
+ l.s $f3, 0xffff8001($4)
+ l.s $f3, 0xf0000000($4)
+ l.s $f3, 0xffffffff($4)
+ l.s $f3, 0x12345678($4)
+
+ lwxc1 $f0, $0($0)
+ lwxc1 $f0, $0($2)
+ lwxc1 $f0, $0($31)
+ lwxc1 $f0, $2($31)
+ lwxc1 $f0, $31($31)
+ lwxc1 $f1, $31($31)
+ lwxc1 $f2, $31($31)
+ lwxc1 $f31, $31($31)
+
+ madd.d $f0, $f1, $f2, $f3
+ madd.d $f28, $f29, $f30, $f31
+ madd.s $f0, $f1, $f2, $f3
+ madd.s $f28, $f29, $f30, $f31
+ madd.ps $f0, $f1, $f2, $f3
+ madd.ps $f28, $f29, $f30, $f31
+
+ mfc1 $5, $0
+ mfc1 $5, $1
+ mfc1 $5, $2
+ mfc1 $5, $3
+ mfc1 $5, $4
+ mfc1 $5, $5
+ mfc1 $5, $6
+ mfc1 $5, $7
+ mfc1 $5, $8
+ mfc1 $5, $9
+ mfc1 $5, $10
+ mfc1 $5, $11
+ mfc1 $5, $12
+ mfc1 $5, $13
+ mfc1 $5, $14
+ mfc1 $5, $15
+ mfc1 $5, $16
+ mfc1 $5, $17
+ mfc1 $5, $18
+ mfc1 $5, $19
+ mfc1 $5, $20
+ mfc1 $5, $21
+ mfc1 $5, $22
+ mfc1 $5, $23
+ mfc1 $5, $24
+ mfc1 $5, $25
+ mfc1 $5, $26
+ mfc1 $5, $27
+ mfc1 $5, $28
+ mfc1 $5, $29
+ mfc1 $5, $30
+ mfc1 $5, $31
+ mfc1 $5, $f0
+ mfc1 $5, $f1
+ mfc1 $5, $f2
+ mfc1 $5, $f3
+ mfc1 $5, $f4
+ mfc1 $5, $f5
+ mfc1 $5, $f6
+ mfc1 $5, $f7
+ mfc1 $5, $f8
+ mfc1 $5, $f9
+ mfc1 $5, $f10
+ mfc1 $5, $f11
+ mfc1 $5, $f12
+ mfc1 $5, $f13
+ mfc1 $5, $f14
+ mfc1 $5, $f15
+ mfc1 $5, $f16
+ mfc1 $5, $f17
+ mfc1 $5, $f18
+ mfc1 $5, $f19
+ mfc1 $5, $f20
+ mfc1 $5, $f21
+ mfc1 $5, $f22
+ mfc1 $5, $f23
+ mfc1 $5, $f24
+ mfc1 $5, $f25
+ mfc1 $5, $f26
+ mfc1 $5, $f27
+ mfc1 $5, $f28
+ mfc1 $5, $f29
+ mfc1 $5, $f30
+ mfc1 $5, $f31
+
+ mfhc1 $5, $0
+ mfhc1 $5, $1
+ mfhc1 $5, $2
+ mfhc1 $5, $3
+ mfhc1 $5, $4
+ mfhc1 $5, $5
+ mfhc1 $5, $6
+ mfhc1 $5, $7
+ mfhc1 $5, $8
+ mfhc1 $5, $9
+ mfhc1 $5, $10
+ mfhc1 $5, $11
+ mfhc1 $5, $12
+ mfhc1 $5, $13
+ mfhc1 $5, $14
+ mfhc1 $5, $15
+ mfhc1 $5, $16
+ mfhc1 $5, $17
+ mfhc1 $5, $18
+ mfhc1 $5, $19
+ mfhc1 $5, $20
+ mfhc1 $5, $21
+ mfhc1 $5, $22
+ mfhc1 $5, $23
+ mfhc1 $5, $24
+ mfhc1 $5, $25
+ mfhc1 $5, $26
+ mfhc1 $5, $27
+ mfhc1 $5, $28
+ mfhc1 $5, $29
+ mfhc1 $5, $30
+ mfhc1 $5, $31
+ mfhc1 $5, $f0
+ mfhc1 $5, $f1
+ mfhc1 $5, $f2
+ mfhc1 $5, $f3
+ mfhc1 $5, $f4
+ mfhc1 $5, $f5
+ mfhc1 $5, $f6
+ mfhc1 $5, $f7
+ mfhc1 $5, $f8
+ mfhc1 $5, $f9
+ mfhc1 $5, $f10
+ mfhc1 $5, $f11
+ mfhc1 $5, $f12
+ mfhc1 $5, $f13
+ mfhc1 $5, $f14
+ mfhc1 $5, $f15
+ mfhc1 $5, $f16
+ mfhc1 $5, $f17
+ mfhc1 $5, $f18
+ mfhc1 $5, $f19
+ mfhc1 $5, $f20
+ mfhc1 $5, $f21
+ mfhc1 $5, $f22
+ mfhc1 $5, $f23
+ mfhc1 $5, $f24
+ mfhc1 $5, $f25
+ mfhc1 $5, $f26
+ mfhc1 $5, $f27
+ mfhc1 $5, $f28
+ mfhc1 $5, $f29
+ mfhc1 $5, $f30
+ mfhc1 $5, $f31
+
+ mov.d $f0, $f1
+ mov.d $f30, $f31
+ mov.s $f0, $f1
+ mov.s $f30, $f31
+ mov.ps $f0, $f1
+ mov.ps $f30, $f31
+
+ movf.d $f2, $f3, $fcc0
+ movf.d $f2, $f3, $fcc1
+ movf.d $f2, $f3, $fcc2
+ movf.d $f2, $f3, $fcc3
+ movf.d $f2, $f3, $fcc4
+ movf.d $f2, $f3, $fcc5
+ movf.d $f2, $f3, $fcc6
+ movf.d $f2, $f3, $fcc7
+ movf.d $f30, $f31, $fcc7
+
+ movf.s $f2, $f3, $fcc0
+ movf.s $f2, $f3, $fcc1
+ movf.s $f2, $f3, $fcc2
+ movf.s $f2, $f3, $fcc3
+ movf.s $f2, $f3, $fcc4
+ movf.s $f2, $f3, $fcc5
+ movf.s $f2, $f3, $fcc6
+ movf.s $f2, $f3, $fcc7
+ movf.s $f30, $f31, $fcc7
+
+ movf.ps $f2, $f3, $fcc0
+ movf.ps $f2, $f3, $fcc2
+ movf.ps $f2, $f3, $fcc4
+ movf.ps $f2, $f3, $fcc6
+ movf.ps $f2, $f3, $fcc6
+ movf.ps $f30, $f31, $fcc6
+
+ movn.d $f2, $f3, $0
+ movn.d $f2, $f3, $31
+ movn.s $f2, $f3, $0
+ movn.s $f2, $f3, $31
+ movn.ps $f2, $f3, $0
+ movn.ps $f2, $f3, $31
+
+ movt.ps $f2, $f3, $fcc0
+ movt.ps $f2, $f3, $fcc2
+ movt.ps $f2, $f3, $fcc4
+ movt.ps $f2, $f3, $fcc6
+ movt.ps $f2, $f3, $fcc6
+ movt.ps $f30, $f31, $fcc6
+
+ movz.d $f2, $f3, $0
+ movz.d $f2, $f3, $31
+ movz.s $f2, $f3, $0
+ movz.s $f2, $f3, $31
+ movz.ps $f2, $f3, $0
+ movz.ps $f2, $f3, $31
+
+ msub.d $f0, $f1, $f2, $f3
+ msub.d $f28, $f29, $f30, $f31
+ msub.s $f0, $f1, $f2, $f3
+ msub.s $f28, $f29, $f30, $f31
+ msub.ps $f0, $f1, $f2, $f3
+ msub.ps $f28, $f29, $f30, $f31
+
+ mtc1 $5, $0
+ mtc1 $5, $1
+ mtc1 $5, $2
+ mtc1 $5, $3
+ mtc1 $5, $4
+ mtc1 $5, $5
+ mtc1 $5, $6
+ mtc1 $5, $7
+ mtc1 $5, $8
+ mtc1 $5, $9
+ mtc1 $5, $10
+ mtc1 $5, $11
+ mtc1 $5, $12
+ mtc1 $5, $13
+ mtc1 $5, $14
+ mtc1 $5, $15
+ mtc1 $5, $16
+ mtc1 $5, $17
+ mtc1 $5, $18
+ mtc1 $5, $19
+ mtc1 $5, $20
+ mtc1 $5, $21
+ mtc1 $5, $22
+ mtc1 $5, $23
+ mtc1 $5, $24
+ mtc1 $5, $25
+ mtc1 $5, $26
+ mtc1 $5, $27
+ mtc1 $5, $28
+ mtc1 $5, $29
+ mtc1 $5, $30
+ mtc1 $5, $31
+ mtc1 $5, $f0
+ mtc1 $5, $f1
+ mtc1 $5, $f2
+ mtc1 $5, $f3
+ mtc1 $5, $f4
+ mtc1 $5, $f5
+ mtc1 $5, $f6
+ mtc1 $5, $f7
+ mtc1 $5, $f8
+ mtc1 $5, $f9
+ mtc1 $5, $f10
+ mtc1 $5, $f11
+ mtc1 $5, $f12
+ mtc1 $5, $f13
+ mtc1 $5, $f14
+ mtc1 $5, $f15
+ mtc1 $5, $f16
+ mtc1 $5, $f17
+ mtc1 $5, $f18
+ mtc1 $5, $f19
+ mtc1 $5, $f20
+ mtc1 $5, $f21
+ mtc1 $5, $f22
+ mtc1 $5, $f23
+ mtc1 $5, $f24
+ mtc1 $5, $f25
+ mtc1 $5, $f26
+ mtc1 $5, $f27
+ mtc1 $5, $f28
+ mtc1 $5, $f29
+ mtc1 $5, $f30
+ mtc1 $5, $f31
+
+ mthc1 $5, $0
+ mthc1 $5, $1
+ mthc1 $5, $2
+ mthc1 $5, $3
+ mthc1 $5, $4
+ mthc1 $5, $5
+ mthc1 $5, $6
+ mthc1 $5, $7
+ mthc1 $5, $8
+ mthc1 $5, $9
+ mthc1 $5, $10
+ mthc1 $5, $11
+ mthc1 $5, $12
+ mthc1 $5, $13
+ mthc1 $5, $14
+ mthc1 $5, $15
+ mthc1 $5, $16
+ mthc1 $5, $17
+ mthc1 $5, $18
+ mthc1 $5, $19
+ mthc1 $5, $20
+ mthc1 $5, $21
+ mthc1 $5, $22
+ mthc1 $5, $23
+ mthc1 $5, $24
+ mthc1 $5, $25
+ mthc1 $5, $26
+ mthc1 $5, $27
+ mthc1 $5, $28
+ mthc1 $5, $29
+ mthc1 $5, $30
+ mthc1 $5, $31
+ mthc1 $5, $f0
+ mthc1 $5, $f1
+ mthc1 $5, $f2
+ mthc1 $5, $f3
+ mthc1 $5, $f4
+ mthc1 $5, $f5
+ mthc1 $5, $f6
+ mthc1 $5, $f7
+ mthc1 $5, $f8
+ mthc1 $5, $f9
+ mthc1 $5, $f10
+ mthc1 $5, $f11
+ mthc1 $5, $f12
+ mthc1 $5, $f13
+ mthc1 $5, $f14
+ mthc1 $5, $f15
+ mthc1 $5, $f16
+ mthc1 $5, $f17
+ mthc1 $5, $f18
+ mthc1 $5, $f19
+ mthc1 $5, $f20
+ mthc1 $5, $f21
+ mthc1 $5, $f22
+ mthc1 $5, $f23
+ mthc1 $5, $f24
+ mthc1 $5, $f25
+ mthc1 $5, $f26
+ mthc1 $5, $f27
+ mthc1 $5, $f28
+ mthc1 $5, $f29
+ mthc1 $5, $f30
+ mthc1 $5, $f31
+
+ mul.s $f0, $f1, $f2
+ mul.s $f29, $f30, $f31
+ mul.s $f29, $f29, $f30
+ mul.s $f29, $f30
+ mul.d $f0, $f1, $f2
+ mul.d $f29, $f30, $f31
+ mul.d $f29, $f29, $f30
+ mul.d $f29, $f30
+ mul.ps $f0, $f1, $f2
+ mul.ps $f29, $f30, $f31
+ mul.ps $f29, $f29, $f30
+ mul.ps $f29, $f30
+
+ neg.s $f0, $f1
+ neg.s $f30, $f31
+ neg.s $f2, $f2
+ neg.s $f2
+ neg.d $f0, $f1
+ neg.d $f30, $f31
+ neg.d $f2, $f2
+ neg.d $f2
+ neg.ps $f0, $f1
+ neg.ps $f30, $f31
+ neg.ps $f2, $f2
+ neg.ps $f2
+
+ nmadd.d $f0, $f1, $f2, $f3
+ nmadd.d $f28, $f29, $f30, $f31
+ nmadd.s $f0, $f1, $f2, $f3
+ nmadd.s $f28, $f29, $f30, $f31
+ nmadd.ps $f0, $f1, $f2, $f3
+ nmadd.ps $f28, $f29, $f30, $f31
+
+ nmsub.d $f0, $f1, $f2, $f3
+ nmsub.d $f28, $f29, $f30, $f31
+ nmsub.s $f0, $f1, $f2, $f3
+ nmsub.s $f28, $f29, $f30, $f31
+ nmsub.ps $f0, $f1, $f2, $f3
+ nmsub.ps $f28, $f29, $f30, $f31
+
+ pll.ps $f0, $f1, $f2
+ pll.ps $f29, $f30, $f31
+ pll.ps $f29, $f29, $f30
+ pll.ps $f29, $f30
+ plu.ps $f0, $f1, $f2
+ plu.ps $f29, $f30, $f31
+ plu.ps $f29, $f29, $f30
+ plu.ps $f29, $f30
+ pul.ps $f0, $f1, $f2
+ pul.ps $f29, $f30, $f31
+ pul.ps $f29, $f29, $f30
+ pul.ps $f29, $f30
+ puu.ps $f0, $f1, $f2
+ puu.ps $f29, $f30, $f31
+ puu.ps $f29, $f29, $f30
+ puu.ps $f29, $f30
+
+ recip.s $f0, $f1
+ recip.s $f30, $f31
+ recip.s $f2, $f2
+ recip.d $f0, $f1
+ recip.d $f30, $f31
+ recip.d $f2, $f2
+
+ round.l.s $f0, $f1
+ round.l.s $f30, $f31
+ round.l.s $f2, $f2
+ round.l.d $f0, $f1
+ round.l.d $f30, $f31
+ round.l.d $f2, $f2
+
+ round.w.s $f0, $f1
+ round.w.s $f30, $f31
+ round.w.s $f2, $f2
+ round.w.d $f0, $f1
+ round.w.d $f30, $f31
+ round.w.d $f2, $f2
+
+ rsqrt.s $f0, $f1
+ rsqrt.s $f30, $f31
+ rsqrt.s $f2, $f2
+ rsqrt.d $f0, $f1
+ rsqrt.d $f30, $f31
+ rsqrt.d $f2, $f2
+
+ sdc1 $3, 0
+ sdc1 $3, ($0)
+ sdc1 $3, 4
+ sdc1 $3, 4($0)
+ sdc1 $3, ($4)
+ sdc1 $3, 0($4)
+ sdc1 $3, 32767($4)
+ sdc1 $3, -32768($4)
+ sdc1 $3, 65535($4)
+ sdc1 $3, 0xffff0000($4)
+ sdc1 $3, 0xffff8000($4)
+ sdc1 $3, 0xffff0001($4)
+ sdc1 $3, 0xffff8001($4)
+ sdc1 $3, 0xf0000000($4)
+ sdc1 $3, 0xffffffff($4)
+ sdc1 $3, 0x12345678($4)
+ sdc1 $f3, 0
+ sdc1 $f3, ($0)
+ sdc1 $f3, 4
+ sdc1 $f3, 4($0)
+ sdc1 $f3, ($4)
+ sdc1 $f3, 0($4)
+ sdc1 $f3, 32767($4)
+ sdc1 $f3, -32768($4)
+ sdc1 $f3, 65535($4)
+ sdc1 $f3, 0xffff0000($4)
+ sdc1 $f3, 0xffff8000($4)
+ sdc1 $f3, 0xffff0001($4)
+ sdc1 $f3, 0xffff8001($4)
+ sdc1 $f3, 0xf0000000($4)
+ sdc1 $f3, 0xffffffff($4)
+ sdc1 $f3, 0x12345678($4)
+
+ s.d $f3, 0
+ s.d $f3, ($0)
+ s.d $f3, 4
+ s.d $f3, 4($0)
+ s.d $f3, ($4)
+ s.d $f3, 0($4)
+ s.d $f3, 32767($4)
+ s.d $f3, -32768($4)
+
+ sdxc1 $f0, $0($0)
+ sdxc1 $f0, $0($2)
+ sdxc1 $f0, $0($31)
+ sdxc1 $f0, $2($31)
+ sdxc1 $f0, $31($31)
+ sdxc1 $f1, $31($31)
+ sdxc1 $f2, $31($31)
+ sdxc1 $f31, $31($31)
+
+ sqrt.s $f0, $f1
+ sqrt.s $f30, $f31
+ sqrt.s $f2, $f2
+ sqrt.d $f0, $f1
+ sqrt.d $f30, $f31
+ sqrt.d $f2, $f2
+
+ sub.s $f0, $f1, $f2
+ sub.s $f29, $f30, $f31
+ sub.s $f29, $f29, $f30
+ sub.s $f29, $f30
+ sub.d $f0, $f1, $f2
+ sub.d $f29, $f30, $f31
+ sub.d $f29, $f29, $f30
+ sub.d $f29, $f30
+ sub.ps $f0, $f1, $f2
+ sub.ps $f29, $f30, $f31
+ sub.ps $f29, $f29, $f30
+ sub.ps $f29, $f30
+
+ suxc1 $f0, $0($0)
+ suxc1 $f0, $0($2)
+ suxc1 $f0, $0($31)
+ suxc1 $f0, $2($31)
+ suxc1 $f0, $31($31)
+ suxc1 $f1, $31($31)
+ suxc1 $f2, $31($31)
+ suxc1 $f31, $31($31)
+
+ swc1 $3, 0
+ swc1 $3, ($0)
+ swc1 $3, 4
+ swc1 $3, 4($0)
+ swc1 $3, ($4)
+ swc1 $3, 0($4)
+ swc1 $3, 32767($4)
+ swc1 $3, -32768($4)
+ swc1 $3, 65535($4)
+ swc1 $3, 0xffff0000($4)
+ swc1 $3, 0xffff8000($4)
+ swc1 $3, 0xffff0001($4)
+ swc1 $3, 0xffff8001($4)
+ swc1 $3, 0xf0000000($4)
+ swc1 $3, 0xffffffff($4)
+ swc1 $3, 0x12345678($4)
+ swc1 $f3, 0
+ swc1 $f3, ($0)
+ swc1 $f3, 4
+ swc1 $f3, 4($0)
+ swc1 $f3, ($4)
+ swc1 $f3, 0($4)
+ swc1 $f3, 32767($4)
+ swc1 $f3, -32768($4)
+ swc1 $f3, 65535($4)
+ swc1 $f3, 0xffff0000($4)
+ swc1 $f3, 0xffff8000($4)
+ swc1 $f3, 0xffff0001($4)
+ swc1 $f3, 0xffff8001($4)
+ swc1 $f3, 0xf0000000($4)
+ swc1 $f3, 0xffffffff($4)
+ swc1 $f3, 0x12345678($4)
+
+ s.s $f3, 0
+ s.s $f3, ($0)
+ s.s $f3, 4
+ s.s $f3, 4($0)
+ s.s $f3, ($4)
+ s.s $f3, 0($4)
+ s.s $f3, 32767($4)
+ s.s $f3, -32768($4)
+ s.s $f3, 65535($4)
+ s.s $f3, 0xffff0000($4)
+ s.s $f3, 0xffff8000($4)
+ s.s $f3, 0xffff0001($4)
+ s.s $f3, 0xffff8001($4)
+ s.s $f3, 0xf0000000($4)
+ s.s $f3, 0xffffffff($4)
+ s.s $f3, 0x12345678($4)
+
+ swxc1 $f0, $0($0)
+ swxc1 $f0, $0($2)
+ swxc1 $f0, $0($31)
+ swxc1 $f0, $2($31)
+ swxc1 $f0, $31($31)
+ swxc1 $f1, $31($31)
+ swxc1 $f2, $31($31)
+ swxc1 $f31, $31($31)
+
+ trunc.l.s $f0, $f1
+ trunc.l.s $f30, $f31
+ trunc.l.s $f2, $f2
+ trunc.l.d $f0, $f1
+ trunc.l.d $f30, $f31
+ trunc.l.d $f2, $f2
+
+ trunc.w.s $f0, $f1
+ trunc.w.s $f30, $f31
+ trunc.w.s $f2, $f2
+ trunc.w.d $f0, $f1
+ trunc.w.d $f30, $f31
+ trunc.w.d $f2, $f2
+
+ movf $2, $3, $fcc0
+ movf $30, $31, $fcc0
+ movf $30, $31, $fcc1
+ movf $30, $31, $fcc2
+ movf $30, $31, $fcc3
+ movf $30, $31, $fcc4
+ movf $30, $31, $fcc5
+ movf $30, $31, $fcc6
+ movf $30, $31, $fcc7
+
+ movt $2, $3, $fcc0
+ movt $30, $31, $fcc0
+ movt $30, $31, $fcc1
+ movt $30, $31, $fcc2
+ movt $30, $31, $fcc3
+ movt $30, $31, $fcc4
+ movt $30, $31, $fcc5
+ movt $30, $31, $fcc6
+ movt $30, $31, $fcc7
+
+ .set noreorder
+ bc1fl $fcc1, test
+ addu $3, $4, $5
+ bc1tl $fcc2, test
+ addu $6, $7, $8
+ .set reorder
+
+ bc1fl $fcc3, test
+ addu $3, $4, $5
+ bc1tl $fcc4, test
+ addu $6, $7, $8
+
+ .end fp_test
+
+ .set mips64r2
+ .globl test_mips64
+ .ent test_mips64
+
+test_mips64:
+ dabs $2, $3
+ dabs $2, $2
+ dabs $2
+
+ dadd $2, $3, $4
+ dadd $29, $30, $31
+ dadd $2, $2, $3
+ dadd $2, $3
+
+ dadd $2, $3, 0
+ dadd $2, $3, 1
+ dadd $2, $3, -512
+ dadd $2, $3, 511
+ dadd $2, $3, 32767
+ dadd $2, $3, -32768
+ dadd $2, $3, 65535
+ dadd $2, $3, 0x12345678
+ dadd $2, $3, 0x1234567887654321
+
+ daddi $2, $3, 0
+ daddi $2, $3, 1
+ daddi $2, $3, -512
+ daddi $2, $3, 511
+ daddi $2, $2, 511
+ daddi $2, 511
+ daddi $2, $3, 32767
+ daddi $2, $3, -32768
+ daddi $2, $3, 65535
+ daddi $2, $3, 0x12345678
+
+ daddiu $2, $3, 0
+ daddiu $2, $3, -32768
+ daddiu $2, $3, 32767
+ daddiu $2, $2, 32767
+ daddiu $2, 32767
+
+ daddu $2, $3, $4
+ daddu $29, $30, $31
+ daddu $2, $2, $3
+ daddu $2, $3
+ daddu $2, $3, $0
+ daddu $2, $3, 0
+ daddu $2, $3, 1
+ daddu $2, $3, 32767
+ daddu $2, $3, -32768
+ daddu $2, $3, 65535
+
+ dclo $2, $3
+ dclo $3, $2
+ dclz $2, $3
+ dclz $3, $2
+
+ ddiv $0, $2, $3
+ ddiv $0, $30, $31
+ ddiv $0, $3
+ ddiv $0, $31
+
+ ddiv $2, $3, $0
+ ddiv $2, $3, $4
+
+ ddiv $3, $4, 0
+ ddiv $3, $4, 1
+ ddiv $3, $4, -1
+ ddiv $3, $4, 2
+
+ ddivu $0, $2, $3
+ ddivu $0, $30, $31
+ ddivu $0, $3
+ ddivu $0, $31
+
+ ddivu $2, $3, $0
+ ddivu $2, $3, $4
+
+ ddivu $3, $4, 0
+ ddivu $3, $4, 1
+ ddivu $3, $4, -1
+ ddivu $3, $4, 2
+
+ dext $2, $3, 31, 1
+ dext $2, $3, 0, 32
+
+ dext $2, $3, 31, 33
+ dextm $2, $3, 31, 33
+
+ dext $2, $3, 33, 10
+ dextu $2, $3, 33, 10
+
+ dins $2, $3, 31, 1
+ dins $2, $3, 0, 32
+
+ dins $2, $3, 31, 33
+ dinsm $2, $3, 31, 33
+
+ dins $2, $3, 33, 10
+ dinsu $2, $3, 33, 10
+
+ dla $2, test
+ dlca $2, test
+
+ dli $2, -32768
+ dli $2, 32767
+ dli $2, 65535
+ dli $2, 0x12345678
+
+ dmfc0 $2, $0
+ dmfc0 $2, $1
+ dmfc0 $2, $2
+ dmfc0 $2, $3
+ dmfc0 $2, $4
+ dmfc0 $2, $5
+ dmfc0 $2, $6
+ dmfc0 $2, $7
+ dmfc0 $2, $8
+ dmfc0 $2, $9
+ dmfc0 $2, $10
+ dmfc0 $2, $11
+ dmfc0 $2, $12
+ dmfc0 $2, $13
+ dmfc0 $2, $14
+ dmfc0 $2, $15
+ dmfc0 $2, $16
+ dmfc0 $2, $17
+ dmfc0 $2, $18
+ dmfc0 $2, $19
+ dmfc0 $2, $20
+ dmfc0 $2, $21
+ dmfc0 $2, $22
+ dmfc0 $2, $23
+ dmfc0 $2, $24
+ dmfc0 $2, $25
+ dmfc0 $2, $26
+ dmfc0 $2, $27
+ dmfc0 $2, $28
+ dmfc0 $2, $29
+ dmfc0 $2, $30
+ dmfc0 $2, $31
+ dmfc0 $2, $0, 0
+ dmfc0 $2, $0, 1
+ dmfc0 $2, $0, 2
+ dmfc0 $2, $0, 3
+ dmfc0 $2, $0, 4
+ dmfc0 $2, $0, 5
+ dmfc0 $2, $0, 6
+ dmfc0 $2, $0, 7
+ dmfc0 $2, $1, 0
+ dmfc0 $2, $1, 1
+ dmfc0 $2, $1, 2
+ dmfc0 $2, $1, 3
+ dmfc0 $2, $1, 4
+ dmfc0 $2, $1, 5
+ dmfc0 $2, $1, 6
+ dmfc0 $2, $1, 7
+ dmfc0 $2, $2, 0
+ dmfc0 $2, $2, 1
+ dmfc0 $2, $2, 2
+ dmfc0 $2, $2, 3
+ dmfc0 $2, $2, 4
+ dmfc0 $2, $2, 5
+ dmfc0 $2, $2, 6
+ dmfc0 $2, $2, 7
+
+ dmtc0 $2, $0
+ dmtc0 $2, $1
+ dmtc0 $2, $2
+ dmtc0 $2, $3
+ dmtc0 $2, $4
+ dmtc0 $2, $5
+ dmtc0 $2, $6
+ dmtc0 $2, $7
+ dmtc0 $2, $8
+ dmtc0 $2, $9
+ dmtc0 $2, $10
+ dmtc0 $2, $11
+ dmtc0 $2, $12
+ dmtc0 $2, $13
+ dmtc0 $2, $14
+ dmtc0 $2, $15
+ dmtc0 $2, $16
+ dmtc0 $2, $17
+ dmtc0 $2, $18
+ dmtc0 $2, $19
+ dmtc0 $2, $20
+ dmtc0 $2, $21
+ dmtc0 $2, $22
+ dmtc0 $2, $23
+ dmtc0 $2, $24
+ dmtc0 $2, $25
+ dmtc0 $2, $26
+ dmtc0 $2, $27
+ dmtc0 $2, $28
+ dmtc0 $2, $29
+ dmtc0 $2, $30
+ dmtc0 $2, $31
+ dmtc0 $2, $0, 0
+ dmtc0 $2, $0, 1
+ dmtc0 $2, $0, 2
+ dmtc0 $2, $0, 3
+ dmtc0 $2, $0, 4
+ dmtc0 $2, $0, 5
+ dmtc0 $2, $0, 6
+ dmtc0 $2, $0, 7
+ dmtc0 $2, $1, 0
+ dmtc0 $2, $1, 1
+ dmtc0 $2, $1, 2
+ dmtc0 $2, $1, 3
+ dmtc0 $2, $1, 4
+ dmtc0 $2, $1, 5
+ dmtc0 $2, $1, 6
+ dmtc0 $2, $1, 7
+ dmtc0 $2, $2, 0
+ dmtc0 $2, $2, 1
+ dmtc0 $2, $2, 2
+ dmtc0 $2, $2, 3
+ dmtc0 $2, $2, 4
+ dmtc0 $2, $2, 5
+ dmtc0 $2, $2, 6
+ dmtc0 $2, $2, 7
+
+ dmfc1 $5, $0
+ dmfc1 $5, $1
+ dmfc1 $5, $2
+ dmfc1 $5, $3
+ dmfc1 $5, $4
+ dmfc1 $5, $5
+ dmfc1 $5, $6
+ dmfc1 $5, $7
+ dmfc1 $5, $8
+ dmfc1 $5, $9
+ dmfc1 $5, $10
+ dmfc1 $5, $11
+ dmfc1 $5, $12
+ dmfc1 $5, $13
+ dmfc1 $5, $14
+ dmfc1 $5, $15
+ dmfc1 $5, $16
+ dmfc1 $5, $17
+ dmfc1 $5, $18
+ dmfc1 $5, $19
+ dmfc1 $5, $20
+ dmfc1 $5, $21
+ dmfc1 $5, $22
+ dmfc1 $5, $23
+ dmfc1 $5, $24
+ dmfc1 $5, $25
+ dmfc1 $5, $26
+ dmfc1 $5, $27
+ dmfc1 $5, $28
+ dmfc1 $5, $29
+ dmfc1 $5, $30
+ dmfc1 $5, $31
+ dmfc1 $5, $f0
+ dmfc1 $5, $f1
+ dmfc1 $5, $f2
+ dmfc1 $5, $f3
+ dmfc1 $5, $f4
+ dmfc1 $5, $f5
+ dmfc1 $5, $f6
+ dmfc1 $5, $f7
+ dmfc1 $5, $f8
+ dmfc1 $5, $f9
+ dmfc1 $5, $f10
+ dmfc1 $5, $f11
+ dmfc1 $5, $f12
+ dmfc1 $5, $f13
+ dmfc1 $5, $f14
+ dmfc1 $5, $f15
+ dmfc1 $5, $f16
+ dmfc1 $5, $f17
+ dmfc1 $5, $f18
+ dmfc1 $5, $f19
+ dmfc1 $5, $f20
+ dmfc1 $5, $f21
+ dmfc1 $5, $f22
+ dmfc1 $5, $f23
+ dmfc1 $5, $f24
+ dmfc1 $5, $f25
+ dmfc1 $5, $f26
+ dmfc1 $5, $f27
+ dmfc1 $5, $f28
+ dmfc1 $5, $f29
+ dmfc1 $5, $f30
+ dmfc1 $5, $f31
+
+ dmtc1 $5, $0
+ dmtc1 $5, $1
+ dmtc1 $5, $2
+ dmtc1 $5, $3
+ dmtc1 $5, $4
+ dmtc1 $5, $5
+ dmtc1 $5, $6
+ dmtc1 $5, $7
+ dmtc1 $5, $8
+ dmtc1 $5, $9
+ dmtc1 $5, $10
+ dmtc1 $5, $11
+ dmtc1 $5, $12
+ dmtc1 $5, $13
+ dmtc1 $5, $14
+ dmtc1 $5, $15
+ dmtc1 $5, $16
+ dmtc1 $5, $17
+ dmtc1 $5, $18
+ dmtc1 $5, $19
+ dmtc1 $5, $20
+ dmtc1 $5, $21
+ dmtc1 $5, $22
+ dmtc1 $5, $23
+ dmtc1 $5, $24
+ dmtc1 $5, $25
+ dmtc1 $5, $26
+ dmtc1 $5, $27
+ dmtc1 $5, $28
+ dmtc1 $5, $29
+ dmtc1 $5, $30
+ dmtc1 $5, $31
+ dmtc1 $5, $f0
+ dmtc1 $5, $f1
+ dmtc1 $5, $f2
+ dmtc1 $5, $f3
+ dmtc1 $5, $f4
+ dmtc1 $5, $f5
+ dmtc1 $5, $f6
+ dmtc1 $5, $f7
+ dmtc1 $5, $f8
+ dmtc1 $5, $f9
+ dmtc1 $5, $f10
+ dmtc1 $5, $f11
+ dmtc1 $5, $f12
+ dmtc1 $5, $f13
+ dmtc1 $5, $f14
+ dmtc1 $5, $f15
+ dmtc1 $5, $f16
+ dmtc1 $5, $f17
+ dmtc1 $5, $f18
+ dmtc1 $5, $f19
+ dmtc1 $5, $f20
+ dmtc1 $5, $f21
+ dmtc1 $5, $f22
+ dmtc1 $5, $f23
+ dmtc1 $5, $f24
+ dmtc1 $5, $f25
+ dmtc1 $5, $f26
+ dmtc1 $5, $f27
+ dmtc1 $5, $f28
+ dmtc1 $5, $f29
+ dmtc1 $5, $f30
+ dmtc1 $5, $f31
+
+ dmfc2 $2, $0
+ dmfc2 $2, $1
+ dmfc2 $2, $2
+ dmfc2 $2, $3
+ dmfc2 $2, $4
+ dmfc2 $2, $5
+ dmfc2 $2, $6
+ dmfc2 $2, $7
+ dmfc2 $2, $8
+ dmfc2 $2, $9
+ dmfc2 $2, $10
+ dmfc2 $2, $11
+ dmfc2 $2, $12
+ dmfc2 $2, $13
+ dmfc2 $2, $14
+ dmfc2 $2, $15
+ dmfc2 $2, $16
+ dmfc2 $2, $17
+ dmfc2 $2, $18
+ dmfc2 $2, $19
+ dmfc2 $2, $20
+ dmfc2 $2, $21
+ dmfc2 $2, $22
+ dmfc2 $2, $23
+ dmfc2 $2, $24
+ dmfc2 $2, $25
+ dmfc2 $2, $26
+ dmfc2 $2, $27
+ dmfc2 $2, $28
+ dmfc2 $2, $29
+ dmfc2 $2, $30
+ dmfc2 $2, $31
+/*
+ dmfc2 $2, $0, 0
+ dmfc2 $2, $0, 1
+ dmfc2 $2, $0, 2
+ dmfc2 $2, $0, 3
+ dmfc2 $2, $0, 4
+ dmfc2 $2, $0, 5
+ dmfc2 $2, $0, 6
+ dmfc2 $2, $0, 7
+ dmfc2 $2, $1, 0
+ dmfc2 $2, $1, 1
+ dmfc2 $2, $1, 2
+ dmfc2 $2, $1, 3
+ dmfc2 $2, $1, 4
+ dmfc2 $2, $1, 5
+ dmfc2 $2, $1, 6
+ dmfc2 $2, $1, 7
+ dmfc2 $2, $2, 0
+ dmfc2 $2, $2, 1
+ dmfc2 $2, $2, 2
+ dmfc2 $2, $2, 3
+ dmfc2 $2, $2, 4
+ dmfc2 $2, $2, 5
+ dmfc2 $2, $2, 6
+ dmfc2 $2, $2, 7
+*/
+
+ dmtc2 $2, $0
+ dmtc2 $2, $1
+ dmtc2 $2, $2
+ dmtc2 $2, $3
+ dmtc2 $2, $4
+ dmtc2 $2, $5
+ dmtc2 $2, $6
+ dmtc2 $2, $7
+ dmtc2 $2, $8
+ dmtc2 $2, $9
+ dmtc2 $2, $10
+ dmtc2 $2, $11
+ dmtc2 $2, $12
+ dmtc2 $2, $13
+ dmtc2 $2, $14
+ dmtc2 $2, $15
+ dmtc2 $2, $16
+ dmtc2 $2, $17
+ dmtc2 $2, $18
+ dmtc2 $2, $19
+ dmtc2 $2, $20
+ dmtc2 $2, $21
+ dmtc2 $2, $22
+ dmtc2 $2, $23
+ dmtc2 $2, $24
+ dmtc2 $2, $25
+ dmtc2 $2, $26
+ dmtc2 $2, $27
+ dmtc2 $2, $28
+ dmtc2 $2, $29
+ dmtc2 $2, $30
+ dmtc2 $2, $31
+/*
+ dmtc2 $2, $0, 0
+ dmtc2 $2, $0, 1
+ dmtc2 $2, $0, 2
+ dmtc2 $2, $0, 3
+ dmtc2 $2, $0, 4
+ dmtc2 $2, $0, 5
+ dmtc2 $2, $0, 6
+ dmtc2 $2, $0, 7
+ dmtc2 $2, $1, 0
+ dmtc2 $2, $1, 1
+ dmtc2 $2, $1, 2
+ dmtc2 $2, $1, 3
+ dmtc2 $2, $1, 4
+ dmtc2 $2, $1, 5
+ dmtc2 $2, $1, 6
+ dmtc2 $2, $1, 7
+ dmtc2 $2, $2, 0
+ dmtc2 $2, $2, 1
+ dmtc2 $2, $2, 2
+ dmtc2 $2, $2, 3
+ dmtc2 $2, $2, 4
+ dmtc2 $2, $2, 5
+ dmtc2 $2, $2, 6
+ dmtc2 $2, $2, 7
+*/
+
+ dmult $2, $3
+ dmultu $2, $3
+
+ dmul $2, $3, $4
+ dmul $2, $3, 0x12345678
+
+ dmulo $2, $3, $4
+ dmulo $2, $3, 4
+
+ dmulou $2, $3, $4
+ dmulou $2, $3, 4
+
+ drem $3, $4, 0
+ drem $3, $4, 1
+ drem $3, $4, -1
+ drem $3, $4, 2
+
+ drem $0, $2, $3
+ drem $0, $30, $31
+ drem $0, $3
+ drem $0, $31
+
+ drem $3, $4, 0
+ drem $3, $4, 1
+ drem $3, $4, -1
+ drem $3, $4, 2
+
+ dremu $0, $2, $3
+ dremu $0, $30, $31
+ dremu $0, $3
+ dremu $0, $31
+
+ dremu $3, $4, 0
+ dremu $3, $4, 1
+ dremu $3, $4, -1
+ dremu $3, $4, 2
+
+ drol $2, $3, $4
+ drol $2, $2, $4
+ drol $2, $3, 4
+
+ dror $2, $3, $4
+ dror $2, $3, 4
+ dror $2, $3, 36
+
+ drorv $2, $3, $4
+ dror32 $2, $3, 4
+
+ drotl $2, $3, $4
+ drotl $2, $2, $4
+ drotl $2, $3, 4
+
+ drotr $2, $3, $4
+ drotr $2, $3, 4
+ drotr $2, $3, 36
+
+ drotrv $2, $3, $4
+ drotr32 $2, $3, 4
+
+ dsbh $2, $3
+ dsbh $2, $2
+ dsbh $2
+
+ dshd $2, $3
+ dshd $2, $2
+ dshd $2
+
+ dsllv $2, $3, $4
+ dsll32 $2, $3, 31
+ dsll $2, $3, $4
+ dsll $2, $3, 63
+ dsll $2, $3, 31
+
+ dsrav $2, $3, $4
+ dsra32 $2, $3, 4
+ dsra $2, $3, $4
+ dsra $2, $3, 36
+ dsra $2, $3, 4
+
+ dsrlv $2, $3, $4
+ dsrl32 $2, $3, 31
+ dsrl $2, $3, $4
+ dsrl $2, $3, 36
+ dsrl $2, $3, 4
+
+ dsub $2, $3, $4
+ dsub $29, $30, $31
+ dsub $2, $2, $3
+ dsub $2, $3
+
+ dsubu $2, $3, $4
+ dsubu $29, $30, $31
+ dsubu $2, $2, $3
+ dsubu $2, $3
+
+ dsubu $2, $3, 0x1234
+ dsubu $2, $3, 0x12345678
+
+ dsub $2, $3, 0
+ dsub $2, $3, 1
+ dsub $2, $3, 512
+ dsub $2, $3, -511
+ dsub $2, $3, -32768
+ dsub $2, $3, 32767
+ dsub $2, $3, 65535
+ dsub $2, $3, 0x12345678
+ dsub $2, $3, 0x8888111112345678
+
+ .set push
+ .set noreorder
+ .set nomacro
+ ld $2, 0
+ ld $2, 4
+ ld $2, ($0)
+ ld $2, 0($0)
+ ld $2, 4($0)
+ ld $2, 4($3)
+ ld $2, -32768($3)
+ ld $2, 32767($3)
+ .set pop
+
+ ldl $2, 0
+ ldl $2, 4
+ ldl $2, ($0)
+ ldl $2, 0($0)
+ ldl $2, 4($0)
+ ldl $2, 4($3)
+ ldl $2, -512($3)
+ ldl $2, 511($3)
+ ldl $2, -32768($3)
+ ldl $2, 0x12345678($3)
+
+ ldr $2, 0
+ ldr $2, 4
+ ldr $2, ($0)
+ ldr $2, 0($0)
+ ldr $2, 4($0)
+ ldr $2, 4($3)
+ ldr $2, -512($3)
+ ldr $2, 511($3)
+ ldr $2, -32768($3)
+ ldr $2, 0x12345678($3)
+
+ lld $2, 0
+ lld $2, 4
+ lld $2, ($0)
+ lld $2, 0($0)
+ lld $2, 4($0)
+ lld $2, 4($3)
+ lld $2, -512($3)
+ lld $2, 511($3)
+ lld $2, -32768($3)
+ lld $2, 0x12345678($3)
+
+ lwu $2, 0
+ lwu $2, 4
+ lwu $2, ($0)
+ lwu $2, 0($0)
+ lwu $2, 4($0)
+ lwu $2, 4($3)
+ lwu $2, -512($3)
+ lwu $2, 511($3)
+ lwu $2, -32768($3)
+ lwu $2, 0x12345678($3)
+
+ scd $2, 0
+ scd $2, 4
+ scd $2, ($0)
+ scd $2, 0($0)
+ scd $2, 4($0)
+ scd $2, 4($3)
+ scd $2, -512($3)
+ scd $2, 511($3)
+ scd $2, -32768($3)
+ scd $2, 0x12345678($3)
+
+ .set push
+ .set noreorder
+ .set nomacro
+ sd $2, 0
+ sd $2, 4
+ sd $2, ($0)
+ sd $2, 0($0)
+ sd $2, 4($0)
+ sd $2, 4($3)
+ sd $2, -32768($3)
+ sd $2, 32767($3)
+ .set pop
+
+ sdl $2, 0
+ sdl $2, 4
+ sdl $2, ($0)
+ sdl $2, 0($0)
+ sdl $2, 4($0)
+ sdl $2, 4($3)
+ sdl $2, -32768($3)
+ sdl $2, 32767($3)
+ sdl $2, 0x12345678($3)
+
+ sdr $2, 0
+ sdr $2, 4
+ sdr $2, ($0)
+ sdr $2, 0($0)
+ sdr $2, 4($0)
+ sdr $2, 4($3)
+ sdr $2, -32768($3)
+ sdr $2, 32767($3)
+ sdr $2, 0x12345678($3)
+
+ ldm $s0, 0
+ ldm $s0, 4
+ ldm $s0, ($5)
+ ldm $s0, 2047($5)
+ ldm $s0-$s1, 2047($5)
+ ldm $s0-$s2, 2047($5)
+ ldm $s0-$s3, 2047($5)
+ ldm $s0-$s4, 2047($5)
+ ldm $s0-$s5, 2047($5)
+ ldm $s0-$s6, 2047($5)
+ ldm $s0-$s7, 2047($5)
+ ldm $s0-$s8, 2047($5)
+ ldm $ra, 2047($5)
+ ldm $s0,$ra, ($5)
+ ldm $s0-$s1,$ra, ($5)
+ ldm $s0-$s2,$ra, ($5)
+ ldm $s0-$s3,$ra, ($5)
+ ldm $s0-$s4,$ra, ($5)
+ ldm $s0-$s5,$ra, ($5)
+ ldm $s0-$s6,$ra, ($5)
+ ldm $s0-$s7,$ra, ($5)
+ ldm $s0-$s8,$ra, ($5)
+ ldm $s0, -32768($0)
+ ldm $s0, 32767($0)
+ ldm $s0, 0($0)
+ ldm $s0, 65535($0)
+ ldm $s0, -32768($29)
+ ldm $s0, 32767($29)
+ ldm $s0, 0($29)
+ ldm $s0, 65535($29)
+ ldm $s0, 0x12345678($29)
+
+ ldp $2, 0
+ ldp $2, 4
+ ldp $2, ($29)
+ ldp $2, 0($29)
+ ldp $2, -2048($3)
+ ldp $2, 2047($3)
+ ldp $2, -32768($3)
+ ldp $2, 32767($3)
+ ldp $2, 0($3)
+ ldp $2, 65535($3)
+ ldp $2, -32768($0)
+ ldp $2, 32767($0)
+ ldp $2, 65535($0)
+ ldp $2, 0x12345678($0)
+
+ sdm $s0, 0
+ sdm $s0, 4
+ sdm $s0, ($5)
+ sdm $s0, 2047($5)
+ sdm $s0-$s1, 2047($5)
+ sdm $s0-$s2, 2047($5)
+ sdm $s0-$s3, 2047($5)
+ sdm $s0-$s4, 2047($5)
+ sdm $s0-$s5, 2047($5)
+ sdm $s0-$s6, 2047($5)
+ sdm $s0-$s7, 2047($5)
+ sdm $s0-$s8, 2047($5)
+ sdm $ra, 2047($5)
+ sdm $s0,$ra, ($5)
+ sdm $s0-$s1,$ra, ($5)
+ sdm $s0-$s2,$ra, ($5)
+ sdm $s0-$s3,$ra, ($5)
+ sdm $s0-$s4,$ra, ($5)
+ sdm $s0-$s5,$ra, ($5)
+ sdm $s0-$s6,$ra, ($5)
+ sdm $s0-$s7,$ra, ($5)
+ sdm $s0-$s8,$ra, ($5)
+ sdm $s0, -32768($0)
+ sdm $s0, 32767($0)
+ sdm $s0, 0($0)
+ sdm $s0, 65535($0)
+ sdm $s0, -32768($29)
+ sdm $s0, 32767($29)
+ sdm $s0, 0($29)
+ sdm $s0, 65535($29)
+ sdm $s0, 0x12345678($29)
+
+ sdp $2, 0
+ sdp $2, 4
+ sdp $2, ($29)
+ sdp $2, 0($29)
+ sdp $2, -2048($3)
+ sdp $2, 2047($3)
+ sdp $2, -32768($3)
+ sdp $2, 32767($3)
+ sdp $2, 0($3)
+ sdp $2, 65535($3)
+ sdp $2, -32768($0)
+ sdp $2, 32767($0)
+ sdp $2, 65535($0)
+ sdp $2, 0x12345678($0)
+
+ uld $3, 0
+ uld $3, ($0)
+ uld $3, 4
+ uld $3, 4($0)
+ uld $3, 2047
+ uld $3, -2048
+ uld $3, 2048
+ uld $3, -2049
+ uld $3, 32753($0)
+ uld $3, -32768($0)
+ uld $3, 65535($0)
+ uld $3, 0xffff0000($0)
+ uld $3, 0xffff8000($0)
+ uld $3, 0xffff0001($0)
+ uld $3, 0xffff8001($0)
+ uld $3, 0xf0000000($0)
+ uld $3, 0xffffffff($0)
+ uld $3, 0x12345678($0)
+ uld $3, 0($4)
+ uld $3, 4($4)
+ uld $3, 2047($4)
+ uld $3, -2048($4)
+ uld $3, 2048($4)
+ uld $3, -2049($4)
+ uld $3, 32753($4)
+ uld $3, -32768($4)
+ uld $3, 65535($4)
+ uld $3, 0xffff0000($4)
+ uld $3, 0xffff8000($4)
+ uld $3, 0xffff0001($4)
+ uld $3, 0xffff8001($4)
+ uld $3, 0xf0000000($4)
+ uld $3, 0xffffffff($4)
+ uld $3, 0x12345678($4)
+
+ usd $3, 0
+ usd $3, ($0)
+ usd $3, 4
+ usd $3, 4($0)
+ usd $3, 2047
+ usd $3, -2048
+ usd $3, 2048
+ usd $3, -2049
+ usd $3, 32753($0)
+ usd $3, -32768($0)
+ usd $3, 65535($0)
+ usd $3, 0xffff0000($0)
+ usd $3, 0xffff8000($0)
+ usd $3, 0xffff0001($0)
+ usd $3, 0xffff8001($0)
+ usd $3, 0xf0000000($0)
+ usd $3, 0xffffffff($0)
+ usd $3, 0x12345678($0)
+ usd $3, 0($4)
+ usd $3, 4($4)
+ usd $3, 2047($4)
+ usd $3, -2048($4)
+ usd $3, 2048($4)
+ usd $3, -2049($4)
+ usd $3, 32753($4)
+ usd $3, -32768($4)
+ usd $3, 65535($4)
+ usd $3, 0xffff0000($4)
+ usd $3, 0xffff8000($4)
+ usd $3, 0xffff0001($4)
+ usd $3, 0xffff8001($4)
+ usd $3, 0xf0000000($4)
+ usd $3, 0xffffffff($4)
+ usd $3, 0x12345678($4)
+
+ ldl $16, %lo(test)($3)
+ ldr $16, %lo(test)($3)
+ lld $16, %lo(test)($3)
+ lwu $16, %lo(test)($3)
+ scd $16, %lo(test)($3)
+ sdl $16, %lo(test)($3)
+ sdr $16, %lo(test)($3)
+ ldm $16, %lo(test)($3)
+ ldp $16, %lo(test)($3)
+ sdm $16, %lo(test)($3)
+ sdp $16, %lo(test)($3)
+ ldc2 $16, %lo(test)($3)
+ sdc2 $16, %lo(test)($3)
+
+ .end test_mips64
+
+ .set reorder
+ .ent test_delay_slot
+test_delay_slot:
+ bal test_delay_slot
+ bgezal $3, test_delay_slot
+ bltzal $3, test_delay_slot
+ bgezall $3, test_delay_slot
+ bltzall $3, test_delay_slot
+ jal test_delay_slot
+ jalx test_delay_slot
+ jalr16 $2
+ jalr32 $2
+ jr16 $2
+ jr32 $2
+ jalr.hb $2
+ jr.hb $2
+
+ jals test_delay_slot
+ jalrs16 $2
+ jalrs32 $2
+ jrs $2
+ jalrs.hb $2
+ jrs.hb $2
+
+ .end test_delay_slot
+
+ .set noreorder
+ .ent test_spec102
+test_spec102:
+ lw $2, -64<<2 ($28)
+ lw $3, -64<<2 ($28)
+ lw $4, -64<<2 ($28)
+ lw $5, -64<<2 ($28)
+ lw $6, -64<<2 ($28)
+ lw $7, -64<<2 ($28)
+ lw $16, -64<<2 ($28)
+ lw $17, -64<<2 ($28)
+ lw $17, -63<<2 ($28)
+ lw $17, -1<<2 ($28)
+ lw $17, 0<<2 ($28)
+ lw $17, 1<<2 ($28)
+ lw $17, 62<<2 ($28)
+ lw $17, 63<<2 ($28)
+ lw $17, 64<<2 ($28)
+ lw $17, -65<<2 ($28)
+ lw $17, 1 ($28)
+ lw $17, 2 ($28)
+ lw $17, 3 ($28)
+ lw $17, -1 ($28)
+ lw $17, -2 ($28)
+ lw $17, -3 ($28)
+ lw $17, 0 ($27)
+
+ addiu $2, $pc, 0
+ addiu $3, $pc, 0
+ addiu $4, $pc, 0
+ addiu $5, $pc, 0
+ addiu $6, $pc, 0
+ addiu $7, $pc, 0
+ addiu $16, $pc, 0
+ addiu $17, $pc, 0
+ addiu $17, $pc, 4194303 << 2
+ addiu $17, $pc, -4194304 << 2
+ addiupc $2, 0
+ addiupc $3, 0
+ addiupc $4, 0
+ addiupc $5, 0
+ addiupc $6, 0
+ addiupc $7, 0
+ addiupc $16, 0
+ addiupc $17, 0
+ addiupc $17, 4194303 << 2
+ addiupc $17, -4194304 << 2
+
+ .end test_spec102
+
+ .set noreorder
+ .ent test_spec107
+test_spec107:
+ movep $5, $6, $0, $0
+ movep $5, $7, $0, $0
+ movep $6, $7, $0, $0
+ movep $4, $21, $0, $0
+ movep $4, $22, $0, $0
+ movep $4, $5, $0, $0
+ movep $4, $6, $0, $0
+ movep $4, $7, $0, $0
+ movep $4, $7, $17, $0
+ movep $4, $7, $2, $0
+ movep $4, $7, $3, $0
+ movep $4, $7, $16, $0
+ movep $4, $7, $18, $0
+ movep $4, $7, $19, $0
+ movep $4, $7, $20, $0
+ movep $4, $7, $20, $17
+ movep $4, $7, $20, $2
+ movep $4, $7, $20, $3
+ movep $4, $7, $20, $16
+ movep $4, $7, $20, $18
+ movep $4, $7, $20, $19
+ movep $4, $7, $20, $20
+ bals test_spec107
+ nop
+ bgezals $2, test_spec107
+ nop
+ bltzals $2, test_spec107
+ nop
+ bal test_spec107
+ nop
+ bgezal $2, test_spec107
+ nop
+ bltzal $2, test_spec107
+ nop
+
+ .end test_spec107
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS abs
+#source: abs.s
+#as: -32
+
+# Test the abs macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4044 fffe bgez a0,[0-9a-f]+ <foo>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0080 2190 neg a0,a0
+[0-9a-f]+ <[^>]*> 4045 fffe bgez a1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c85 move a0,a1
+[0-9a-f]+ <[^>]*> 00a0 2190 neg a0,a1
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS add
+#source: add.s
+#as: -32
+
+# Test the add macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1084 0000 addi a0,a0,0
+[0-9a-f]+ <[^>]*> 1084 0001 addi a0,a0,1
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 0024 2110 add a0,a0,at
+[0-9a-f]+ <[^>]*> 1084 8000 addi a0,a0,-32768
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 0024 2110 add a0,a0,at
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 0024 2110 add a0,a0,at
+[0-9a-f]+ <[^>]*> 3084 0001 addiu a0,a0,1
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS ALNV.PS instruction branch swapping
+#as: -32
+#source: alnv_ps-swap.s
+
+# Check that a register dependency between ALNV.PS and the following
+# branch prevents from branch swapping (microMIPS).
+
+# Note that currently swapping of ALNV.PS in microMIPS code is disabled
+# altogether.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
+([0-9a-f]+) <[^>]*> cfff b \1 <foo\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <foo\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
+([0-9a-f]+) <[^>]*> 4023 fffe bltzal v1,\1 <foo\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
+[0-9a-f]+ <[^>]*> 45c3 jalr v1
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
+[0-9a-f]+ <[^>]*> 0083 0f3c jalr a0,v1
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1
+[0-9a-f]+ <[^>]*> 007f 0f3c jalr v1,ra
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
+([0-9a-f]+) <[^>]*> cfff b \1 <foo\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
+([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <foo\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
+([0-9a-f]+) <[^>]*> 4023 fffe bltzal v1,\1 <foo\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
+[0-9a-f]+ <[^>]*> 45c3 jalr v1
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
+[0-9a-f]+ <[^>]*> 0083 0f3c jalr a0,v1
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra
+[0-9a-f]+ <[^>]*> 007f 0f3c jalr v1,ra
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS and
+#source: and.s
+#as: -32
+
+# Test the and macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> d084 0000 andi a0,a0,0x0
+[0-9a-f]+ <[^>]*> d084 0001 andi a0,a0,0x1
+[0-9a-f]+ <[^>]*> d084 8000 andi a0,a0,0x8000
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 0024 2250 and a0,a0,at
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 0024 2250 and a0,a0,at
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 0024 2250 and a0,a0,at
+[0-9a-f]+ <[^>]*> 5085 0000 ori a0,a1,0x0
+[0-9a-f]+ <[^>]*> 0004 22d0 not a0,a0
+[0-9a-f]+ <[^>]*> 5085 0001 ori a0,a1,0x1
+[0-9a-f]+ <[^>]*> 0004 22d0 not a0,a0
+[0-9a-f]+ <[^>]*> 5085 8000 ori a0,a1,0x8000
+[0-9a-f]+ <[^>]*> 0004 22d0 not a0,a0
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 0025 22d0 nor a0,a1,at
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 0025 22d0 nor a0,a1,at
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 0025 22d0 nor a0,a1,at
+[0-9a-f]+ <[^>]*> 5085 0000 ori a0,a1,0x0
+[0-9a-f]+ <[^>]*> 7085 0000 xori a0,a1,0x0
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS beq
+#source: beq.s
+#as: -32
+
+# Test the beq macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 94a4 fffe beq a0,a1,0+0000 <text_label>
+ 0: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9404 fffe beqz a0,0+0006 <text_label\+0x6>
+ 6: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 3020 0001 li at,1
+[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+0010 <text_label\+0x10>
+ 10: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+001a <text_label\+0x1a>
+ 1a: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+0024 <text_label\+0x24>
+ 24: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+002e <text_label\+0x2e>
+ 2e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+003c <text_label\+0x3c>
+ 3c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b404 fffe bnez a0,0+0042 <text_label\+0x42>
+ 42: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
+[0-9a-f]+ <[^>]*> 9400 fffe b 00020048 <text_label\+0x20048>
+ 20048: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0002004e <text_label\+0x2004e>
+ 2004e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS bge
+#source: bge.s
+#as: -32
+
+# Test the bge macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0004 <text_label\+0x4>
+ 4: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4044 fffe bgez a0,0+000a <text_label\+0xa>
+ a: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4085 fffe blez a1,0+0010 <text_label\+0x10>
+ 10: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4044 fffe bgez a0,0+0016 <text_label\+0x16>
+ 16: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 40c4 fffe bgtz a0,0+001c <text_label\+0x1c>
+ 1c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9024 0002 slti at,a0,2
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0026 <text_label\+0x26>
+ 26: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0034 <text_label\+0x34>
+ 34: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9024 8000 slti at,a0,-32768
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+003e <text_label\+0x3e>
+ 3e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+004c <text_label\+0x4c>
+ 4c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+005e <text_label\+0x5e>
+ 5e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0068 <text_label\+0x68>
+ 68: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 40c4 fffe bgtz a0,0+006e <text_label\+0x6e>
+ 6e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4005 fffe bltz a1,0+0074 <text_label\+0x74>
+ 74: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 40c4 fffe bgtz a0,0+007a <text_label\+0x7a>
+ 7a: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0084 <text_label\+0x84>
+ 84: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+008e <text_label\+0x8e>
+ 8e: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS bgeu
+#source: bgeu.s
+#as: -32
+
+# Test the bgeu macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0004 <text_label\+0x4>
+ 4: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 94a0 fffe beq zero,a1,0+000a <text_label\+0xa>
+ a: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b404 fffe bnez a0,0+0010 <text_label\+0x10>
+ 10: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b024 0002 sltiu at,a0,2
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+001a <text_label\+0x1a>
+ 1a: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0028 <text_label\+0x28>
+ 28: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b024 8000 sltiu at,a0,-32768
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0032 <text_label\+0x32>
+ 32: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0040 <text_label\+0x40>
+ 40: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0052 <text_label\+0x52>
+ 52: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+005c <text_label\+0x5c>
+ 5c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b404 fffe bnez a0,0+0062 <text_label\+0x62>
+ 62: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b404 fffe bnez a0,0+0068 <text_label\+0x68>
+ 68: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0072 <text_label\+0x72>
+ 72: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+007c <text_label\+0x7c>
+ 7c: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS blt
+#source: blt.s
+#as: -32
+
+# Test the blt macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0004 <text_label\+0x4>
+ 4: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4004 fffe bltz a0,0+000a <text_label\+0xa>
+ a: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 40c5 fffe bgtz a1,0+0010 <text_label\+0x10>
+ 10: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4004 fffe bltz a0,0+0016 <text_label\+0x16>
+ 16: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4084 fffe blez a0,0+001c <text_label\+0x1c>
+ 1c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9024 0002 slti at,a0,2
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0026 <text_label\+0x26>
+ 26: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0034 <text_label\+0x34>
+ 34: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9024 8000 slti at,a0,-32768
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+003e <text_label\+0x3e>
+ 3e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+004c <text_label\+0x4c>
+ 4c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+005e <text_label\+0x5e>
+ 5e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0068 <text_label\+0x68>
+ 68: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4084 fffe blez a0,0+006e <text_label\+0x6e>
+ 6e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4045 fffe bgez a1,0+0074 <text_label\+0x74>
+ 74: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4084 fffe blez a0,0+007a <text_label\+0x7a>
+ 7a: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0084 <text_label\+0x84>
+ 84: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+008e <text_label\+0x8e>
+ 8e: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS bltu
+#source: bltu.s
+#as: -32
+
+# Test the bltu macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0004 <text_label\+0x4>
+ 4: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b4a0 fffe bne zero,a1,0+000a <text_label\+0xa>
+ a: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9404 fffe beqz a0,0+0010 <text_label\+0x10>
+ 10: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b024 0002 sltiu at,a0,2
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+001a <text_label\+0x1a>
+ 1a: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0028 <text_label\+0x28>
+ 28: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b024 8000 sltiu at,a0,-32768
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0032 <text_label\+0x32>
+ 32: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0040 <text_label\+0x40>
+ 40: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0052 <text_label\+0x52>
+ 52: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+005c <text_label\+0x5c>
+ 5c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9404 fffe beqz a0,0+0062 <text_label\+0x62>
+ 62: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9404 fffe beqz a0,0+0068 <text_label\+0x68>
+ 68: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0072 <text_label\+0x72>
+ 72: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+007c <text_label\+0x7c>
+ 7c: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-likely instructions
+#source: branch-likely.s
+#as: -32
+
+# Check branch-likely instructions (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 9404 fffe beqz a0,0+0000 <text_label>
+ 0: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b404 fffe bnez a0,0+0006 <text_label\+0x6>
+ 6: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9404 fffe beqz a0,0+000c <text_label\+0xc>
+ c: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> b404 fffe bnez a0,0+0012 <text_label\+0x12>
+ 12: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+001c <text_label\+0x1c>
+ 1c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0026 <text_label\+0x26>
+ 26: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0030 <text_label\+0x30>
+ 30: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+003a <text_label\+0x3a>
+ 3a: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0044 <text_label\+0x44>
+ 44: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+004e <text_label\+0x4e>
+ 4e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0058 <text_label\+0x58>
+ 58: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0062 <text_label\+0x62>
+ 62: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+006c <text_label\+0x6c>
+ 6c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0076 <text_label\+0x76>
+ 76: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0080 <text_label\+0x80>
+ 80: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+008a <text_label\+0x8a>
+ 8a: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0094 <text_label\+0x94>
+ 94: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+009e <text_label\+0x9e>
+ 9e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
+[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+00a8 <text_label\+0xa8>
+ a8: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
+[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+00b2 <text_label\+0xb2>
+ b2: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-1
+#source: branch-misc-1.s
+#as: -32
+
+# Test the branches to local symbols in current file (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+003c <x>
+ 3c: R_MICROMIPS_PC16_S1 l1
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0044 <x\+0x8>
+ 44: R_MICROMIPS_PC16_S1 l2
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+004c <x\+0x10>
+ 4c: R_MICROMIPS_PC16_S1 l3
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0054 <x\+0x18>
+ 54: R_MICROMIPS_PC16_S1 l4
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+005c <x\+0x20>
+ 5c: R_MICROMIPS_PC16_S1 l5
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0064 <x\+0x28>
+ 64: R_MICROMIPS_PC16_S1 l6
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
+ \.\.\.
+ \.\.\.
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2-64
+#source: branch-misc-2.s
+#as: -64 -non_shared
+
+# Test the backward branches to global symbols in current file (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0040 <x\+0x4>
+ 3c: R_MICROMIPS_PC16_S1 g1\+0xf+fffc
+ 3c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 3c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0048 <x\+0xc>
+ 44: R_MICROMIPS_PC16_S1 g2\+0xf+fffc
+ 44: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 44: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0050 <x\+0x14>
+ 4c: R_MICROMIPS_PC16_S1 g3\+0xf+fffc
+ 4c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 4c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0058 <x\+0x1c>
+ 54: R_MICROMIPS_PC16_S1 g4\+0xf+fffc
+ 54: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 54: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0060 <x\+0x24>
+ 5c: R_MICROMIPS_PC16_S1 g5\+0xf+fffc
+ 5c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 5c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0068 <x\+0x2c>
+ 64: R_MICROMIPS_PC16_S1 g6\+0xf+fffc
+ 64: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 64: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> 9400 0000 b 0+00ac <g6\+0x4>
+ a8: R_MICROMIPS_PC16_S1 x1\+0xf+fffc
+ a8: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ a8: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 0000 b 0+00b2 <g6\+0xa>
+ ae: R_MICROMIPS_PC16_S1 x2\+0xf+fffc
+ ae: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ ae: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 0000 b 0+00b8 <g6\+0x10>
+ b4: R_MICROMIPS_PC16_S1 \.data\+0xf+fffc
+ b4: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ b4: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2
+#source: branch-misc-2.s
+#as: -32 -non_shared
+
+# Test the backward branches to global symbols in current file (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+003c <x>
+ 3c: R_MICROMIPS_PC16_S1 g1
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0044 <x\+0x8>
+ 44: R_MICROMIPS_PC16_S1 g2
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+004c <x\+0x10>
+ 4c: R_MICROMIPS_PC16_S1 g3
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0054 <x\+0x18>
+ 54: R_MICROMIPS_PC16_S1 g4
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+005c <x\+0x20>
+ 5c: R_MICROMIPS_PC16_S1 g5
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0064 <x\+0x28>
+ 64: R_MICROMIPS_PC16_S1 g6
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+00a8 <g6>
+ a8: R_MICROMIPS_PC16_S1 x1
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+00ae <g6\+0x6>
+ ae: R_MICROMIPS_PC16_S1 x2
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+00b4 <g6\+0xc>
+ b4: R_MICROMIPS_PC16_S1 \.Ldata
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2pic-64
+#source: branch-misc-2.s
+#as: -64 -call_shared
+
+# Test the backward branches to global symbols in current file (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0040 <x\+0x4>
+ 3c: R_MICROMIPS_PC16_S1 g1\+0xf+fffc
+ 3c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 3c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0048 <x\+0xc>
+ 44: R_MICROMIPS_PC16_S1 g2\+0xf+fffc
+ 44: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 44: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0050 <x\+0x14>
+ 4c: R_MICROMIPS_PC16_S1 g3\+0xf+fffc
+ 4c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 4c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0058 <x\+0x1c>
+ 54: R_MICROMIPS_PC16_S1 g4\+0xf+fffc
+ 54: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 54: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0060 <x\+0x24>
+ 5c: R_MICROMIPS_PC16_S1 g5\+0xf+fffc
+ 5c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 5c: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 0000 bal 0+0068 <x\+0x2c>
+ 64: R_MICROMIPS_PC16_S1 g6\+0xf+fffc
+ 64: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ 64: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> 9400 0000 b 0+00ac <g6\+0x4>
+ a8: R_MICROMIPS_PC16_S1 x1\+0xf+fffc
+ a8: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ a8: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 0000 b 0+00b2 <g6\+0xa>
+ ae: R_MICROMIPS_PC16_S1 x2\+0xf+fffc
+ ae: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ ae: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 0000 b 0+00b8 <g6\+0x10>
+ b4: R_MICROMIPS_PC16_S1 \.data\+0xf+fffc
+ b4: R_MIPS_NONE \*ABS\*\+0xf+fffc
+ b4: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2pic
+#source: branch-misc-2.s
+#as: -32 -call_shared
+
+# Test the backward branches to global symbols in current file (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+003c <x>
+ 3c: R_MICROMIPS_PC16_S1 g1
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0044 <x\+0x8>
+ 44: R_MICROMIPS_PC16_S1 g2
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+004c <x\+0x10>
+ 4c: R_MICROMIPS_PC16_S1 g3
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0054 <x\+0x18>
+ 54: R_MICROMIPS_PC16_S1 g4
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+005c <x\+0x20>
+ 5c: R_MICROMIPS_PC16_S1 g5
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 4060 fffe bal 0+0064 <x\+0x28>
+ 64: R_MICROMIPS_PC16_S1 g6
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+00a8 <g6>
+ a8: R_MICROMIPS_PC16_S1 x1
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+00ae <g6\+0x6>
+ ae: R_MICROMIPS_PC16_S1 x2
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+00b4 <g6\+0xc>
+ b4: R_MICROMIPS_PC16_S1 \.Ldata
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-4-64
+#as: -64
+#source: branch-misc-4.s
+
+# Verify PC-relative relocations do not overflow (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> 9400 0000 b [0-9a-f]+ <foo\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar\+0xf+fffc
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 0000 b [0-9a-f]+ <foo\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.init\+0x2
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
+
+Disassembly of section \.init:
+[0-9a-f]+ <[^>]*> 9400 0000 b [0-9a-f]+ <bar\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo\+0xf+fffc
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xf+fffc
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 0000 b [0-9a-f]+ <bar\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.text\+0x40002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x40002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x40002
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-4
+#as: -32
+#source: branch-misc-4.s
+
+# Verify PC-relative relocations do not overflow (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+([0-9a-f]+) <[^>]*> 9400 fffe b \1 <foo>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 9400 fffe b \1 <\.Lfoo>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.Lbar
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
+
+Disassembly of section \.init:
+([0-9a-f]+) <[^>]*> 9400 fffe b \1 <bar>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 9400 fffe b \1 <\.Lbar>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.Lfoo
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branches to self
+#as: -32
+#source: branch-self.s
+
+# Test various ways to request a branch to self (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+([0-9a-f]+) <[^>]*> e930 sw v0,0\(v1\)
+([0-9a-f]+) <[^>]*> cfff b \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> e930 sw v0,0\(v1\)
+([0-9a-f]+) <[^>]*> cfff b \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> e930 sw v0,0\(v1\)
+([0-9a-f]+) <[^>]*> cfff b \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> e930 sw v0,0\(v1\)
+([0-9a-f]+) <[^>]*> cfff b \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> e930 sw v0,0\(v1\)
+([0-9a-f]+) <[^>]*> cfff b \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> e930 sw v0,0\(v1\)
+([0-9a-f]+) <[^>]*> cfff b \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .*
+([0-9a-f]+) <[^>]*> 0c00 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS CACHE instruction
+#as: -32 --defsym micromips=1
+#source: cache.s
+
+# Check MIPS CACHE instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 20a2 67ff cache 0x5,2047\(v0\)
+[0-9a-f]+ <[^>]*> 20a3 6800 cache 0x5,-2048\(v1\)
+[0-9a-f]+ <[^>]*> 3020 1000 li at,4096
+[0-9a-f]+ <[^>]*> 0081 0950 addu at,at,a0
+[0-9a-f]+ <[^>]*> 20a1 6800 cache 0x5,-2048\(at\)
+[0-9a-f]+ <[^>]*> 3020 f000 li at,-4096
+[0-9a-f]+ <[^>]*> 00a1 0950 addu at,at,a1
+[0-9a-f]+ <[^>]*> 20a1 67ff cache 0x5,2047\(at\)
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 00c1 0950 addu at,at,a2
+[0-9a-f]+ <[^>]*> 20a1 6fff cache 0x5,-1\(at\)
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 00e1 0950 addu at,at,a3
+[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 0101 0950 addu at,at,t0
+[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 0121 0950 addu at,at,t1
+[0-9a-f]+ <[^>]*> 20a1 6fff cache 0x5,-1\(at\)
+[0-9a-f]+ <[^>]*> 5020 9000 li at,0x9000
+[0-9a-f]+ <[^>]*> 0141 0950 addu at,at,t2
+[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
+[0-9a-f]+ <[^>]*> 41a1 ffff lui at,0xffff
+[0-9a-f]+ <[^>]*> 5021 7000 ori at,at,0x7000
+[0-9a-f]+ <[^>]*> 0161 0950 addu at,at,t3
+[0-9a-f]+ <[^>]*> 20a1 6fff cache 0x5,-1\(at\)
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DADDI instruction
+#as: -32 --defsym micromips=1
+#source: daddi.s
+
+# Check MIPS DADDI instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5862 7fdc daddi v1,v0,511
+[0-9a-f]+ <[^>]*> 58a4 801c daddi a1,a0,-512
+[0-9a-f]+ <[^>]*> 3020 0200 li at,512
+[0-9a-f]+ <[^>]*> 5826 3910 dadd a3,a2,at
+[0-9a-f]+ <[^>]*> 3020 fdff li at,-513
+[0-9a-f]+ <[^>]*> 5828 4910 dadd t1,t0,at
+[0-9a-f]+ <[^>]*> 3020 7fff li at,32767
+[0-9a-f]+ <[^>]*> 582a 5910 dadd t3,t2,at
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 582c 6910 dadd t5,t4,at
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 582e 7910 dadd t7,t6,at
+[0-9a-f]+ <[^>]*> 41a1 ffff lui at,0xffff
+[0-9a-f]+ <[^>]*> 5021 7fff ori at,at,0x7fff
+[0-9a-f]+ <[^>]*> 5830 8910 dadd s1,s0,at
+[0-9a-f]+ <[^>]*> 5020 8200 li at,0x8200
+[0-9a-f]+ <[^>]*> 5832 9910 dadd s3,s2,at
+[0-9a-f]+ <[^>]*> 41a1 ffff lui at,0xffff
+[0-9a-f]+ <[^>]*> 5021 7dff ori at,at,0x7dff
+[0-9a-f]+ <[^>]*> 5834 a910 dadd s5,s4,at
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS dli
+#source: dli.s
+#as: -64
+
+# Test the dli macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 3080 0000 li a0,0
+[0-9a-f]+ <[^>]*> 3080 0001 li a0,1
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5080 8000 li a0,0x8000
+[0-9a-f]+ <[^>]*> 3080 8000 li a0,-32768
+[0-9a-f]+ <[^>]*> 41a4 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 41a4 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 5084 a5a5 ori a0,a0,0xa5a5
+[0-9a-f]+ <[^>]*> 5080 8000 li a0,0x8000
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 1234 ori a0,a0,0x1234
+[0-9a-f]+ <[^>]*> 41a4 ffff lui a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 0048 dsrl32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 41a4 ffff lui a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 0048 dsrl32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 6040 dsrl a0,a0,0xc
+[0-9a-f]+ <[^>]*> 41a4 8000 lui a0,0x8000
+[0-9a-f]+ <[^>]*> 5084 1234 ori a0,a0,0x1234
+[0-9a-f]+ <[^>]*> 3080 8000 li a0,-32768
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 1234 ori a0,a0,0x1234
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 5678 ori a0,a0,0x5678
+[0-9a-f]+ <[^>]*> 41a4 8000 lui a0,0x8000
+[0-9a-f]+ <[^>]*> 5084 1234 ori a0,a0,0x1234
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 5678 ori a0,a0,0x5678
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 3080 8765 li a0,-30875
+[0-9a-f]+ <[^>]*> 41a4 ffff lui a0,0xffff
+[0-9a-f]+ <[^>]*> 5084 4321 ori a0,a0,0x4321
+[0-9a-f]+ <[^>]*> 3080 fff0 li a0,-16
+[0-9a-f]+ <[^>]*> 3080 ff00 li a0,-256
+[0-9a-f]+ <[^>]*> 3080 f000 li a0,-4096
+[0-9a-f]+ <[^>]*> 41a4 ffff lui a0,0xffff
+[0-9a-f]+ <[^>]*> 41a4 fff0 lui a0,0xfff0
+[0-9a-f]+ <[^>]*> 41a4 ff00 lui a0,0xff00
+[0-9a-f]+ <[^>]*> 41a4 f000 lui a0,0xf000
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 0008 dsll32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 3080 fff0 li a0,-16
+[0-9a-f]+ <[^>]*> 5884 0008 dsll32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 3080 ff00 li a0,-256
+[0-9a-f]+ <[^>]*> 5884 0008 dsll32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 3080 f000 li a0,-4096
+[0-9a-f]+ <[^>]*> 5884 0008 dsll32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 5080 ffff li a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 8008 dsll32 a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5080 fff0 li a0,0xfff0
+[0-9a-f]+ <[^>]*> 5884 8008 dsll32 a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5080 ff00 li a0,0xff00
+[0-9a-f]+ <[^>]*> 5884 8008 dsll32 a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5080 f000 li a0,0xf000
+[0-9a-f]+ <[^>]*> 5884 8008 dsll32 a0,a0,0x10
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 2040 dsrl a0,a0,0x4
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 4040 dsrl a0,a0,0x8
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 6040 dsrl a0,a0,0xc
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 8040 dsrl a0,a0,0x10
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 a040 dsrl a0,a0,0x14
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 c040 dsrl a0,a0,0x18
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 e040 dsrl a0,a0,0x1c
+[0-9a-f]+ <[^>]*> 41a4 ffff lui a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 0048 dsrl32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 41a4 0fff lui a0,0xfff
+[0-9a-f]+ <[^>]*> 5084 ffff ori a0,a0,0xffff
+[0-9a-f]+ <[^>]*> 41a4 00ff lui a0,0xff
+[0-9a-f]+ <[^>]*> 5084 ffff ori a0,a0,0xffff
+[0-9a-f]+ <[^>]*> 41a4 000f lui a0,0xf
+[0-9a-f]+ <[^>]*> 5084 ffff ori a0,a0,0xffff
+[0-9a-f]+ <[^>]*> 5080 ffff li a0,0xffff
+[0-9a-f]+ <[^>]*> 3080 0fff li a0,4095
+[0-9a-f]+ <[^>]*> 3080 00ff li a0,255
+[0-9a-f]+ <[^>]*> 3080 000f li a0,15
+[0-9a-f]+ <[^>]*> 41a4 0003 lui a0,0x3
+[0-9a-f]+ <[^>]*> 5084 fffc ori a0,a0,0xfffc
+[0-9a-f]+ <[^>]*> 5080 ffff li a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 f000 dsll a0,a0,0x1e
+[0-9a-f]+ <[^>]*> 5080 ffff li a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 1008 dsll32 a0,a0,0x2
+[0-9a-f]+ <[^>]*> 5080 ffff li a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 3008 dsll32 a0,a0,0x6
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 0008 dsll32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 5884 5040 dsrl a0,a0,0xa
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 e000 dsll a0,a0,0x1c
+[0-9a-f]+ <[^>]*> 5884 5040 dsrl a0,a0,0xa
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 c000 dsll a0,a0,0x18
+[0-9a-f]+ <[^>]*> 5884 5040 dsrl a0,a0,0xa
+[0-9a-f]+ <[^>]*> 41a4 003f lui a0,0x3f
+[0-9a-f]+ <[^>]*> 5084 fc03 ori a0,a0,0xfc03
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 ffff ori a0,a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 c000 ori a0,a0,0xc000
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS ELF jal
+#source: jal.s
+#as: -32
+
+# Test the jal macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 45d9 jalr t9
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 0099 0f3c jalr a0,t9
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> f400 0000 jal 0+0000 <text_label>
+ e: R_MICROMIPS_26_S1 text_label
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> f400 0000 jal 0+0000 <text_label>
+ 16: R_MICROMIPS_26_S1 external_text_label
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> d400 0000 j 0+0000 <text_label>
+ 1e: R_MICROMIPS_26_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j 0+0000 <text_label>
+ 24: R_MICROMIPS_26_S1 external_text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -sr -j .text
+#name: MIPS ELF reloc 2
+#source: elf-rel2.s
+#as: -mabi=o64
+
+# Test the GPREL and LITERAL generation (microMIPS).
+# FIXME: really this should check that the contents of .sdata, .lit4,
+# and .lit8 are correct too.
+
+.*: +file format .*mips.*
+
+RELOCATION RECORDS FOR \[\.text\]:
+OFFSET [ ]+ TYPE VALUE
+0+0000000 R_MICROMIPS_LITERAL \.lit8
+0+0000004 R_MICROMIPS_LITERAL \.lit8
+0+0000008 R_MICROMIPS_LITERAL \.lit8
+0+000000c R_MICROMIPS_LITERAL \.lit4
+0+0000010 R_MICROMIPS_LITERAL \.lit4
+0+0000014 R_MICROMIPS_LITERAL \.lit4
+0+0000018 R_MICROMIPS_GPREL16 \.sdata
+0+000001c R_MICROMIPS_GPREL16 \.sdata
+0+0000020 R_MICROMIPS_GPREL16 \.sdata
+
+
+Contents of section \.text:
+ 0000 bc5c0000 bc5c0008 bc5c0010 9c5c0000 .*
+ 0010 9c5c0004 9c5c0008 fc5c0000 fc5c0004 .*
+ 0020 fc5c0008 .*
--- /dev/null
+#objdump: --prefix-addresses -dr --show-raw-insn
+#name: MIPS ELF reloc 4
+#source: elf-rel4.s
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 309c 0000 addiu a0,gp,0
+[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 a
+[0-9a-f]+ <[^>]*> 309c 0004 addiu a0,gp,4
+[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 a
+[0-9a-f]+ <[^>]*> 309c 0008 addiu a0,gp,8
+[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 a
+[0-9a-f]+ <[^>]*> 309c 000c addiu a0,gp,12
+[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 a
--- /dev/null
+#objdump: -sr -j .text
+#name: MIPS ELF reloc 2
+#source: elf-rel2.s
+#as: -mabi=o64
+
+# Test the GPREL and LITERAL generation (microMIPS).
+# FIXME: really this should check that the contents of .sdata, .lit4,
+# and .lit8 are correct too.
+
+.*: +file format .*mips.*
+
+RELOCATION RECORDS FOR \[\.text\]:
+OFFSET [ ]+ TYPE VALUE
+0+0000000 R_MICROMIPS_LITERAL \.lit8
+0+0000004 R_MICROMIPS_LITERAL \.lit8
+0+0000008 R_MICROMIPS_LITERAL \.lit8
+0+000000c R_MICROMIPS_LITERAL \.lit4
+0+0000010 R_MICROMIPS_LITERAL \.lit4
+0+0000014 R_MICROMIPS_LITERAL \.lit4
+0+0000018 R_MICROMIPS_GPREL16 \.sdata
+0+000001c R_MICROMIPS_GPREL16 \.sdata
+0+0000020 R_MICROMIPS_GPREL16 \.sdata
+
+
+Contents of section \.text:
+ 0000 5cbc0000 5cbc0800 5cbc1000 5c9c0000 .*
+ 0010 5c9c0400 5c9c0800 5cfc0000 5cfc0400 .*
+ 0020 5cfc0800 .*
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn --adjust-vma=0x55555550
+#name: MIPS jal mask 1.1
+#as: -32
+#source: jal-mask-1.s
+
+# Check address masks for JAL/J instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+55555550 <[^>]*> d400 0000 j 50000000 <[^>]*>
+55555554 <[^>]*> 0c00 nop
+55555556 <[^>]*> d555 5552 j 52aaaaa4 <[^>]*>
+5555555a <[^>]*> 0c00 nop
+5555555c <[^>]*> d6aa aaac j 55555558 <[^>]*>
+55555560 <[^>]*> 0c00 nop
+55555562 <[^>]*> d7ff fffe j 57fffffc <[^>]*>
+55555566 <[^>]*> 0c00 nop
+55555568 <[^>]*> f400 0000 jal 50000000 <[^>]*>
+5555556c <[^>]*> 0000 0000 nop
+55555570 <[^>]*> f555 5552 jal 52aaaaa4 <[^>]*>
+55555574 <[^>]*> 0000 0000 nop
+55555578 <[^>]*> f6aa aaac jal 55555558 <[^>]*>
+5555557c <[^>]*> 0000 0000 nop
+55555580 <[^>]*> f7ff fffe jal 57fffffc <[^>]*>
+55555584 <[^>]*> 0000 0000 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn --adjust-vma=0xaaaaaaa0
+#name: MIPS jal mask 1.2
+#as: -32
+#source: jal-mask-1.s
+
+# Check address masks for JAL/J instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+aaaaaaa0 <[^>]*> d400 0000 j a8000000 <[^>]*>
+aaaaaaa4 <[^>]*> 0c00 nop
+aaaaaaa6 <[^>]*> d555 5552 j aaaaaaa4 <[^>]*>
+aaaaaaaa <[^>]*> 0c00 nop
+aaaaaaac <[^>]*> d6aa aaac j ad555558 <[^>]*>
+aaaaaab0 <[^>]*> 0c00 nop
+aaaaaab2 <[^>]*> d7ff fffe j affffffc <[^>]*>
+aaaaaab6 <[^>]*> 0c00 nop
+aaaaaab8 <[^>]*> f400 0000 jal a8000000 <[^>]*>
+aaaaaabc <[^>]*> 0000 0000 nop
+aaaaaac0 <[^>]*> f555 5552 jal aaaaaaa4 <[^>]*>
+aaaaaac4 <[^>]*> 0000 0000 nop
+aaaaaac8 <[^>]*> f6aa aaac jal ad555558 <[^>]*>
+aaaaaacc <[^>]*> 0000 0000 nop
+aaaaaad0 <[^>]*> f7ff fffe jal affffffc <[^>]*>
+aaaaaad4 <[^>]*> 0000 0000 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS jal-svr4pic noreorder
+#as: -32 -KPIC
+#source: jal-svr4pic-noreorder.s
+
+# Test the jal macro with -KPIC and `.set noreorder' (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 41bc 0000 lui gp,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 _gp_disp
+[0-9a-f]+ <[^>]*> 339c 0000 addiu gp,gp,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 _gp_disp
+[0-9a-f]+ <[^>]*> 033c e150 addu gp,gp,t9
+[0-9a-f]+ <[^>]*> fb9d 0000 sw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 45f9 jalrs t9
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 0099 4f3c jalrs a0,t9
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3339 0001 addiu t9,t9,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 03f9 4f3c jalrs t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_CALL16 weak_text_label
+[0-9a-f]+ <[^>]*> 03f9 4f3c jalrs t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR weak_text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_CALL16 external_text_label
+[0-9a-f]+ <[^>]*> 03f9 4f3c jalrs t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR external_text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+([0-9a-f]+) <[^>]*> 9400 fffe b \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS jal-svr4pic
+#as: -32 -KPIC
+#source: jal-svr4pic.s
+
+# Test the jal macro with -KPIC (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 41bc 0000 lui gp,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 _gp_disp
+[0-9a-f]+ <[^>]*> 339c 0000 addiu gp,gp,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 _gp_disp
+[0-9a-f]+ <[^>]*> 033c e150 addu gp,gp,t9
+[0-9a-f]+ <[^>]*> fb9d 0000 sw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 45f9 jalrs t9
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 0099 4f3c jalrs a0,t9
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3339 0001 addiu t9,t9,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 03f9 4f3c jalrs t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_CALL16 weak_text_label
+[0-9a-f]+ <[^>]*> 03f9 4f3c jalrs t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR weak_text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_CALL16 external_text_label
+[0-9a-f]+ <[^>]*> 03f9 4f3c jalrs t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR external_text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+([0-9a-f]+) <[^>]*> 9400 fffe b \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS lb-svr4pic-ilocks
+#source: lb-pic.s
+#as: -32 -KPIC
+
+# Test the lb macro with -KPIC (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1c80 0000 lb a0,0\(zero\)
+[0-9a-f]+ <[^>]*> 1c80 0001 lb a0,1\(zero\)
+[0-9a-f]+ <[^>]*> 41a4 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 1c84 8000 lb a0,-32768\(a0\)
+[0-9a-f]+ <[^>]*> 1c80 8000 lb a0,-32768\(zero\)
+[0-9a-f]+ <[^>]*> 41a4 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> 41a4 0002 lui a0,0x2
+[0-9a-f]+ <[^>]*> 1c84 a5a5 lb a0,-23131\(a0\)
+[0-9a-f]+ <[^>]*> 1c85 0000 lb a0,0\(a1\)
+[0-9a-f]+ <[^>]*> 1c85 0001 lb a0,1\(a1\)
+[0-9a-f]+ <[^>]*> 41a4 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 8000 lb a0,-32768\(a0\)
+[0-9a-f]+ <[^>]*> 1c85 8000 lb a0,-32768\(a1\)
+[0-9a-f]+ <[^>]*> 41a4 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> 41a4 0002 lui a0,0x2
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 a5a5 lb a0,-23131\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.data
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.data
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_data_label
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_data_label
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_common
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_common
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.bss
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.bss
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.bss
+[0-9a-f]+ <[^>]*> 3084 03e8 addiu a0,a0,1000
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.bss
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.data
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.data
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_data_label
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_data_label
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_common
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_common
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.bss
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.bss
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.bss
+[0-9a-f]+ <[^>]*> 3084 03e8 addiu a0,a0,1000
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.bss
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.data
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.data
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_data_label
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_data_label
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.bss
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.bss
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.bss
+[0-9a-f]+ <[^>]*> 3084 03e8 addiu a0,a0,1000
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.bss
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.data
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.data
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_data_label
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_data_label
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.bss
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.bss
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.bss
+[0-9a-f]+ <[^>]*> 3084 03e8 addiu a0,a0,1000
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.bss
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS li
+#source: li.s
+#as: -32
+
+# Test the li macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> ee00 li a0,0
+[0-9a-f]+ <[^>]*> ee01 li a0,1
+[0-9a-f]+ <[^>]*> 5080 8000 li a0,0x8000
+[0-9a-f]+ <[^>]*> 3080 8000 li a0,-32768
+[0-9a-f]+ <[^>]*> 41a4 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 41a4 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 5084 a5a5 ori a0,a0,0xa5a5
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DWARF-2 location information with branch swapping disassembly
+#as: -32
+#source: loc-swap.s
+
+# Check branch swapping with DWARF-2 location information (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0c90 move a0,s0
+[0-9a-f]+ <[^>]*> 4584 jr a0
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0ff0 move ra,s0
+[0-9a-f]+ <[^>]*> 4584 jr a0
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c90 move a0,s0
+[0-9a-f]+ <[^>]*> 459f jr ra
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0ff0 move ra,s0
+[0-9a-f]+ <[^>]*> 459f jr ra
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c90 move a0,s0
+[0-9a-f]+ <[^>]*> 45c4 jalr a0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 0ff0 move ra,s0
+[0-9a-f]+ <[^>]*> 45c4 jalr a0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 0c90 move a0,s0
+[0-9a-f]+ <[^>]*> f400 0000 jal 0+0000 <foo>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+[0-9a-f]+ <[^>]*> 0ff0 move ra,s0
+[0-9a-f]+ <[^>]*> f400 0000 jal 0+0000 <foo>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
--- /dev/null
+#PROG: readelf
+#readelf: -wl
+#name: MIPS DWARF-2 location information with branch swapping
+#as: -32
+#source: loc-swap.s
+
+# Verify that DWARF-2 location information for instructions reordered
+# into a branch delay slot is updated to point to the branch instead
+# (microMIPS).
+
+Raw dump of debug contents of section \.debug_line:
+
+ Offset: 0x0
+ Length: 67
+ DWARF Version: 2
+ Prologue Length: 33
+ Minimum Instruction Length: 1
+ Initial value of 'is_stmt': 1
+ Line Base: -5
+ Line Range: 14
+ Opcode Base: 13
+
+ Opcodes:
+ Opcode 1 has 0 args
+ Opcode 2 has 1 args
+ Opcode 3 has 1 args
+ Opcode 4 has 1 args
+ Opcode 5 has 1 args
+ Opcode 6 has 0 args
+ Opcode 7 has 0 args
+ Opcode 8 has 0 args
+ Opcode 9 has 1 args
+ Opcode 10 has 0 args
+ Opcode 11 has 0 args
+ Opcode 12 has 1 args
+
+ The Directory Table is empty\.
+
+ The File Name Table:
+ Entry Dir Time Size Name
+ 1 0 0 0 loc-swap\.s
+
+ Line Number Statements:
+ Extended opcode 2: set Address to 0x1
+ Special opcode 11: advance Address by 0 to 0x1 and Line by 6 to 7
+ Special opcode 35: advance Address by 2 to 0x3 and Line by 2 to 9
+ Special opcode 64: advance Address by 4 to 0x7 and Line by 3 to 12
+ Special opcode 35: advance Address by 2 to 0x9 and Line by 2 to 14
+ Special opcode 64: advance Address by 4 to 0xd and Line by 3 to 17
+ Special opcode 35: advance Address by 2 to 0xf and Line by 2 to 19
+ Special opcode 64: advance Address by 4 to 0x13 and Line by 3 to 22
+ Special opcode 35: advance Address by 2 to 0x15 and Line by 2 to 24
+ Special opcode 64: advance Address by 4 to 0x19 and Line by 3 to 27
+ Special opcode 35: advance Address by 2 to 0x1b and Line by 2 to 29
+ Special opcode 92: advance Address by 6 to 0x21 and Line by 3 to 32
+ Special opcode 35: advance Address by 2 to 0x23 and Line by 2 to 34
+ Special opcode 92: advance Address by 6 to 0x29 and Line by 3 to 37
+ Special opcode 35: advance Address by 2 to 0x2b and Line by 2 to 39
+ Special opcode 120: advance Address by 8 to 0x33 and Line by 3 to 42
+ Special opcode 35: advance Address by 2 to 0x35 and Line by 2 to 44
+ Advance PC by 23 to 0x4c
+ Extended opcode 1: End of Sequence
--- /dev/null
+#objdump: -dr --show-raw-insn -M reg-names=numeric
+#name: MIPS1 FP instructions
+#source: mips1-fp.s
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <foo>:
+[0-9a-f ]+: 5482 0030 add\.s \$f0,\$f2,\$f4
+[0-9a-f ]+: 5440 103b cfc1 \$2,\$0
+#pass
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS32 cop2 instructions
+#source: micromips@mips32-cp2.s
+#as: -32
+
+# Check MIPS32 cop2 instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4280 fffe bc2f 0+0000 <text_label>
+ 0: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 42a0 fffe bc2t 0+0006 <text_label\+0x6>
+ 6: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+000c <text_label\+0xc>
+ c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 42a0 fffe bc2t 0+0012 <.*>
+ 12: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4280 fffe bc2f 0+0018 <.*\+0x6>
+ 18: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+001e <.*\+0xc>
+ 1e: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0022 cd3c cfc2 at,\$2
+[0-9a-f]+ <[^>]*> 0009 1a2a cop2 0x12345
+[0-9a-f]+ <[^>]*> 0043 dd3c ctc2 v0,\$3
+[0-9a-f]+ <[^>]*> 0064 4d3c mfc2 v1,\$4
+[0-9a-f]+ <[^>]*> 00c7 5d3c mtc2 a2,\$7
+[0-9a-f]+ <[^>]*> 4280 fffe bc2f 0+0038 <.*\+0x14>
+ 38: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 42a4 fffe bc2t \$cc1,0+003e <.*\+0x1a>
+ 3e: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+0044 <.*\+0x20>
+ 44: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 42b8 fffe bc2t \$cc6,0+004a <.*>
+ 4a: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 429c fffe bc2f \$cc7,0+0050 <.*\+0x6>
+ 50: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b 0+0056 <.*\+0xc>
+ 56: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+# Source file to test assembly of MIPS32-derived microMIPS cop2 instructions.
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+ # Unprivileged coprocessor instructions.
+ # These tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
+
+ bc2f text_label
+ nop
+ bc2fl text_label
+ nop
+ bc2t text_label
+ nop
+ bc2tl text_label
+ nop
+ # XXX other BCzCond encodings not currently expressable.
+
+ cfc2 $1, $2
+ # Different cop2 range for microMIPS.
+ cop2 0x12345 # disassembles as c2 ...
+ ctc2 $2, $3
+
+ # No sel with cp2 for microMIPS.
+ mfc2 $3, $4
+ mtc2 $6, $7
+
+
+ # Cop2 branches with cond code number, like bc1t/f.
+ bc2f $cc0,text_label
+ nop
+ bc2fl $cc1,text_label
+ nop
+ bc2t $cc6,text_label
+ nop
+ bc2tl $cc7,text_label
+ nop
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS32 WAIT and SDBBP instructions
+#source: micromips@mips32-imm.s
+#as: -32
+
+# Check MIPS32 WAIT and SDBBP instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+[0-9a-f]+ <[^>]*> 03c3 937c wait 0x3c3
+[0-9a-f]+ <[^>]*> 03c3 db7c sdbbp 0x3c3
+ \.\.\.
--- /dev/null
+# Source file to test wide immediates with MIPS32 WAIT and SDBBP instructions
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+
+ # 10 bits accepted for microMIPS
+ wait 0x3c3
+ sdbbp 0x3c3
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS32 odd single-precision float registers
+#source: mips32-sf32.s
+#as: -32
+
+# Check MIPS32 instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 41a1 3f80 lui \$1,0x3f80
+[0-9a-f]+ <[^>]*> 5421 283b mtc1 \$1,\$f1
+[0-9a-f]+ <[^>]*> 9c7c 0000 lwc1 \$f3,0\(\$28\)
+[ ]*[0-9a-f]+: R_MICROMIPS_LITERAL \.lit4
+[0-9a-f]+ <[^>]*> 5461 2830 add\.s \$f5,\$f1,\$f3
+[0-9a-f]+ <[^>]*> 5507 137b cvt\.d\.s \$f8,\$f7
+[0-9a-f]+ <[^>]*> 5507 337b cvt\.d\.w \$f8,\$f7
+[0-9a-f]+ <[^>]*> 54e8 1b7b cvt\.s\.d \$f7,\$f8
+[0-9a-f]+ <[^>]*> 54e8 6b3b trunc\.w\.d \$f7,\$f8
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS32 instructions
+#source: mips32.s
+#as: -32
+
+# Check MIPS32 instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0022 4b3c clo at,v0
+[0-9a-f]+ <[^>]*> 0064 5b3c clz v1,a0
+[0-9a-f]+ <[^>]*> 00c5 cb3c madd a1,a2
+[0-9a-f]+ <[^>]*> 0107 db3c maddu a3,t0
+[0-9a-f]+ <[^>]*> 0149 eb3c msub t1,t2
+[0-9a-f]+ <[^>]*> 018b fb3c msubu t3,t4
+[0-9a-f]+ <[^>]*> 01ee 6a10 mul t5,t6,t7
+[0-9a-f]+ <[^>]*> 6090 2000 pref 0x4,0\(s0\)
+[0-9a-f]+ <[^>]*> 6091 27ff pref 0x4,2047\(s1\)
+[0-9a-f]+ <[^>]*> 6092 2800 pref 0x4,-2048\(s2\)
+[0-9a-f]+ <[^>]*> 0000 0800 ssnop
+[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
+[0-9a-f]+ <[^>]*> 20a2 67ff cache 0x5,2047\(v0\)
+[0-9a-f]+ <[^>]*> 20a3 6800 cache 0x5,-2048\(v1\)
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 0081 0950 addu at,at,a0
+[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 00a1 0950 addu at,at,a1
+[0-9a-f]+ <[^>]*> 20a1 6fff cache 0x5,-1\(at\)
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 20a1 6fff cache 0x5,-1\(at\)
+[0-9a-f]+ <[^>]*> 0000 f37c eret
+[0-9a-f]+ <[^>]*> 0000 037c tlbp
+[0-9a-f]+ <[^>]*> 0000 137c tlbr
+[0-9a-f]+ <[^>]*> 0000 237c tlbwi
+[0-9a-f]+ <[^>]*> 0000 337c tlbwr
+[0-9a-f]+ <[^>]*> 0000 937c wait
+[0-9a-f]+ <[^>]*> 0000 937c wait
+[0-9a-f]+ <[^>]*> 0345 937c wait 0x345
+[0-9a-f]+ <[^>]*> 4680 break
+[0-9a-f]+ <[^>]*> 4680 break
+[0-9a-f]+ <[^>]*> 0345 0007 break 0x345
+[0-9a-f]+ <[^>]*> 0048 d147 break 0x48,0x345
+[0-9a-f]+ <[^>]*> 46c0 sdbbp
+[0-9a-f]+ <[^>]*> 46c0 sdbbp
+[0-9a-f]+ <[^>]*> 0345 db7c sdbbp 0x345
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS MIPS32r2 cop2 instructions
+#as: -32
+
+# Check MIPS32 Release 2 (mips32r2) cop2 instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+[0-9a-f]+ <[^>]*> 022f 8d3c mfhc2 \$17,\$15
+[0-9a-f]+ <[^>]*> 022f 9d3c mthc2 \$17,\$15
+ \.\.\.
--- /dev/null
+# Source file to test assembly of MIPS32r2-derived microMIPS cop2 instructions.
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+ # cp2 instructions.
+
+ # Only register syntax with cp2 for microMIPS (and no sel).
+ mfhc2 $17, $15
+ mthc2 $17, $15
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS MIPS32r2 fp instructions
+#source: mips32r2-fp32.s
+#as: -32
+
+# Check MIPS32 Release 2 (mips32r2) FP instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5620 303b mfhc1 \$17,\$f0
+[0-9a-f]+ <[^>]*> 5620 383b mthc1 \$17,\$f0
+#pass
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS32r2 sync instructions
+#as: -32
+#source: mips32r2-sync.s
+
+# Check MIPS32r2 sync instructions assembly and disassembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0000 6b7c sync
+[0-9a-f]+ <[^>]*> 0002 6b7c sync 0x2
+[0-9a-f]+ <[^>]*> 0004 6b7c sync_wmb
+[0-9a-f]+ <[^>]*> 0008 6b7c sync 0x8
+[0-9a-f]+ <[^>]*> 0010 6b7c sync_mb
+[0-9a-f]+ <[^>]*> 0011 6b7c sync_acquire
+[0-9a-f]+ <[^>]*> 0012 6b7c sync_release
+[0-9a-f]+ <[^>]*> 0013 6b7c sync_rmb
+[0-9a-f]+ <[^>]*> 0018 6b7c sync 0x18
+[0-9a-f]+ <[^>]*> 0000 6b7c sync
+[0-9a-f]+ <[^>]*> 0002 6b7c sync 0x2
+[0-9a-f]+ <[^>]*> 0004 6b7c sync_wmb
+[0-9a-f]+ <[^>]*> 0008 6b7c sync 0x8
+[0-9a-f]+ <[^>]*> 0010 6b7c sync_mb
+[0-9a-f]+ <[^>]*> 0011 6b7c sync_acquire
+[0-9a-f]+ <[^>]*> 0012 6b7c sync_release
+[0-9a-f]+ <[^>]*> 0013 6b7c sync_rmb
+[0-9a-f]+ <[^>]*> 0018 6b7c sync 0x18
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS MIPS32r2 non-fp instructions
+#source: mips32r2.s
+#as: -32
+
+# Check MIPS32 Release 2 (mips32r2) *non-fp* instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0000 1800 ehb
+[0-9a-f]+ <[^>]*> 0085 39ac ext \$4,\$5,0x6,0x8
+[0-9a-f]+ <[^>]*> 0085 698c ins \$4,\$5,0x6,0x8
+[0-9a-f]+ <[^>]*> 03e8 1f3c jalr\.hb \$8
+[0-9a-f]+ <[^>]*> 0289 1f3c jalr\.hb \$20,\$9
+[0-9a-f]+ <[^>]*> 0008 1f3c jr\.hb \$8
+[0-9a-f]+ <[^>]*> 0140 6b3c rdhwr \$10,\$0
+[0-9a-f]+ <[^>]*> 0161 6b3c rdhwr \$11,\$1
+[0-9a-f]+ <[^>]*> 0182 6b3c rdhwr \$12,\$2
+[0-9a-f]+ <[^>]*> 01a3 6b3c rdhwr \$13,\$3
+[0-9a-f]+ <[^>]*> 01c4 6b3c rdhwr \$14,\$4
+[0-9a-f]+ <[^>]*> 01e5 6b3c rdhwr \$15,\$5
+[0-9a-f]+ <[^>]*> 032a e0c0 ror \$25,\$10,0x1c
+[0-9a-f]+ <[^>]*> 032a 20c0 ror \$25,\$10,0x4
+[0-9a-f]+ <[^>]*> 0080 c9d0 negu \$25,\$4
+[0-9a-f]+ <[^>]*> 0159 c8d0 rorv \$25,\$10,\$25
+[0-9a-f]+ <[^>]*> 0144 c8d0 rorv \$25,\$10,\$4
+[0-9a-f]+ <[^>]*> 0144 c8d0 rorv \$25,\$10,\$4
+[0-9a-f]+ <[^>]*> 00e7 2b3c seb \$7,\$7
+[0-9a-f]+ <[^>]*> 010a 2b3c seb \$8,\$10
+[0-9a-f]+ <[^>]*> 00e7 3b3c seh \$7,\$7
+[0-9a-f]+ <[^>]*> 010a 3b3c seh \$8,\$10
+[0-9a-f]+ <[^>]*> 420a 5555 synci 21845\(\$10\)
+[0-9a-f]+ <[^>]*> 00e7 7b3c wsbh \$7,\$7
+[0-9a-f]+ <[^>]*> 010a 7b3c wsbh \$8,\$10
+[0-9a-f]+ <[^>]*> 0000 477c di
+[0-9a-f]+ <[^>]*> 0000 477c di
+[0-9a-f]+ <[^>]*> 000a 477c di \$10
+[0-9a-f]+ <[^>]*> 0000 577c ei
+[0-9a-f]+ <[^>]*> 0000 577c ei
+[0-9a-f]+ <[^>]*> 000a 577c ei \$10
+[0-9a-f]+ <[^>]*> 0159 e17c rdpgpr \$10,\$25
+[0-9a-f]+ <[^>]*> 0159 f17c wrpgpr \$10,\$25
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS mips4 branch-likely instructions
+#source: mips4-branch-likely.s
+#as: -32
+
+# Test mips4 branch-likely instructions (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4384 fffe bc1f \$fcc1,0+0000 <text_label>
+ 0: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 43a8 fffe bc1t \$fcc2,0+0006 <text_label\+0x6>
+ 6: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS mips4 fp
+#source: mips4-fp.s
+#as: -32
+
+# Test mips4 fp instructions (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4380 fffe bc1f 0+0000 <text_label>
+ 0: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4384 fffe bc1f \$fcc1,0+0006 <text_label\+0x6>
+ 6: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 43a4 fffe bc1t \$fcc1,0+000c <text_label\+0xc>
+ c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 54c4 043c c\.f\.d \$f4,\$f6
+[0-9a-f]+ <[^>]*> 54c4 243c c\.f\.d \$fcc1,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 5485 10c8 ldxc1 \$f2,a0\(a1\)
+[0-9a-f]+ <[^>]*> 5485 1048 lwxc1 \$f2,a0\(a1\)
+[0-9a-f]+ <[^>]*> 54c4 0089 madd\.d \$f0,\$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 5402 5201 madd\.s \$f10,\$f8,\$f2,\$f0
+[0-9a-f]+ <[^>]*> 5485 817b movf a0,a1,\$fcc4
+[0-9a-f]+ <[^>]*> 5486 0220 movf\.d \$f4,\$f6,\$fcc0
+[0-9a-f]+ <[^>]*> 5486 0020 movf\.s \$f4,\$f6,\$fcc0
+[0-9a-f]+ <[^>]*> 54c6 2138 movn\.d \$f4,\$f6,a2
+[0-9a-f]+ <[^>]*> 54c6 2038 movn\.s \$f4,\$f6,a2
+[0-9a-f]+ <[^>]*> 5485 897b movt a0,a1,\$fcc4
+[0-9a-f]+ <[^>]*> 5486 0260 movt\.d \$f4,\$f6,\$fcc0
+[0-9a-f]+ <[^>]*> 5486 0060 movt\.s \$f4,\$f6,\$fcc0
+[0-9a-f]+ <[^>]*> 54c6 2178 movz\.d \$f4,\$f6,a2
+[0-9a-f]+ <[^>]*> 54c6 2078 movz\.s \$f4,\$f6,a2
+[0-9a-f]+ <[^>]*> 54c4 00a9 msub\.d \$f0,\$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 54c4 00a1 msub\.s \$f0,\$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 54c4 008a nmadd\.d \$f0,\$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 54c4 0082 nmadd\.s \$f0,\$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 54c4 00aa nmsub\.d \$f0,\$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 54c4 00a2 nmsub\.s \$f0,\$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 5485 21a0 prefx 0x4,a0\(a1\)
+[0-9a-f]+ <[^>]*> 5486 523b recip\.d \$f4,\$f6
+[0-9a-f]+ <[^>]*> 5486 123b recip\.s \$f4,\$f6
+[0-9a-f]+ <[^>]*> 5486 423b rsqrt\.d \$f4,\$f6
+[0-9a-f]+ <[^>]*> 5486 023b rsqrt\.s \$f4,\$f6
+[0-9a-f]+ <[^>]*> 5485 2108 sdxc1 \$f4,a0\(a1\)
+[0-9a-f]+ <[^>]*> 5485 2048 lwxc1 \$f4,a0\(a1\)
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS mips4 non-fp
+#source: mips4.s
+
+# Test mips4 *non-fp* instructions (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 00c6 2018 movn a0,a2,a2
+[0-9a-f]+ <[^>]*> 00c6 2058 movz a0,a2,a2
+[0-9a-f]+ <[^>]*> 6084 2000 pref 0x4,0\(a0\)
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS mips5 instructions
+#source: mips5.s
+#stderr: mips5.l
+
+# Check MIPS V instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5402 437b abs\.ps \$f0,\$f2
+[0-9a-f]+ <[^>]*> 54c4 1230 add\.ps \$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 5548 30d9 alnv\.ps \$f6,\$f8,\$f10,\$3
+[0-9a-f]+ <[^>]*> 5548 08bc c\.eq\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 48bc c\.eq\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 083c c\.f\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 483c c\.f\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0bbc c\.le\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4bbc c\.le\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0b3c c\.lt\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4b3c c\.lt\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0b7c c\.nge\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4b7c c\.nge\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0afc c\.ngl\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4afc c\.ngl\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0a7c c\.ngle\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4a7c c\.ngle\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0bfc c\.ngt\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4bfc c\.ngt\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 09bc c\.ole\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 49bc c\.ole\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 093c c\.olt\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 493c c\.olt\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0abc c\.seq\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4abc c\.seq\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0a3c c\.sf\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4a3c c\.sf\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 08fc c\.ueq\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 48fc c\.ueq\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 09fc c\.ule\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 49fc c\.ule\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 097c c\.ult\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 497c c\.ult\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 087c c\.un\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 487c c\.un\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 560e 6180 cvt\.ps\.s \$f12,\$f14,\$f16
+[0-9a-f]+ <[^>]*> 5612 213b cvt\.s\.pl \$f16,\$f18
+[0-9a-f]+ <[^>]*> 5654 293b cvt\.s\.pu \$f18,\$f20
+[0-9a-f]+ <[^>]*> 5485 a148 luxc1 \$f20,\$4\(\$5\)
+[0-9a-f]+ <[^>]*> 5758 a591 madd\.ps \$f20,\$f22,\$f24,\$f26
+[0-9a-f]+ <[^>]*> 571a 407b mov\.ps \$f24,\$f26
+[0-9a-f]+ <[^>]*> 575c 4420 movf\.ps \$f26,\$f28,\$fcc2
+[0-9a-f]+ <[^>]*> 547c d238 movn\.ps \$f26,\$f28,\$3
+[0-9a-f]+ <[^>]*> 579e 8460 movt\.ps \$f28,\$f30,\$fcc4
+[0-9a-f]+ <[^>]*> 54be e278 movz\.ps \$f28,\$f30,\$5
+[0-9a-f]+ <[^>]*> 5482 f031 msub\.ps \$f30,\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 54c4 12b0 mul\.ps \$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 54c8 4b7b neg\.ps \$f6,\$f8
+[0-9a-f]+ <[^>]*> 558a 3212 nmadd\.ps \$f6,\$f8,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 558a 3232 nmsub\.ps \$f6,\$f8,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 55cc 5080 pll\.ps \$f10,\$f12,\$f14
+[0-9a-f]+ <[^>]*> 5650 70c0 plu\.ps \$f14,\$f16,\$f18
+[0-9a-f]+ <[^>]*> 5692 8100 pul\.ps \$f16,\$f18,\$f20
+[0-9a-f]+ <[^>]*> 5716 a140 puu\.ps \$f20,\$f22,\$f24
+[0-9a-f]+ <[^>]*> 5758 b270 sub\.ps \$f22,\$f24,\$f26
+[0-9a-f]+ <[^>]*> 54c7 d188 suxc1 \$f26,\$6\(\$7\)
+[0-9a-f]+ <[^>]*> 558a 68bc c\.eq\.ps \$fcc3,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 575c 6420 movf\.ps \$f26,\$f28,\$fcc3
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS64 cop2 instructions
+#source: micromips@mips64-cp2.s
+#as: -32
+
+# Check MIPS64 cop2 instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+[0-9a-f]+ <[^>]*> 0064 6d3c dmfc2 v1,\$4
+[0-9a-f]+ <[^>]*> 00c7 7d3c dmtc2 a2,\$7
+ \.\.\.
--- /dev/null
+# Source file to test assembly of MIPS64-derived microMIPS cop2 instructions
+
+ .set noreorder
+ .set noat
+
+ .globl text_label .text
+text_label:
+
+ # Unprivileged coprocessor instructions.
+ # These tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
+
+ # No sel with cp2 for microMIPS.
+ dmfc2 $3, $4
+ dmtc2 $6, $7
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS64 instructions
+#source: mips64.s
+#as: -32
+
+# Check MIPS64 instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5822 4b3c dclo at,v0
+[0-9a-f]+ <[^>]*> 5864 5b3c dclz v1,a0
+#pass
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS MIPS64r2 instructions
+#source: mips64r2.s
+
+# Check MIPS64r2 instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5843 002c dext \$2,\$3,0x0,0x1
+[0-9a-f]+ <[^>]*> 5843 f82c dext \$2,\$3,0x0,0x20
+[0-9a-f]+ <[^>]*> 5843 0024 dextm \$2,\$3,0x0,0x21
+[0-9a-f]+ <[^>]*> 5843 f824 dextm \$2,\$3,0x0,0x40
+[0-9a-f]+ <[^>]*> 5843 07ec dext \$2,\$3,0x1f,0x1
+[0-9a-f]+ <[^>]*> 5843 ffec dext \$2,\$3,0x1f,0x20
+[0-9a-f]+ <[^>]*> 5843 07e4 dextm \$2,\$3,0x1f,0x21
+[0-9a-f]+ <[^>]*> 5843 0014 dextu \$2,\$3,0x20,0x1
+[0-9a-f]+ <[^>]*> 5843 f814 dextu \$2,\$3,0x20,0x20
+[0-9a-f]+ <[^>]*> 5843 07d4 dextu \$2,\$3,0x3f,0x1
+[0-9a-f]+ <[^>]*> 5843 5aa4 dextm \$2,\$3,0xa,0x2c
+[0-9a-f]+ <[^>]*> 5843 5a94 dextu \$2,\$3,0x2a,0xc
+[0-9a-f]+ <[^>]*> 5843 000c dins \$2,\$3,0x0,0x1
+[0-9a-f]+ <[^>]*> 5843 f80c dins \$2,\$3,0x0,0x20
+[0-9a-f]+ <[^>]*> 5843 0004 dinsm \$2,\$3,0x0,0x21
+[0-9a-f]+ <[^>]*> 5843 f804 dinsm \$2,\$3,0x0,0x40
+[0-9a-f]+ <[^>]*> 5843 ffcc dins \$2,\$3,0x1f,0x1
+[0-9a-f]+ <[^>]*> 5843 07c4 dinsm \$2,\$3,0x1f,0x2
+[0-9a-f]+ <[^>]*> 5843 ffc4 dinsm \$2,\$3,0x1f,0x21
+[0-9a-f]+ <[^>]*> 5843 0034 dinsu \$2,\$3,0x20,0x1
+[0-9a-f]+ <[^>]*> 5843 f834 dinsu \$2,\$3,0x20,0x20
+[0-9a-f]+ <[^>]*> 5843 fff4 dinsu \$2,\$3,0x3f,0x1
+[0-9a-f]+ <[^>]*> 5843 aa84 dinsm \$2,\$3,0xa,0x2c
+[0-9a-f]+ <[^>]*> 5843 aab4 dinsu \$2,\$3,0x2a,0xc
+[0-9a-f]+ <[^>]*> 5b2a e0c8 dror32 \$25,\$10,0x1c
+[0-9a-f]+ <[^>]*> 5b2a 20c0 dror \$25,\$10,0x4
+[0-9a-f]+ <[^>]*> 5b2a e0c0 dror \$25,\$10,0x1c
+[0-9a-f]+ <[^>]*> 5b2a 20c8 dror32 \$25,\$10,0x4
+[0-9a-f]+ <[^>]*> 5880 c9d0 dnegu \$25,\$4
+[0-9a-f]+ <[^>]*> 5959 c8d0 drorv \$25,\$10,\$25
+[0-9a-f]+ <[^>]*> 5944 c8d0 drorv \$25,\$10,\$4
+[0-9a-f]+ <[^>]*> 5b2a 20c8 dror32 \$25,\$10,0x4
+[0-9a-f]+ <[^>]*> 5944 c8d0 drorv \$25,\$10,\$4
+[0-9a-f]+ <[^>]*> 58e7 7b3c dsbh \$7,\$7
+[0-9a-f]+ <[^>]*> 590a 7b3c dsbh \$8,\$10
+[0-9a-f]+ <[^>]*> 58e7 fb3c dshd \$7,\$7
+[0-9a-f]+ <[^>]*> 590a fb3c dshd \$8,\$10
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS PREF instruction
+#as: -32 --defsym micromips=1 --defsym tpref=1
+#source: cache.s
+
+# Check MIPS PREF instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 60a2 27ff pref 0x5,2047\(v0\)
+[0-9a-f]+ <[^>]*> 60a3 2800 pref 0x5,-2048\(v1\)
+[0-9a-f]+ <[^>]*> 3020 1000 li at,4096
+[0-9a-f]+ <[^>]*> 0081 0950 addu at,at,a0
+[0-9a-f]+ <[^>]*> 60a1 2800 pref 0x5,-2048\(at\)
+[0-9a-f]+ <[^>]*> 3020 f000 li at,-4096
+[0-9a-f]+ <[^>]*> 00a1 0950 addu at,at,a1
+[0-9a-f]+ <[^>]*> 60a1 27ff pref 0x5,2047\(at\)
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 00c1 0950 addu at,at,a2
+[0-9a-f]+ <[^>]*> 60a1 2fff pref 0x5,-1\(at\)
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 00e1 0950 addu at,at,a3
+[0-9a-f]+ <[^>]*> 60a1 2000 pref 0x5,0\(at\)
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 0101 0950 addu at,at,t0
+[0-9a-f]+ <[^>]*> 60a1 2000 pref 0x5,0\(at\)
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 0121 0950 addu at,at,t1
+[0-9a-f]+ <[^>]*> 60a1 2fff pref 0x5,-1\(at\)
+[0-9a-f]+ <[^>]*> 5020 9000 li at,0x9000
+[0-9a-f]+ <[^>]*> 0141 0950 addu at,at,t2
+[0-9a-f]+ <[^>]*> 60a1 2000 pref 0x5,0\(at\)
+[0-9a-f]+ <[^>]*> 41a1 ffff lui at,0xffff
+[0-9a-f]+ <[^>]*> 5021 7000 ori at,at,0x7000
+[0-9a-f]+ <[^>]*> 0161 0950 addu at,at,t3
+[0-9a-f]+ <[^>]*> 60a1 2fff pref 0x5,-1\(at\)
+ \.\.\.
--- /dev/null
+#as: -KPIC -32 -relax-branch --defsym atk0=1
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS relax with .set at
+#stderr: relax.l
+#source: relax.s
+
+# Test relaxation with .set at (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45da jalr k0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> b462 fffe bne v0,v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45da jalr k0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> 4003 fffe bltz v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45da jalr k0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> b462 fffe bne v0,v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45fa jalrs k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4003 fffe bltz v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45fa jalrs k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45da jalr k0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> b462 fffe bne v0,v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45da jalr k0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> 4003 fffe bltz v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45da jalr k0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> b462 fffe bne v0,v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 459a jr k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45fa jalrs k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4003 fffe bltz v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45fa jalrs k0
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#as: -KPIC -32 -relax-branch
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS relax
+#stderr: relax.l
+#source: relax.s
+
+# Test relaxation (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45c1 jalr at
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> b462 fffe bne v0,v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45c1 jalr at
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> 4003 fffe bltz v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45c1 jalr at
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> b462 fffe bne v0,v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45e1 jalrs at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4003 fffe bltz v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45e1 jalrs at
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45c1 jalr at
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> b462 fffe bne v0,v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45c1 jalr at
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> 4003 fffe bltz v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45c1 jalr at
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+([0-9a-f]+) <[^>]*> b462 fffe bne v0,v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 4581 jr at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45e1 jalrs at
+[0-9a-f]+ <[^>]*> 0c00 nop
+([0-9a-f]+) <[^>]*> 4003 fffe bltz v1,\1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
+[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
+[0-9a-f]+ <[^>]*> 45e1 jalrs at
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS hardware rol/ror
+#source: rol.s
+#as: -32
+
+# Test the rol and ror macros (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 00a0 09d0 negu at,a1
+[0-9a-f]+ <[^>]*> 0081 20d0 rorv a0,a0,at
+[0-9a-f]+ <[^>]*> 00c0 21d0 negu a0,a2
+[0-9a-f]+ <[^>]*> 00a4 20d0 rorv a0,a1,a0
+[0-9a-f]+ <[^>]*> 0084 f8c0 ror a0,a0,0x1f
+[0-9a-f]+ <[^>]*> 0085 f8c0 ror a0,a1,0x1f
+[0-9a-f]+ <[^>]*> 0085 00c0 ror a0,a1,0x0
+[0-9a-f]+ <[^>]*> 0085 20d0 rorv a0,a0,a1
+[0-9a-f]+ <[^>]*> 00a6 20d0 rorv a0,a1,a2
+[0-9a-f]+ <[^>]*> 0084 08c0 ror a0,a0,0x1
+[0-9a-f]+ <[^>]*> 0085 08c0 ror a0,a1,0x1
+[0-9a-f]+ <[^>]*> 0085 00c0 ror a0,a1,0x0
+[0-9a-f]+ <[^>]*> 0085 00c0 ror a0,a1,0x0
+[0-9a-f]+ <[^>]*> 0085 f8c0 ror a0,a1,0x1f
+[0-9a-f]+ <[^>]*> 0085 08c0 ror a0,a1,0x1
+[0-9a-f]+ <[^>]*> 0085 00c0 ror a0,a1,0x0
+[0-9a-f]+ <[^>]*> 0085 08c0 ror a0,a1,0x1
+[0-9a-f]+ <[^>]*> 0085 f8c0 ror a0,a1,0x1f
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: uld2 -EB
+#source: uld2.s
+#as: -EB
+
+# Further checks of uld macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 6085 4000 ldl \$4,0\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 5007 ldr \$4,7\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 4001 ldl \$4,1\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 5008 ldr \$4,8\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 4000 ldl \$1,0\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 5007 ldr \$1,7\(\$5\)
+[0-9a-f]+ <[^>]*> 0ca1 move \$5,\$1
+[0-9a-f]+ <[^>]*> 6025 4001 ldl \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 5008 ldr \$1,8\(\$5\)
+[0-9a-f]+ <[^>]*> 0ca1 move \$5,\$1
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: uld2 -EL
+#source: uld2.s
+#as: -EL
+
+# Further checks of uld macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 6085 4007 ldl \$4,7\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 5000 ldr \$4,0\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 4008 ldl \$4,8\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 5001 ldr \$4,1\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 4007 ldl \$1,7\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 5000 ldr \$1,0\(\$5\)
+[0-9a-f]+ <[^>]*> 0ca1 move \$5,\$1
+[0-9a-f]+ <[^>]*> 6025 4008 ldl \$1,8\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 5001 ldr \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 0ca1 move \$5,\$1
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: ulh2 -EB
+#source: ulh2.s
+#as: -EB -32
+
+# Further checks of ulh/ulhu macros (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1c25 0000 lb \$1,0\(\$5\)
+[0-9a-f]+ <[^>]*> 1485 0001 lbu \$4,1\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0024 2290 or \$4,\$4,\$1
+[0-9a-f]+ <[^>]*> 1c25 0001 lb \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 1485 0002 lbu \$4,2\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0024 2290 or \$4,\$4,\$1
+[0-9a-f]+ <[^>]*> 1c25 0000 lb \$1,0\(\$5\)
+[0-9a-f]+ <[^>]*> 14a5 0001 lbu \$5,1\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0025 2a90 or \$5,\$5,\$1
+[0-9a-f]+ <[^>]*> 1c25 0001 lb \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 14a5 0002 lbu \$5,2\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0025 2a90 or \$5,\$5,\$1
+[0-9a-f]+ <[^>]*> 1425 0000 lbu \$1,0\(\$5\)
+[0-9a-f]+ <[^>]*> 1485 0001 lbu \$4,1\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0024 2290 or \$4,\$4,\$1
+[0-9a-f]+ <[^>]*> 1425 0001 lbu \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 1485 0002 lbu \$4,2\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0024 2290 or \$4,\$4,\$1
+[0-9a-f]+ <[^>]*> 1425 0000 lbu \$1,0\(\$5\)
+[0-9a-f]+ <[^>]*> 14a5 0001 lbu \$5,1\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0025 2a90 or \$5,\$5,\$1
+[0-9a-f]+ <[^>]*> 1425 0001 lbu \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 14a5 0002 lbu \$5,2\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0025 2a90 or \$5,\$5,\$1
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: ulh2 -EL
+#source: ulh2.s
+#as: -EL -32
+
+# Further checks of ulh/ulhu macros (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1c25 0001 lb \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 1485 0000 lbu \$4,0\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0024 2290 or \$4,\$4,\$1
+[0-9a-f]+ <[^>]*> 1c25 0002 lb \$1,2\(\$5\)
+[0-9a-f]+ <[^>]*> 1485 0001 lbu \$4,1\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0024 2290 or \$4,\$4,\$1
+[0-9a-f]+ <[^>]*> 1c25 0001 lb \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 14a5 0000 lbu \$5,0\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0025 2a90 or \$5,\$5,\$1
+[0-9a-f]+ <[^>]*> 1c25 0002 lb \$1,2\(\$5\)
+[0-9a-f]+ <[^>]*> 14a5 0001 lbu \$5,1\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0025 2a90 or \$5,\$5,\$1
+[0-9a-f]+ <[^>]*> 1425 0001 lbu \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 1485 0000 lbu \$4,0\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0024 2290 or \$4,\$4,\$1
+[0-9a-f]+ <[^>]*> 1425 0002 lbu \$1,2\(\$5\)
+[0-9a-f]+ <[^>]*> 1485 0001 lbu \$4,1\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0024 2290 or \$4,\$4,\$1
+[0-9a-f]+ <[^>]*> 1425 0001 lbu \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 14a5 0000 lbu \$5,0\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0025 2a90 or \$5,\$5,\$1
+[0-9a-f]+ <[^>]*> 1425 0002 lbu \$1,2\(\$5\)
+[0-9a-f]+ <[^>]*> 14a5 0001 lbu \$5,1\(\$5\)
+[0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
+[0-9a-f]+ <[^>]*> 0025 2a90 or \$5,\$5,\$1
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: ulw2 -EB interlocked
+#source: ulw2.s
+#as: -EB -32
+
+# Further checks of ulw macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 6085 0000 lwl \$4,0\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 1003 lwr \$4,3\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 0001 lwl \$4,1\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 1004 lwr \$4,4\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 0000 lwl \$1,0\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 1003 lwr \$1,3\(\$5\)
+[0-9a-f]+ <[^>]*> 0ca1 move \$5,\$1
+[0-9a-f]+ <[^>]*> 6025 0001 lwl \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 1004 lwr \$1,4\(\$5\)
+[0-9a-f]+ <[^>]*> 0ca1 move \$5,\$1
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: ulw2 -EL interlocked
+#source: ulw2.s
+#as: -EL -32
+
+# Further checks of ulw macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 6085 0003 lwl \$4,3\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 1000 lwr \$4,0\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 0004 lwl \$4,4\(\$5\)
+[0-9a-f]+ <[^>]*> 6085 1001 lwr \$4,1\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 0003 lwl \$1,3\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 1000 lwr \$1,0\(\$5\)
+[0-9a-f]+ <[^>]*> 0ca1 move \$5,\$1
+[0-9a-f]+ <[^>]*> 6025 0004 lwl \$1,4\(\$5\)
+[0-9a-f]+ <[^>]*> 6025 1001 lwr \$1,1\(\$5\)
+[0-9a-f]+ <[^>]*> 0ca1 move \$5,\$1
+ \.\.\.
{ mipsisa64r2-*-* mipsisa64r2el-*-* }
mips_arch_create mips16 32 {} {} \
{ -march=mips1 -mips16 } { -mmips:16 }
+mips_arch_create micromips 64 mips64r2 {} \
+ { -march=mips64 -mmicromips } {}
mips_arch_create r3000 32 mips1 {} \
{ -march=r3000 -mtune=r3000 } { -mmips:3000 }
mips_arch_create r3900 32 mips1 { gpr_ilocks } \
set addr32 [expr [istarget mipstx39*-*-*] || [istarget mips-*-linux*] || [istarget mipsel-*-linux*] || [istarget mips*-*-ecoff]]
set has_newabi [expr [istarget *-*-irix6*] || [istarget mips64*-*-linux*]]
set no_mips16 [expr !$elf]
+ set no_micromips [expr !$elf]
if { [istarget "mips*-*-*linux*"] || [istarget "mips*-sde-elf*"] } then {
set tmips "t"
if { $no_mips16 } {
mips_arch_destroy mips16
}
+ if { $no_micromips } {
+ mips_arch_destroy micromips
+ }
run_dump_test_arches "abs" [mips_arch_list_matching mips1]
run_dump_test_arches "add" [mips_arch_list_matching mips1]
} else {
run_dump_test "jal"
}
+ run_dump_test_arches "jal-mask-11" [mips_arch_list_matching mips1]
+ run_dump_test_arches "jal-mask-12" [mips_arch_list_matching mips1]
+ run_dump_test_arches "jal-mask-21" [mips_arch_list_matching micromips]
+ run_dump_test_arches "jal-mask-22" [mips_arch_list_matching micromips]
run_dump_test "eret-1"
run_dump_test "eret-2"
run_dump_test "eret-3"
- run_dump_test_arches "24k-branch-delay-1" [mips_arch_list_matching mips1]
+ run_dump_test_arches "24k-branch-delay-1" \
+ [mips_arch_list_matching mips1 !micromips]
run_dump_test_arches "24k-triple-stores-1" \
- [mips_arch_list_matching mips32r2 !octeon]
- run_dump_test_arches "24k-triple-stores-2" [mips_arch_list_matching mips2]
- run_dump_test_arches "24k-triple-stores-3" [mips_arch_list_matching mips3]
- run_dump_test_arches "24k-triple-stores-4" [mips_arch_list_matching mips2]
- run_dump_test_arches "24k-triple-stores-5" [mips_arch_list_matching mips1]
- run_dump_test_arches "24k-triple-stores-6" [mips_arch_list_matching mips2]
- run_dump_test_arches "24k-triple-stores-7" [mips_arch_list_matching mips2]
- run_dump_test_arches "24k-triple-stores-8" [mips_arch_list_matching mips1]
- run_dump_test_arches "24k-triple-stores-9" [mips_arch_list_matching mips1]
- run_dump_test_arches "24k-triple-stores-10" [mips_arch_list_matching mips1]
+ [mips_arch_list_matching mips32r2 !octeon !micromips]
+ run_dump_test_arches "24k-triple-stores-2" \
+ [mips_arch_list_matching mips2 !micromips]
+ run_dump_test_arches "24k-triple-stores-3" \
+ [mips_arch_list_matching mips3 !micromips]
+ run_dump_test_arches "24k-triple-stores-4" \
+ [mips_arch_list_matching mips2 !micromips]
+ run_dump_test_arches "24k-triple-stores-5" \
+ [mips_arch_list_matching mips1 !micromips]
+ run_dump_test_arches "24k-triple-stores-6" \
+ [mips_arch_list_matching mips2 !micromips]
+ run_dump_test_arches "24k-triple-stores-7" \
+ [mips_arch_list_matching mips2 !micromips]
+ run_dump_test_arches "24k-triple-stores-8" \
+ [mips_arch_list_matching mips1 !micromips]
+ run_dump_test_arches "24k-triple-stores-9" \
+ [mips_arch_list_matching mips1 !micromips]
+ run_dump_test_arches "24k-triple-stores-10" \
+ [mips_arch_list_matching mips1 !micromips]
if $elf {
run_dump_test_arches "24k-triple-stores-11" \
- [mips_arch_list_matching mips1]
+ [mips_arch_list_matching mips1 !micromips]
}
if $elf {
run_dump_test "mips16"
run_dump_test "mips16-64"
# Check MIPS16e extensions
- run_dump_test_arches "mips16e" [mips_arch_list_matching mips32]
+ run_dump_test_arches "mips16e" \
+ [mips_arch_list_matching mips32 !micromips]
# Check jalx handling
run_dump_test "mips16-jalx"
run_dump_test "mips-jalx"
run_dump_test "sync"
run_dump_test_arches "mips32" [mips_arch_list_matching mips32]
+ run_dump_test_arches "mips32-imm" [mips_arch_list_matching mips32]
run_dump_test_arches "mips32-sf32" [mips_arch_list_matching mips32]
run_list_test_arches "mips32-sf32" "-32 -msoft-float" \
run_dump_test "relax-swap1-mips2"
run_dump_test "relax-swap2"
run_list_test_arches "relax-bposge" "-mdsp -relax-branch" \
- [mips_arch_list_matching mips64r2]
+ [mips_arch_list_matching mips64r2 \
+ !micromips]
run_list_test "illegal" "-32"
run_list_test "baddata1" "-32"
run_dump_test "elf_ase_mips16"
run_dump_test "elf_ase_mips16-2"
}
+ if { !$no_micromips } {
+ run_dump_test "elf_ase_micromips"
+ run_dump_test "elf_ase_micromips-2"
+ }
run_dump_test "mips-gp32-fp32-pic"
run_dump_test "mips-gp32-fp64-pic"
run_dump_test_arches "alnv_ps-swap" [lsort -dictionary -unique [concat \
[mips_arch_list_matching mips5] \
[mips_arch_list_matching mips32r2] ] ]
+ run_dump_test_arches "cache" [lsort -dictionary -unique [concat \
+ [mips_arch_list_matching mips3] \
+ [mips_arch_list_matching mips32] ] ]
+ run_dump_test_arches "daddi" [mips_arch_list_matching mips3]
+ run_dump_test_arches "pref" [lsort -dictionary -unique [concat \
+ [mips_arch_list_matching mips4] \
+ [mips_arch_list_matching mips32] ] ]
if $has_newabi { run_dump_test "cfi-n64-1" }
run_dump_test "pr12915"
run_dump_test "reginfo-1a"
run_dump_test "reginfo-1b"
+
+ if { !$no_micromips } {
+ run_dump_test "micromips"
+ run_dump_test "micromips-trap"
+ run_list_test "micromips-size-0" \
+ "-32 -march=mips64 -mmicromips" "microMIPS instruction size 0"
+ run_dump_test "micromips-size-1"
+ run_dump_test "micromips-branch-relax"
+ run_dump_test "micromips-branch-relax-pic"
+ run_dump_test "micromips-branch-delay"
+ }
}
-#objdump: -rst -mips16
+#objdump: -rst --special-syms -mips16
#name: MIPS16 reloc
#as: -32 -mips16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS32 WAIT and SDBBP instructions
+#as: -32
+
+# Check MIPS32 WAIT and SDBBP instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+[0-9a-f]+ <[^>]*> 4359e260 wait 0x56789
+[0-9a-f]+ <[^>]*> 7159e27f sdbbp 0x56789
+ \.\.\.
--- /dev/null
+# Source file to test wide immediates with MIPS32 WAIT and SDBBP instructions
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+
+ # 20 bits accepted for MIPS32
+ wait 0x56789
+ sdbbp 0x56789
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
0+0014 <[^>]*> 716c0005 msubu t3,t4
0+0018 <[^>]*> 71cf6802 mul t5,t6,t7
0+001c <[^>]*> ce040000 pref 0x4,0\(s0\)
-0+0020 <[^>]*> ce247fff pref 0x4,32767\(s1\)
-0+0024 <[^>]*> ce448000 pref 0x4,-32768\(s2\)
+0+0020 <[^>]*> ce2407ff pref 0x4,2047\(s1\)
+0+0024 <[^>]*> ce44f800 pref 0x4,-2048\(s2\)
0+0028 <[^>]*> 00000040 ssnop
0+002c <[^>]*> bc250000 cache 0x5,0\(at\)
-0+0030 <[^>]*> bc457fff cache 0x5,32767\(v0\)
-0+0034 <[^>]*> bc658000 cache 0x5,-32768\(v1\)
+0+0030 <[^>]*> bc4507ff cache 0x5,2047\(v0\)
+0+0034 <[^>]*> bc65f800 cache 0x5,-2048\(v1\)
0+0038 <[^>]*> 3c010001 lui at,0x1
0+003c <[^>]*> 00240821 addu at,at,a0
0+0040 <[^>]*> bc258000 cache 0x5,-32768\(at\)
0+0070 <[^>]*> 42000006 tlbwr
0+0074 <[^>]*> 42000020 wait
0+0078 <[^>]*> 42000020 wait
-0+007c <[^>]*> 4359e260 wait 0x56789
+0+007c <[^>]*> 4200d160 wait 0x345
0+0080 <[^>]*> 0000000d break
0+0084 <[^>]*> 0000000d break
0+0088 <[^>]*> 0345000d break 0x345
0+008c <[^>]*> 0048d14d break 0x48,0x345
0+0090 <[^>]*> 7000003f sdbbp
0+0094 <[^>]*> 7000003f sdbbp
-0+0098 <[^>]*> 7159e27f sdbbp 0x56789
+0+0098 <[^>]*> 7000d17f sdbbp 0x345
\.\.\.
msubu $11, $12
mul $13, $14, $15
pref 4, ($16)
- pref 4, 32767($17)
- pref 4, -32768($18)
+ pref 4, 2047($17)
+ pref 4, -2048($18)
ssnop
# privileged instructions
cache 5, ($1)
- cache 5, 32767($2)
- cache 5, -32768($3)
+ cache 5, 2047($2)
+ cache 5, -2048($3)
.set at
cache 5, 32768($4)
cache 5, -32769($5)
tlbwr
wait
wait 0 # disassembles without code
- wait 0x56789
+ wait 0x345
# For a while break for the mips32 ISA interpreted a single argument
# as a 20-bit code, placing it in the opcode differently to
# different.
sdbbp
sdbbp 0 # disassembles without code
- sdbbp 0x56789
+ sdbbp 0x345
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
sdxc1 $f4,$4($5)
swxc1 $f4,$4($5)
-# Round to a 16 byte boundary, for ease in testing multiple targets.
- nop
- nop
- nop
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
# It used to be disabled due to a clash with lwc3.
pref 4,0($4)
-# Round to a 16 byte boundary, for ease in testing multiple targets.
- nop
- nop
- nop
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
-#objdump: -rst -mips16
+#objdump: -rst --special-syms -mips16
#name: MIPS16 reloc
#as: -32 -mips16
#source: mips16-e.s
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS PREF instruction
+#as: -32 --defsym tpref=1
+#source: cache.s
+
+# Check MIPS PREF instruction assembly.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> cc4507ff pref 0x5,2047\(v0\)
+[0-9a-f]+ <[^>]*> cc65f800 pref 0x5,-2048\(v1\)
+[0-9a-f]+ <[^>]*> cc850800 pref 0x5,2048\(a0\)
+[0-9a-f]+ <[^>]*> cca5f7ff pref 0x5,-2049\(a1\)
+[0-9a-f]+ <[^>]*> ccc57fff pref 0x5,32767\(a2\)
+[0-9a-f]+ <[^>]*> cce58000 pref 0x5,-32768\(a3\)
+[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1
+[0-9a-f]+ <[^>]*> 00280821 addu at,at,t0
+[0-9a-f]+ <[^>]*> cc258000 pref 0x5,-32768\(at\)
+[0-9a-f]+ <[^>]*> 3c01ffff lui at,0xffff
+[0-9a-f]+ <[^>]*> 00290821 addu at,at,t1
+[0-9a-f]+ <[^>]*> cc257fff pref 0x5,32767\(at\)
+[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1
+[0-9a-f]+ <[^>]*> 002a0821 addu at,at,t2
+[0-9a-f]+ <[^>]*> cc259000 pref 0x5,-28672\(at\)
+[0-9a-f]+ <[^>]*> 3c01ffff lui at,0xffff
+[0-9a-f]+ <[^>]*> 002b0821 addu at,at,t3
+[0-9a-f]+ <[^>]*> cc256fff pref 0x5,28671\(at\)
+ \.\.\.
20494: R_MIPS_LO16 \.text
00020498 <bar\+0x248> jalr k0
0002049c <bar\+0x24c> nop
+ \.\.\.
20494: R_MIPS_LO16 \.text
00020498 <bar\+0x248> jalr at
0002049c <bar\+0x24c> nop
+ \.\.\.
bltzall $2, foo
bgezall $3, foo
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
\.\.\.
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
\.\.\.
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|-16384)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,(1|4097)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,1\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,1\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,(1|8193)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,(1|-16383)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(23131|14939)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|-16384)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,(1|4097)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,(1|8193)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sdc1 \$f4,(1|-16383)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(23131|14939)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sdc1 \$f4,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
\.\.\.
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,-23131\(at\)
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[0-9a-f]+ <[^>]*> addu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
\.\.\.
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,-23131\(at\)
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> sd a0,0\(gp\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_data_label\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_data_label\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 small_external_common\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 small_external_common\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> daddu at,a1,gp
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_GPREL16 \.sbss\+0x1
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_GPREL16 \.sbss\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0xffffffffffff8000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0xffffffffffff8000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x10000
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x10000
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.data\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.data\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_data_label\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_data_label\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 big_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 big_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 small_external_common\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 small_external_common\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.bss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.bss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: R_MIPS_HIGHEST \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHEST \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HIGHER \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HIGHER \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddiu at,at,0
-[ ]*[0-9a-f]+: R_MIPS_HI16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_HI16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[0-9a-f]+ <[^>]*> dsll at,at,0x10
[0-9a-f]+ <[^>]*> daddu at,at,a1
[0-9a-f]+ <[^>]*> sd a0,0\(at\)
-[ ]*[0-9a-f]+: R_MIPS_LO16 \.sbss\+0x1a5a5
+[ ]*[0-9a-f]+: R_(MICRO)?MIPS_LO16 \.sbss\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1a5a5
\.\.\.
[0-9a-f]+ <[^>]*> sw a0,-23131\(at\)
[0-9a-f]+ <[^>]*> sw a1,-23127\(at\)
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a0,0\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,4\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a0,0\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> sw a1,4\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a0,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,(4|8196)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a0,(0|-16384)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> sw a1,(4|-16380)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a0,(1|4097)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,(5|4101)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a0,1\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,5\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a0,1\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> sw a1,5\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a0,(1|8193)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,(5|8197)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a0,(1|-16383)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> sw a1,(5|-16379)\(gp\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a0,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|24572)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a0,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|24572)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a0,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,(4|8196)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a0,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(23127|19031)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> sw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> sw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> sw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> sw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> sw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a0,-(23131|14939)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,-(23127|14935)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a0,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(23127|19031)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,(4|8196)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sw a0,(0|-16384)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> sw a1,(4|-16380)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,(1|4097)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,(5|4101)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sw a0,1\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> sw a1,5\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,(1|8193)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,(5|8197)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,gp
[0-9a-f]+ <[^>]*> sw a0,(1|-16383)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> sw a1,(5|-16379)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_GPREL16|GPREL) \.sbss(\+0x4000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|24572)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-32768\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> sw a1,-32764\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-(32768|24576)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|24572)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x0
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-(32768|28672)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(32764|28668)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,0\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> sw a1,4\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,(0|8192)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,(4|8196)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x1
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,(0|4096)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,(4|4100)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(23127|19031)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.data(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.data(\+0xfffff000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_data_label
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> sw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_data_label
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_data_label
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) big_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> sw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) big_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) big_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) small_external_common
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-23131\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> sw a1,-23127\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) small_external_common
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) small_external_common
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-(23131|14939)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> sw a1,-(23127|14935)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.bss(\+0xffffe000)?
[0-9a-f]+ <[^>]*> lui at,0x2
-[ ]*[0-9a-f]+: (R_MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_HI16|REFHI) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> addu at,a1,at
[0-9a-f]+ <[^>]*> sw a0,-(23131|19035)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
[0-9a-f]+ <[^>]*> sw a1,-(23127|19031)\(at\)
-[ ]*[0-9a-f]+: (R_MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
+[ ]*[0-9a-f]+: (R_(MICRO)?MIPS_LO16|REFLO) \.sbss(\+0xfffff000)?
\.\.\.
-#objdump: -rst -mips16
+#objdump: -rst --special-syms -mips16
#name: MIPS16 reloc
#as: -32 -mips16
#source: mips16-e.s
-#objdump: -rst -mips16
+#objdump: -rst --special-syms -mips16
#name: MIPS16 reloc
#as: -32 -mips16
#source: mips16-e.s
+2011-07-24 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (R_MICROMIPS_min): New relocations.
+ (R_MICROMIPS_26_S1): Likewise.
+ (R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
+ (R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
+ (R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
+ (R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
+ (R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
+ (R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
+ (R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
+ (R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
+ (R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
+ (R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
+ (R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
+ (R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
+ (R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
+ (R_MICROMIPS_TLS_GOTTPREL): Likewise.
+ (R_MICROMIPS_TLS_TPREL_HI16): Likewise.
+ (R_MICROMIPS_TLS_TPREL_LO16): Likewise.
+ (R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
+ (R_MICROMIPS_max): Likewise.
+ (EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
+ (STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
+ (ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
+ (STO_MICROMIPS): Likewise.
+ (ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
+ (ELF_ST_IS_COMPRESSED): Likewise.
+ (STO_MIPS_PLT, STO_MIPS_PIC): Rework.
+ (ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
+ (STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
+
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* common.h (EM_K1OM): New.
/* These relocations are specific to VxWorks. */
RELOC_NUMBER (R_MIPS_COPY, 126)
RELOC_NUMBER (R_MIPS_JUMP_SLOT, 127)
+
+ /* These relocations are specific to microMIPS. */
+ FAKE_RELOC (R_MICROMIPS_min, 130)
+ RELOC_NUMBER (R_MICROMIPS_26_S1, 133)
+ RELOC_NUMBER (R_MICROMIPS_HI16, 134)
+ RELOC_NUMBER (R_MICROMIPS_LO16, 135)
+ RELOC_NUMBER (R_MICROMIPS_GPREL16, 136) /* In Elf 64:
+ alias R_MICROMIPS_GPREL */
+ RELOC_NUMBER (R_MICROMIPS_LITERAL, 137)
+ RELOC_NUMBER (R_MICROMIPS_GOT16, 138) /* In Elf 64:
+ alias R_MICROMIPS_GOT */
+ RELOC_NUMBER (R_MICROMIPS_PC7_S1, 139)
+ RELOC_NUMBER (R_MICROMIPS_PC10_S1, 140)
+ RELOC_NUMBER (R_MICROMIPS_PC16_S1, 141)
+ RELOC_NUMBER (R_MICROMIPS_CALL16, 142) /* In Elf 64:
+ alias R_MICROMIPS_CALL */
+ RELOC_NUMBER (R_MICROMIPS_GOT_DISP, 145)
+ RELOC_NUMBER (R_MICROMIPS_GOT_PAGE, 146)
+ RELOC_NUMBER (R_MICROMIPS_GOT_OFST, 147)
+ RELOC_NUMBER (R_MICROMIPS_GOT_HI16, 148)
+ RELOC_NUMBER (R_MICROMIPS_GOT_LO16, 149)
+ RELOC_NUMBER (R_MICROMIPS_SUB, 150)
+ RELOC_NUMBER (R_MICROMIPS_HIGHER, 151)
+ RELOC_NUMBER (R_MICROMIPS_HIGHEST, 152)
+ RELOC_NUMBER (R_MICROMIPS_CALL_HI16, 153)
+ RELOC_NUMBER (R_MICROMIPS_CALL_LO16, 154)
+ RELOC_NUMBER (R_MICROMIPS_SCN_DISP, 155)
+ RELOC_NUMBER (R_MICROMIPS_JALR, 156)
+ RELOC_NUMBER (R_MICROMIPS_HI0_LO16, 157)
+ /* TLS relocations. */
+ RELOC_NUMBER (R_MICROMIPS_TLS_GD, 162)
+ RELOC_NUMBER (R_MICROMIPS_TLS_LDM, 163)
+ RELOC_NUMBER (R_MICROMIPS_TLS_DTPREL_HI16, 164)
+ RELOC_NUMBER (R_MICROMIPS_TLS_DTPREL_LO16, 165)
+ RELOC_NUMBER (R_MICROMIPS_TLS_GOTTPREL, 166)
+ RELOC_NUMBER (R_MICROMIPS_TLS_TPREL_HI16, 169)
+ RELOC_NUMBER (R_MICROMIPS_TLS_TPREL_LO16, 170)
+ /* microMIPS GP- and PC-relative relocations. */
+ RELOC_NUMBER (R_MICROMIPS_GPREL7_S2, 172)
+ RELOC_NUMBER (R_MICROMIPS_PC23_S2, 173)
+ FAKE_RELOC (R_MICROMIPS_max, 174)
+
/* This was a GNU extension used by embedded-PIC. It was co-opted by
mips-linux for exception-handling data. It is no longer used, but
should continue to be supported by the linker for backward
/* Use MIPS-16 ISA extensions */
#define EF_MIPS_ARCH_ASE_M16 0x04000000
+/* Use MICROMIPS ISA extensions. */
+#define EF_MIPS_ARCH_ASE_MICROMIPS 0x02000000
+
/* Indicates code compiled for a 64-bit machine in 32-bit mode.
(regs are 32-bits wide.) */
#define EF_MIPS_32BITMODE 0x00000100
#define STO_HIDDEN STV_HIDDEN
#define STO_PROTECTED STV_PROTECTED
+/* Two topmost bits denote the MIPS ISA for .text symbols:
+ + 00 -- standard MIPS code,
+ + 10 -- microMIPS code,
+ + 11 -- MIPS16 code; requires the following two bits to be set too.
+ Note that one of the MIPS16 bits overlaps with STO_MIPS_PIC. See below
+ for details. */
+#define STO_MIPS_ISA (3 << 6)
+
+/* The mask spanning the rest of MIPS psABI flags. At most one is expected
+ to be set except for STO_MIPS16. */
+#define STO_MIPS_FLAGS (~(STO_MIPS_ISA | ELF_ST_VISIBILITY (-1)))
+
/* The MIPS psABI was updated in 2008 with support for PLTs and copy
relocs. There are therefore two types of nonzero SHN_UNDEF functions:
PLT entries and traditional MIPS lazy binding stubs. We mark the former
with STO_MIPS_PLT to distinguish them from the latter. */
#define STO_MIPS_PLT 0x8
+#define ELF_ST_IS_MIPS_PLT(other) (((other) & STO_MIPS_FLAGS) == STO_MIPS_PLT)
+#define ELF_ST_SET_MIPS_PLT(other) (((other) & ~STO_MIPS_FLAGS) | STO_MIPS_PLT)
/* This value is used to mark PIC functions in an object that mixes
- PIC and non-PIC. */
+ PIC and non-PIC. Note that this bit overlaps with STO_MIPS16,
+ although MIPS16 symbols are never considered to be MIPS_PIC. */
#define STO_MIPS_PIC 0x20
-#define ELF_ST_IS_MIPS_PIC(OTHER) \
- (((OTHER) & ~ELF_ST_VISIBILITY (-1)) == STO_MIPS_PIC)
-#define ELF_ST_SET_MIPS_PIC(OTHER) \
- (STO_MIPS_PIC | ELF_ST_VISIBILITY (OTHER))
+#define ELF_ST_IS_MIPS_PIC(other) (((other) & STO_MIPS_FLAGS) == STO_MIPS_PIC)
+#define ELF_ST_SET_MIPS_PIC(other) (((other) & ~STO_MIPS_FLAGS) | STO_MIPS_PIC)
/* This value is used for a mips16 .text symbol. */
#define STO_MIPS16 0xf0
-#define ELF_ST_IS_MIPS16(OTHER) (((OTHER) & 0xf0) == STO_MIPS16)
-#define ELF_ST_SET_MIPS16(OTHER) (((OTHER) & ~0xf0) | STO_MIPS16)
+#define ELF_ST_IS_MIPS16(other) (((other) & STO_MIPS16) == STO_MIPS16)
+#define ELF_ST_SET_MIPS16(other) ((other) | STO_MIPS16)
+
+/* This value is used for a microMIPS .text symbol. To distinguish from
+ STO_MIPS16, we set top two bits to be 10 to denote STO_MICROMIPS. The
+ mask is STO_MIPS_ISA. */
+#define STO_MICROMIPS (2 << 6)
+#define ELF_ST_IS_MICROMIPS(other) (((other) & STO_MIPS_ISA) == STO_MICROMIPS)
+#define ELF_ST_SET_MICROMIPS(other) (((other) & ~STO_MIPS_ISA) | STO_MICROMIPS)
+
+/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
+ has been indicated for a .text symbol. */
+#define ELF_ST_IS_COMPRESSED(other) \
+ (ELF_ST_IS_MIPS16 (other) || ELF_ST_IS_MICROMIPS (other))
/* This bit is used on Irix to indicate a symbol whose definition
is optional - if, at final link time, it cannot be found, no
+2011-07-24 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
+ (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
+ (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
+ (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
+ (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
+ (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
+ (OP_MASK_RS3, OP_SH_RS3): Likewise.
+ (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
+ (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
+ (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
+ (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
+ (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
+ (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
+ (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
+ (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
+ (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
+ (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
+ (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
+ (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
+ (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
+ (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
+ (INSN_WRITE_GPR_S): New macro.
+ (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
+ (INSN2_READ_FPR_D): Likewise.
+ (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
+ (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
+ (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
+ (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
+ (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
+ (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
+ (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
+ (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
+ (CPU_MICROMIPS): New macro.
+ (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
+ (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
+ (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
+ (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
+ (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
+ (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
+ (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
+ (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
+ (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
+ (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
+ (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
+ (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
+ (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
+ (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
+ (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
+ (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
+ (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
+ (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
+ (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
+ (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
+ (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
+ (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
+ (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
+ (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
+ (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
+ (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
+ (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
+ (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
+ (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
+ (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
+ (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
+ (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
+ (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
+ (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
+ (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
+ (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
+ (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
+ (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
+ (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
+ (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
+ (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
+ (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
+ (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
+ (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
+ (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
+ (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
+ (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
+ (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
+ (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
+ (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
+ (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
+ (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
+ (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
+ (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
+ (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
+ (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
+ (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
+ (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
+ (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
+ (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
+ (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
+ (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
+ (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
+ (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
+ (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
+ (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
+ (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
+ (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
+ (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
+ (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
+ (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
+ (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
+ (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
+ (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
+ (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
+ (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
+ (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
+ (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
+ (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
+ (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
+ (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
+ (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
+ (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
+ (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
+ (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
+ (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
+ (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
+ (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
+ (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
+ (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
+ (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
+ (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
+ (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
+ (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
+ (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
+ (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
+ (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
+ (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
+ (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
+ (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
+ (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
+ (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
+ (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
+ (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
+ (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
+ (micromips_opcodes): New declaration.
+ (bfd_micromips_num_opcodes): Likewise.
+
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (INSN_TRAP): Rename to...
#define OP_SH_CODE20 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_SHAMT 6
+#define OP_MASK_EXTLSB OP_MASK_SHAMT
+#define OP_SH_EXTLSB OP_SH_SHAMT
+#define OP_MASK_STYPE OP_MASK_SHAMT
+#define OP_SH_STYPE OP_SH_SHAMT
#define OP_MASK_FD 0x1f
#define OP_SH_FD 6
#define OP_MASK_TARGET 0x3ffffff
#define OP_SH_FZ 0
#define OP_MASK_FZ 0x1f
+/* Every MICROMIPSOP_X definition requires a corresponding OP_X
+ definition, and vice versa. This simplifies various parts
+ of the operand handling in GAS. The fields below only exist
+ in the microMIPS encoding, so define each one to have an empty
+ range. */
+#define OP_MASK_CODE10 0
+#define OP_SH_CODE10 0
+#define OP_MASK_TRAP 0
+#define OP_SH_TRAP 0
+#define OP_MASK_OFFSET12 0
+#define OP_SH_OFFSET12 0
+#define OP_MASK_OFFSET10 0
+#define OP_SH_OFFSET10 0
+#define OP_MASK_RS3 0
+#define OP_SH_RS3 0
+#define OP_MASK_MB 0
+#define OP_SH_MB 0
+#define OP_MASK_MC 0
+#define OP_SH_MC 0
+#define OP_MASK_MD 0
+#define OP_SH_MD 0
+#define OP_MASK_ME 0
+#define OP_SH_ME 0
+#define OP_MASK_MF 0
+#define OP_SH_MF 0
+#define OP_MASK_MG 0
+#define OP_SH_MG 0
+#define OP_MASK_MH 0
+#define OP_SH_MH 0
+#define OP_MASK_MI 0
+#define OP_SH_MI 0
+#define OP_MASK_MJ 0
+#define OP_SH_MJ 0
+#define OP_MASK_ML 0
+#define OP_SH_ML 0
+#define OP_MASK_MM 0
+#define OP_SH_MM 0
+#define OP_MASK_MN 0
+#define OP_SH_MN 0
+#define OP_MASK_MP 0
+#define OP_SH_MP 0
+#define OP_MASK_MQ 0
+#define OP_SH_MQ 0
+#define OP_MASK_IMMA 0
+#define OP_SH_IMMA 0
+#define OP_MASK_IMMB 0
+#define OP_SH_IMMB 0
+#define OP_MASK_IMMC 0
+#define OP_SH_IMMC 0
+#define OP_MASK_IMMF 0
+#define OP_SH_IMMF 0
+#define OP_MASK_IMMG 0
+#define OP_SH_IMMG 0
+#define OP_MASK_IMMH 0
+#define OP_SH_IMMH 0
+#define OP_MASK_IMMI 0
+#define OP_SH_IMMI 0
+#define OP_MASK_IMMJ 0
+#define OP_SH_IMMJ 0
+#define OP_MASK_IMML 0
+#define OP_SH_IMML 0
+#define OP_MASK_IMMM 0
+#define OP_SH_IMMM 0
+#define OP_MASK_IMMN 0
+#define OP_SH_IMMN 0
+#define OP_MASK_IMMO 0
+#define OP_SH_IMMO 0
+#define OP_MASK_IMMP 0
+#define OP_SH_IMMP 0
+#define OP_MASK_IMMQ 0
+#define OP_SH_IMMQ 0
+#define OP_MASK_IMMU 0
+#define OP_SH_IMMU 0
+#define OP_MASK_IMMW 0
+#define OP_SH_IMMW 0
+#define OP_MASK_IMMX 0
+#define OP_SH_IMMX 0
+#define OP_MASK_IMMY 0
+#define OP_SH_IMMY 0
+
/* This structure holds information for a particular instruction. */
struct mips_opcode
"z" must be zero register
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
"+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
- LSB (OP_*_SHAMT).
+ LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
+ microMIPS compatibility).
Enforces: 0 <= pos < 32.
"+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
#define INSN2_READ_GPR_D 0x00000200
+/* Instruction has a branch delay slot that requires a 16-bit instruction. */
+#define INSN2_BRANCH_DELAY_16BIT 0x00000400
+/* Instruction has a branch delay slot that requires a 32-bit instruction. */
+#define INSN2_BRANCH_DELAY_32BIT 0x00000800
+/* Modifies the general purpose register in MICROMIPSOP_*_RS. */
+#define INSN2_WRITE_GPR_S 0x00001000
+/* Reads the floating point register in MICROMIPSOP_*_FD. */
+#define INSN2_READ_FPR_D 0x00002000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MB. */
+#define INSN2_MOD_GPR_MB 0x00004000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MC. */
+#define INSN2_MOD_GPR_MC 0x00008000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MD. */
+#define INSN2_MOD_GPR_MD 0x00010000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_ME. */
+#define INSN2_MOD_GPR_ME 0x00020000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MF. */
+#define INSN2_MOD_GPR_MF 0x00040000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MG. */
+#define INSN2_MOD_GPR_MG 0x00080000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MJ. */
+#define INSN2_MOD_GPR_MJ 0x00100000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MP. */
+#define INSN2_MOD_GPR_MP 0x00200000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MQ. */
+#define INSN2_MOD_GPR_MQ 0x00400000
+/* Reads/Writes the stack pointer ($29). */
+#define INSN2_MOD_SP 0x00800000
+/* Reads the RA ($31) register. */
+#define INSN2_READ_GPR_31 0x01000000
+/* Reads the global pointer ($28). */
+#define INSN2_READ_GP 0x02000000
+/* Reads the program counter ($pc). */
+#define INSN2_READ_PC 0x04000000
+/* Is an unconditional branch insn. */
+#define INSN2_UNCOND_BRANCH 0x08000000
+/* Is a conditional branch insn. */
+#define INSN2_COND_BRANCH 0x10000000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MH/I. */
+#define INSN2_MOD_GPR_MHI 0x20000000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MM. */
+#define INSN2_MOD_GPR_MM 0x40000000
+/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MN. */
+#define INSN2_MOD_GPR_MN 0x80000000
+
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
specifies the base ISA level(s). The remainder of a 32-bit
M_ADDU_I,
M_AND_I,
M_BALIGN,
+ M_BC1FL,
+ M_BC1TL,
+ M_BC2FL,
+ M_BC2TL,
M_BEQ,
M_BEQ_I,
+ M_BEQL,
M_BEQL_I,
M_BGE,
M_BGEL,
M_BGEUL,
M_BGEU_I,
M_BGEUL_I,
+ M_BGEZ,
+ M_BGEZL,
+ M_BGEZALL,
M_BGT,
M_BGTL,
M_BGT_I,
M_BGTUL,
M_BGTU_I,
M_BGTUL_I,
+ M_BGTZ,
+ M_BGTZL,
M_BLE,
M_BLEL,
M_BLE_I,
M_BLEUL,
M_BLEU_I,
M_BLEUL_I,
+ M_BLEZ,
+ M_BLEZL,
M_BLT,
M_BLTL,
M_BLT_I,
M_BLTUL,
M_BLTU_I,
M_BLTUL_I,
+ M_BLTZ,
+ M_BLTZL,
+ M_BLTZALL,
M_BNE,
+ M_BNEL,
M_BNE_I,
M_BNEL_I,
M_CACHE_AB,
+ M_CACHE_OB,
M_DABS,
M_DADD_I,
M_DADDU_I,
M_JAL_1,
M_JAL_2,
M_JAL_A,
+ M_JALS_1,
+ M_JALS_2,
+ M_JALS_A,
M_L_DOB,
M_L_DAB,
M_LA_AB,
M_LD_AB,
M_LDC1_AB,
M_LDC2_AB,
+ M_LDC2_OB,
M_LDC3_AB,
M_LDL_AB,
+ M_LDL_OB,
+ M_LDM_AB,
+ M_LDM_OB,
+ M_LDP_AB,
+ M_LDP_OB,
M_LDR_AB,
+ M_LDR_OB,
M_LH_A,
M_LH_AB,
M_LHU_A,
M_LI_S,
M_LI_SS,
M_LL_AB,
+ M_LL_OB,
M_LLD_AB,
+ M_LLD_OB,
M_LS_A,
M_LW_A,
M_LW_AB,
M_LWC1_AB,
M_LWC2_A,
M_LWC2_AB,
+ M_LWC2_OB,
M_LWC3_A,
M_LWC3_AB,
M_LWL_A,
M_LWL_AB,
+ M_LWL_OB,
+ M_LWM_AB,
+ M_LWM_OB,
+ M_LWP_AB,
+ M_LWP_OB,
M_LWR_A,
M_LWR_AB,
+ M_LWR_OB,
M_LWU_AB,
+ M_LWU_OB,
M_MSGSND,
M_MSGLD,
M_MSGLD_T,
M_NOR_I,
M_OR_I,
M_PREF_AB,
+ M_PREF_OB,
M_REM_3,
M_REM_3I,
M_REMU_3,
M_S_DAB,
M_S_S,
M_SC_AB,
+ M_SC_OB,
M_SCD_AB,
+ M_SCD_OB,
M_SD_A,
M_SD_OB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
+ M_SDC2_OB,
M_SDC3_AB,
M_SDL_AB,
+ M_SDL_OB,
+ M_SDM_AB,
+ M_SDM_OB,
+ M_SDP_AB,
+ M_SDP_OB,
M_SDR_AB,
+ M_SDR_OB,
M_SEQ,
M_SEQ_I,
M_SGE,
M_SWC1_AB,
M_SWC2_A,
M_SWC2_AB,
+ M_SWC2_OB,
M_SWC3_A,
M_SWC3_AB,
M_SWL_A,
M_SWL_AB,
+ M_SWL_OB,
+ M_SWM_AB,
+ M_SWM_OB,
+ M_SWP_AB,
+ M_SWP_OB,
M_SWR_A,
M_SWR_AB,
+ M_SWR_OB,
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
extern const struct mips_opcode mips16_opcodes[];
extern const int bfd_mips16_num_opcodes;
+/* These are the bitmasks and shift counts used for the different
+ fields in the instruction formats. Other than MAJOR, no masks are
+ provided for the fixed portions of an instruction, since they are
+ not needed. */
+
+#define MICROMIPSOP_MASK_MAJOR 0x3f
+#define MICROMIPSOP_SH_MAJOR 26
+#define MICROMIPSOP_MASK_IMMEDIATE 0xffff
+#define MICROMIPSOP_SH_IMMEDIATE 0
+#define MICROMIPSOP_MASK_DELTA 0xffff
+#define MICROMIPSOP_SH_DELTA 0
+#define MICROMIPSOP_MASK_CODE10 0x3ff
+#define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
+#define MICROMIPSOP_MASK_TRAP 0xf
+#define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
+#define MICROMIPSOP_MASK_SHAMT 0x1f
+#define MICROMIPSOP_SH_SHAMT 11
+#define MICROMIPSOP_MASK_TARGET 0x3ffffff
+#define MICROMIPSOP_SH_TARGET 0
+#define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
+#define MICROMIPSOP_SH_EXTLSB 6
+#define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
+#define MICROMIPSOP_SH_EXTMSBD 11
+#define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
+#define MICROMIPSOP_SH_INSMSB 11
+#define MICROMIPSOP_MASK_CODE 0x3ff
+#define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
+#define MICROMIPSOP_MASK_CODE2 0x3ff
+#define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
+#define MICROMIPSOP_MASK_CACHE 0x1f
+#define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
+#define MICROMIPSOP_MASK_SEL 0x7
+#define MICROMIPSOP_SH_SEL 11
+#define MICROMIPSOP_MASK_OFFSET12 0xfff
+#define MICROMIPSOP_SH_OFFSET12 0
+#define MICROMIPSOP_MASK_STYPE 0x1f
+#define MICROMIPSOP_SH_STYPE 16
+#define MICROMIPSOP_MASK_OFFSET10 0x3ff
+#define MICROMIPSOP_SH_OFFSET10 6
+#define MICROMIPSOP_MASK_RS 0x1f
+#define MICROMIPSOP_SH_RS 16
+#define MICROMIPSOP_MASK_RT 0x1f
+#define MICROMIPSOP_SH_RT 21
+#define MICROMIPSOP_MASK_RD 0x1f
+#define MICROMIPSOP_SH_RD 11
+#define MICROMIPSOP_MASK_FS 0x1f
+#define MICROMIPSOP_SH_FS 16
+#define MICROMIPSOP_MASK_FT 0x1f
+#define MICROMIPSOP_SH_FT 21
+#define MICROMIPSOP_MASK_FD 0x1f
+#define MICROMIPSOP_SH_FD 11
+#define MICROMIPSOP_MASK_FR 0x1f
+#define MICROMIPSOP_SH_FR 6
+#define MICROMIPSOP_MASK_RS3 0x1f
+#define MICROMIPSOP_SH_RS3 6
+#define MICROMIPSOP_MASK_PREFX 0x1f
+#define MICROMIPSOP_SH_PREFX 11
+#define MICROMIPSOP_MASK_BCC 0x7
+#define MICROMIPSOP_SH_BCC 18
+#define MICROMIPSOP_MASK_CCC 0x7
+#define MICROMIPSOP_SH_CCC 13
+#define MICROMIPSOP_MASK_COPZ 0x7fffff
+#define MICROMIPSOP_SH_COPZ 3
+
+#define MICROMIPSOP_MASK_MB 0x7
+#define MICROMIPSOP_SH_MB 23
+#define MICROMIPSOP_MASK_MC 0x7
+#define MICROMIPSOP_SH_MC 4
+#define MICROMIPSOP_MASK_MD 0x7
+#define MICROMIPSOP_SH_MD 7
+#define MICROMIPSOP_MASK_ME 0x7
+#define MICROMIPSOP_SH_ME 1
+#define MICROMIPSOP_MASK_MF 0x7
+#define MICROMIPSOP_SH_MF 3
+#define MICROMIPSOP_MASK_MG 0x7
+#define MICROMIPSOP_SH_MG 0
+#define MICROMIPSOP_MASK_MH 0x7
+#define MICROMIPSOP_SH_MH 7
+#define MICROMIPSOP_MASK_MI 0x7
+#define MICROMIPSOP_SH_MI 7
+#define MICROMIPSOP_MASK_MJ 0x1f
+#define MICROMIPSOP_SH_MJ 0
+#define MICROMIPSOP_MASK_ML 0x7
+#define MICROMIPSOP_SH_ML 4
+#define MICROMIPSOP_MASK_MM 0x7
+#define MICROMIPSOP_SH_MM 1
+#define MICROMIPSOP_MASK_MN 0x7
+#define MICROMIPSOP_SH_MN 4
+#define MICROMIPSOP_MASK_MP 0x1f
+#define MICROMIPSOP_SH_MP 5
+#define MICROMIPSOP_MASK_MQ 0x7
+#define MICROMIPSOP_SH_MQ 7
+
+#define MICROMIPSOP_MASK_IMMA 0x7f
+#define MICROMIPSOP_SH_IMMA 0
+#define MICROMIPSOP_MASK_IMMB 0x7
+#define MICROMIPSOP_SH_IMMB 1
+#define MICROMIPSOP_MASK_IMMC 0xf
+#define MICROMIPSOP_SH_IMMC 0
+#define MICROMIPSOP_MASK_IMMD 0x3ff
+#define MICROMIPSOP_SH_IMMD 0
+#define MICROMIPSOP_MASK_IMME 0x7f
+#define MICROMIPSOP_SH_IMME 0
+#define MICROMIPSOP_MASK_IMMF 0xf
+#define MICROMIPSOP_SH_IMMF 0
+#define MICROMIPSOP_MASK_IMMG 0xf
+#define MICROMIPSOP_SH_IMMG 0
+#define MICROMIPSOP_MASK_IMMH 0xf
+#define MICROMIPSOP_SH_IMMH 0
+#define MICROMIPSOP_MASK_IMMI 0x7f
+#define MICROMIPSOP_SH_IMMI 0
+#define MICROMIPSOP_MASK_IMMJ 0xf
+#define MICROMIPSOP_SH_IMMJ 0
+#define MICROMIPSOP_MASK_IMML 0xf
+#define MICROMIPSOP_SH_IMML 0
+#define MICROMIPSOP_MASK_IMMM 0x7
+#define MICROMIPSOP_SH_IMMM 1
+#define MICROMIPSOP_MASK_IMMN 0x3
+#define MICROMIPSOP_SH_IMMN 4
+#define MICROMIPSOP_MASK_IMMO 0xf
+#define MICROMIPSOP_SH_IMMO 0
+#define MICROMIPSOP_MASK_IMMP 0x1f
+#define MICROMIPSOP_SH_IMMP 0
+#define MICROMIPSOP_MASK_IMMQ 0x7fffff
+#define MICROMIPSOP_SH_IMMQ 0
+#define MICROMIPSOP_MASK_IMMU 0x1f
+#define MICROMIPSOP_SH_IMMU 0
+#define MICROMIPSOP_MASK_IMMW 0x3f
+#define MICROMIPSOP_SH_IMMW 1
+#define MICROMIPSOP_MASK_IMMX 0xf
+#define MICROMIPSOP_SH_IMMX 1
+#define MICROMIPSOP_MASK_IMMY 0x1ff
+#define MICROMIPSOP_SH_IMMY 1
+
+/* Placeholders for fields that only exist in the traditional 32-bit
+ instruction encoding; see the comment above for details. */
+#define MICROMIPSOP_MASK_CODE20 0
+#define MICROMIPSOP_SH_CODE20 0
+#define MICROMIPSOP_MASK_PERFREG 0
+#define MICROMIPSOP_SH_PERFREG 0
+#define MICROMIPSOP_MASK_CODE19 0
+#define MICROMIPSOP_SH_CODE19 0
+#define MICROMIPSOP_MASK_ALN 0
+#define MICROMIPSOP_SH_ALN 0
+#define MICROMIPSOP_MASK_VECBYTE 0
+#define MICROMIPSOP_SH_VECBYTE 0
+#define MICROMIPSOP_MASK_VECALIGN 0
+#define MICROMIPSOP_SH_VECALIGN 0
+#define MICROMIPSOP_MASK_DSPACC 0
+#define MICROMIPSOP_SH_DSPACC 0
+#define MICROMIPSOP_MASK_DSPACC_S 0
+#define MICROMIPSOP_SH_DSPACC_S 0
+#define MICROMIPSOP_MASK_DSPSFT 0
+#define MICROMIPSOP_SH_DSPSFT 0
+#define MICROMIPSOP_MASK_DSPSFT_7 0
+#define MICROMIPSOP_SH_DSPSFT_7 0
+#define MICROMIPSOP_MASK_SA3 0
+#define MICROMIPSOP_SH_SA3 0
+#define MICROMIPSOP_MASK_SA4 0
+#define MICROMIPSOP_SH_SA4 0
+#define MICROMIPSOP_MASK_IMM8 0
+#define MICROMIPSOP_SH_IMM8 0
+#define MICROMIPSOP_MASK_IMM10 0
+#define MICROMIPSOP_SH_IMM10 0
+#define MICROMIPSOP_MASK_WRDSP 0
+#define MICROMIPSOP_SH_WRDSP 0
+#define MICROMIPSOP_MASK_RDDSP 0
+#define MICROMIPSOP_SH_RDDSP 0
+#define MICROMIPSOP_MASK_BP 0
+#define MICROMIPSOP_SH_BP 0
+#define MICROMIPSOP_MASK_MT_U 0
+#define MICROMIPSOP_SH_MT_U 0
+#define MICROMIPSOP_MASK_MT_H 0
+#define MICROMIPSOP_SH_MT_H 0
+#define MICROMIPSOP_MASK_MTACC_T 0
+#define MICROMIPSOP_SH_MTACC_T 0
+#define MICROMIPSOP_MASK_MTACC_D 0
+#define MICROMIPSOP_SH_MTACC_D 0
+#define MICROMIPSOP_MASK_BBITIND 0
+#define MICROMIPSOP_SH_BBITIND 0
+#define MICROMIPSOP_MASK_CINSPOS 0
+#define MICROMIPSOP_SH_CINSPOS 0
+#define MICROMIPSOP_MASK_CINSLM1 0
+#define MICROMIPSOP_SH_CINSLM1 0
+#define MICROMIPSOP_MASK_SEQI 0
+#define MICROMIPSOP_SH_SEQI 0
+#define MICROMIPSOP_SH_OFFSET_A 0
+#define MICROMIPSOP_MASK_OFFSET_A 0
+#define MICROMIPSOP_SH_OFFSET_B 0
+#define MICROMIPSOP_MASK_OFFSET_B 0
+#define MICROMIPSOP_SH_OFFSET_C 0
+#define MICROMIPSOP_MASK_OFFSET_C 0
+#define MICROMIPSOP_SH_RZ 0
+#define MICROMIPSOP_MASK_RZ 0
+#define MICROMIPSOP_SH_FZ 0
+#define MICROMIPSOP_MASK_FZ 0
+
+/* These are the characters which may appears in the args field of a microMIPS
+ instruction. They appear in the order in which the fields appear
+ when the instruction is used. Commas and parentheses in the args
+ string are ignored when assembling, and written into the output
+ when disassembling.
+
+ The followings are for 16-bit microMIPS instructions.
+
+ "ma" must be $28
+ "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
+ The same register used as both source and target.
+ "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
+ "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
+ The same register used as both source and target.
+ "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
+ "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
+ "mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7
+ "mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7
+ ("mh" and "mi" form a valid 3-bit register pair)
+ "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
+ "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
+ "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
+ "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
+ "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
+ "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
+ "mr" must be program counter
+ "ms" must be $29
+ "mt" must be the same as the previous register
+ "mx" must be the same as the destination register
+ "my" must be $31
+ "mz" must be $0
+
+ "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
+ "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
+ "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
+ 32768, 65535) (MICROMIPSOP_*_IMMC)
+ "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
+ "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
+ "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
+ "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
+ "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
+ "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
+ "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
+ "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
+ "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
+ "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
+ "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
+ "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
+ "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
+ "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
+ "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
+ "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
+ "mZ" must be zero
+
+ In most cases 32-bit microMIPS instructions use the same characters
+ as MIPS (with ADDIUPC being a notable exception, but there are some
+ others too).
+
+ "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
+ "1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
+ "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
+ ">" shift amount between 32 and 63, stored after subtracting 32
+ (MICROMIPSOP_*_SHAMT)
+ "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
+ "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
+ "a" 26-bit target address (MICROMIPSOP_*_TARGET)
+ "b" 5-bit base register (MICROMIPSOP_*_RS)
+ "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
+ "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
+ "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
+ "i" 16 bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
+ "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
+ "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
+ "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
+ "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
+ "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
+ "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
+ "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
+ "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
+ "t" 5-bit target register (MICROMIPSOP_*_RT)
+ "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
+ "v" 5-bit same register used as both source and destination
+ (MICROMIPSOP_*_RS)
+ "w" 5-bit same register used as both target and destination
+ (MICROMIPSOP_*_RT)
+ "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
+ "z" must be zero register
+ "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
+ "B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
+ "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
+
+ "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
+ LSB (MICROMIPSOP_*_EXTLSB).
+ Enforces: 0 <= pos < 32.
+ "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 0 < (pos+size) <= 32.
+ "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 0 < (pos+size) <= 32.
+ (Also used by DEXT w/ different limits, but limits for
+ that are checked by the M_DEXT macro.)
+ "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
+ Enforces: 32 <= pos < 64.
+ "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 32 < (pos+size) <= 64.
+ "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 32 < (pos+size) <= 64.
+ "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 32 < (pos+size) <= 64.
+
+ PC-relative addition (ADDIUPC) instruction:
+ "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
+ "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
+
+ Floating point instructions:
+ "D" 5-bit destination register (MICROMIPSOP_*_FD)
+ "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
+ "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
+ "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
+ "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
+ "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
+ "V" 5-bit same register used as floating source and destination or target
+ (MICROMIPSOP_*_FS)
+
+ Coprocessor instructions:
+ "E" 5-bit target register (MICROMIPSOP_*_RT)
+ "G" 5-bit destination register (MICROMIPSOP_*_RD)
+ "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
+ "+D" combined destination register ("G") and sel ("H") for CP0 ops,
+ for pretty-printing in disassembly only
+
+ Macro instructions:
+ "A" general 32 bit expression
+ "I" 32-bit immediate (value placed in imm_expr).
+ "+I" 32-bit immediate (value placed in imm2_expr).
+ "F" 64-bit floating point constant in .rdata
+ "L" 64-bit floating point constant in .lit8
+ "f" 32-bit floating point constant
+ "l" 32-bit floating point constant in .lit4
+
+ Other:
+ "()" parens surrounding optional value
+ "," separates operands
+ "+" start of extension sequence
+ "m" start of microMIPS extension sequence
+
+ Characters used so far, for quick reference when adding more:
+ "1234567890"
+ "<>(),+.|~"
+ "ABCDEFGHI KLMN RST V "
+ "abcd f hijklmnopqrstuvw yz"
+
+ Extension character sequences used so far ("+" followed by the
+ following), for quick reference when adding more:
+ ""
+ ""
+ "ABCDEFGHI"
+ ""
+
+ Extension character sequences used so far ("m" followed by the
+ following), for quick reference when adding more:
+ ""
+ ""
+ " BCDEFGHIJ LMNOPQ U WXYZ"
+ " bcdefghij lmn pq st xyz"
+*/
+
+extern const struct mips_opcode micromips_opcodes[];
+extern const int bfd_micromips_num_opcodes;
+
/* A NOP insn impemented as "or at,at,zero".
Used to implement -mfix-loongson2f. */
#define LOONGSON2F_NOP_INSN 0x00200825
+2011-07-24 Catherine Moore <clm@codesourcery.com>
+ Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * lib/ld-lib.exp (run_dump_test): Support distinct assembler
+ flags for the same source named multiple times.
+ * ld-mips-elf/jalx-1.s: New test source.
+ * ld-mips-elf/jalx-1.d: New test output.
+ * ld-mips-elf/jalx-1.ld: New test linker script.
+ * ld-mips-elf/jalx-2-main.s: New test source.
+ * ld-mips-elf/jalx-2-ex.s: Likewise.
+ * ld-mips-elf/jalx-2-printf.s: Likewise.
+ * ld-mips-elf/jalx-2.dd: New test output.
+ * ld-mips-elf/jalx-2.ld: New test linker script.
+ * ld-mips-elf/mips16-and-micromips.d: New test.
+ * ld-mips-elf/mips-elf.exp: Run the new tests
+
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* ld-x86-64/abs-k1om.d: New.
--- /dev/null
+#name: MIPS jalx-1
+#source: jalx-1.s
+#ld: -T jalx-1.ld
+#objdump: -d
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+88000000 <test>:
+88000000: f200 0002 jalx 88000008 <test1>
+88000004: 0000 0000 nop
+
+88000008 <test1>:
+88000008: 00851821 addu v1,a0,a1
+ \.\.\.
--- /dev/null
+ENTRY (test)
+_start_text_phys = 0x88000000;
+_start_text = _start_text_phys;
+
+SECTIONS
+{
+ .text _start_text : AT (ADDR (.text)) { *(.text) }
+}
--- /dev/null
+ .set noreorder
+ .set micromips
+ .ent test
+ .globl test
+test:
+ jalx test1
+ nop
+
+ .set nomicromips
+test1:
+ addu $3, $4, $5
+ .end test
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
--- /dev/null
+ .file 1 "jalx-2-ex.c"
+ .section .mdebug.abi32
+ .previous
+ .gnu_attribute 4, 1
+ .abicalls
+ .option pic0
+ .text
+ .align 2
+ .globl external_function
+ .set nomips16
+ .set nomicromips
+ .ent external_function
+ .type external_function, @function
+external_function:
+ .frame $fp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0
+ .mask 0x40000000,-4
+ .fmask 0x00000000,0
+ .set noreorder
+ .set nomacro
+
+ addiu $sp,$sp,-8
+ sw $fp,4($sp)
+ move $fp,$sp
+ move $sp,$fp
+ lw $fp,4($sp)
+ addiu $sp,$sp,8
+ j $31
+ nop
+
+ .set macro
+ .set reorder
+ .end external_function
+ .size external_function, .-external_function
+ .ident "GCC: (Sourcery G++ Lite 4.4-999999 - Preview) 4.4.1"
--- /dev/null
+ .file 1 "jalx-2-main.c"
+ .section .mdebug.abi32
+ .previous
+ .gnu_attribute 4, 1
+ .abicalls
+ .option pic0
+ .text
+ .align 2
+ .globl internal_function
+ .set nomips16
+ .set micromips
+ .ent internal_function
+ .type internal_function, @function
+internal_function:
+ .frame $fp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0
+ .mask 0x40000000,-4
+ .fmask 0x00000000,0
+ .set noreorder
+ .set nomacro
+
+ addiu $sp,$sp,-8
+ sw $fp,4($sp)
+ move $fp,$sp
+ move $sp,$fp
+ lw $fp,4($sp)
+ jraddiusp 8
+ .set macro
+ .set reorder
+ .end internal_function
+ .size internal_function, .-internal_function
+ .rdata
+ .align 2
+$LC0:
+ .ascii "hello world\012\000"
+ .text
+ .align 2
+ .globl main
+ .set nomips16
+ .set micromips
+ .ent main
+ .type main, @function
+main:
+ .frame $fp,32,$31 # vars= 0, regs= 2/0, args= 16, gp= 8
+ .mask 0xc0000000,-4
+ .fmask 0x00000000,0
+ .set noreorder
+ .set nomacro
+
+ addiu $sp,$sp,-32
+ sw $31,28($sp)
+ sw $fp,24($sp)
+ move $fp,$sp
+ sw $4,32($fp)
+ sw $5,36($fp)
+ lui $2,%hi($LC0)
+ addiu $4,$2,%lo($LC0)
+ jal printf
+ nop
+
+ jal internal_function
+ nop
+
+ jal external_function
+ nop
+
+ move $sp,$fp
+ lw $31,28($sp)
+ lw $fp,24($sp)
+ jraddiusp 32
+ .set macro
+ .set reorder
+ .end main
+ .size main, .-main
+ .ident "GCC: (Sourcery G++ Lite 4.4-999999 - Preview) 4.4.1"
--- /dev/null
+ .file 1 "jalx-2-printf.c"
+ .section .mdebug.abi32
+ .previous
+ .gnu_attribute 4, 1
+ .abicalls
+ .text
+ .align 2
+ .globl printf
+ .set nomips16
+ .set micromips
+ .ent printf
+ .type printf, @function
+printf:
+ .frame $fp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0
+ .mask 0x40000000,-4
+ .fmask 0x00000000,0
+ .set noreorder
+ .set nomacro
+
+ addiu $sp,$sp,-8
+ sw $fp,4($sp)
+ move $fp,$sp
+ sw $5,12($fp)
+ sw $6,16($fp)
+ sw $7,20($fp)
+ sw $4,8($fp)
+ move $2,$0
+ move $sp,$fp
+ lw $fp,4($sp)
+ jraddiusp 8
+ .set macro
+ .set reorder
+ .end printf
+ .size printf, .-printf
+ .ident "GCC: (Sourcery G++ Lite 4.4-999999 - Preview) 4.4.1"
--- /dev/null
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+04400000 <external_function>:
+ 4400000: 27bdfff8 addiu sp,sp,-8
+ 4400004: afbe0004 sw s8,4\(sp\)
+ 4400008: 03a0f021 move s8,sp
+ 440000c: 03c0e821 move sp,s8
+ 4400010: 8fbe0004 lw s8,4\(sp\)
+ 4400014: 27bd0008 addiu sp,sp,8
+ 4400018: 03e00008 jr ra
+ 440001c: 00000000 nop
+
+04400020 <internal_function>:
+ 4400020: 4fb0 addiu sp,sp,-8
+ 4400022: cbc1 sw s8,4\(sp\)
+ 4400024: 0fdd move s8,sp
+ 4400026: 0fbe move sp,s8
+ 4400028: 4bc1 lw s8,4\(sp\)
+ 440002a: 4702 jraddiusp 8
+
+0440002c <main>:
+ 440002c: 4ff1 addiu sp,sp,-32
+ 440002e: cbe7 sw ra,28\(sp\)
+ 4400030: cbc6 sw s8,24\(sp\)
+ 4400032: 0fdd move s8,sp
+ 4400034: f89e 0020 sw a0,32\(s8\)
+ 4400038: f8be 0024 sw a1,36\(s8\)
+ 440003c: 41a2 0440 lui v0,0x440
+ 4400040: 3082 02a0 addiu a0,v0,672
+ 4400044: f110 0028 jalx 44000a0 <_PROCEDURE_LINKAGE_TABLE_\+0x20>
+ 4400048: 0000 0000 nop
+ 440004c: f620 0010 jal 4400020 <internal_function>
+ 4400050: 0000 0000 nop
+ 4400054: f110 0000 jalx 4400000 <external_function>
+ 4400058: 0000 0000 nop
+ 440005c: 0fbe move sp,s8
+ 440005e: 4be7 lw ra,28\(sp\)
+ 4400060: 4bc6 lw s8,24\(sp\)
+ 4400062: 4708 jraddiusp 32
+ \.\.\.
+
+Disassembly of section \.plt:
+
+04400080 <_PROCEDURE_LINKAGE_TABLE_>:
+ 4400080: 3c1c0440 lui gp,0x440
+ 4400084: 8f9900d8 lw t9,216\(gp\)
+ 4400088: 279c00d8 addiu gp,gp,216
+ 440008c: 031cc023 subu t8,t8,gp
+ 4400090: 03e07821 move t7,ra
+ 4400094: 0018c082 srl t8,t8,0x2
+ 4400098: 0320f809 jalr t9
+ 440009c: 2718fffe addiu t8,t8,-2
+ 44000a0: 3c0f0440 lui t7,0x440
+ 44000a4: 8df900e0 lw t9,224\(t7\)
+ 44000a8: 03200008 jr t9
+ 44000ac: 25f800e0 addiu t8,t7,224
--- /dev/null
+ENTRY (internal_function)
+_start_text_phys = 0x4400000;
+_start_text = _start_text_phys;
+
+SECTIONS
+{
+ .text _start_text : AT (ADDR (.text)) { *(.text) }
+}
# MIPS branch offset final link checking.
run_dump_test "branch-misc-1"
+# Jalx test
+run_dump_test "jalx-1"
+
+if { $linux_gnu } {
+ run_ld_link_tests [list \
+ [list "Dummy shared library for JALX test 2" \
+ "-shared -nostdlib -melf32btsmip" \
+ "-G0 -EB -mmicromips -no-mdebug -mabi=32 -march=mips32r2 -KPIC" \
+ { jalx-2-printf.s } \
+ {} \
+ "libjalx-2.so"] \
+ [list "Dummy external function for JALX test 2" \
+ "-r -melf32btsmip" \
+ "-G0 -EB -no-mdebug -mabi=32 -march=mips32r2 -mno-shared -call_nonpic" \
+ { jalx-2-ex.s } \
+ {} \
+ "jalx-2-ex.o.r"] \
+ [list "MIPS JALX test 2" \
+ "-nostdlib -T jalx-2.ld tmpdir/libjalx-2.so tmpdir/jalx-2-ex.o.r -melf32btsmip" \
+ "-G0 -EB -mmicromips -no-mdebug -mabi=32 -march=mips32r2 -mno-shared -call_nonpic" \
+ { jalx-2-main.s } \
+ { { objdump -d jalx-2.dd } } \
+ "jalx-2"]]
+}
+
# Test multi-got link. We only do this on GNU/Linux because it requires
# the "traditional" emulations.
if { $linux_gnu } {
run_dump_test "jr-to-b-1"
run_dump_test "jr-to-b-2"
}
+
+# MIPS16 and microMIPS interlinking test.
+run_dump_test "mips16-and-micromips"
--- /dev/null
+#name: MIPS16 and microMIPS interlink
+#source: ../../../gas/testsuite/gas/mips/nop.s -mips16
+#source: ../../../gas/testsuite/gas/mips/nop.s -mmicromips
+#ld: -e0
+#error: \A.*: .*\.o: ASE mismatch: linking microMIPS module with previous MIPS16 modules[\n\r]+.*: failed to merge target specific data of file .*\.o\Z
set opts(error) {}
set opts(warning) {}
set opts(objcopy_linked_file) {}
- set asflags(${file}.s) {}
foreach i $opt_array {
set opt_name [lindex $i 0]
warning {}
error {}
source {
- # Move any source-specific as-flags to a separate array to
+ # Move any source-specific as-flags to a separate list to
# simplify processing.
if { [llength $opt_val] > 1 } {
- set asflags([lindex $opt_val 0]) [lrange $opt_val 1 end]
+ lappend asflags [lrange $opt_val 1 end]
set opt_val [lindex $opt_val 0]
} else {
- set asflags($opt_val) {}
+ lappend asflags {}
}
}
default {
if { $opts(source) == "" } {
set sourcefiles [list ${file}.s]
+ set asflags [list ""]
} else {
set sourcefiles {}
foreach sf $opts(source) {
} else {
lappend sourcefiles "$srcdir/$subdir/$sf"
}
- # Must have asflags indexed on source name.
- set asflags($srcdir/$subdir/$sf) $asflags($sf)
}
}
set objfiles {}
for { set i 0 } { $i < [llength $sourcefiles] } { incr i } {
set sourcefile [lindex $sourcefiles $i]
+ set sourceasflags [lindex $asflags $i]
set objfile "tmpdir/dump$i.o"
catch "exec rm -f $objfile" exec_output
lappend objfiles $objfile
- set cmd "$AS $ASFLAGS $opts(as) $asflags($sourcefile) -o $objfile $sourcefile"
+ set cmd "$AS $ASFLAGS $opts(as) $sourceasflags -o $objfile $sourcefile"
send_log "$cmd\n"
set cmdret [remote_exec host [concat sh -c [list "$cmd 2>&1"]] "" "/dev/null" "ld.tmp"]
+2011-07-24 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c: New file.
+ * mips-dis.c (micromips_to_32_reg_b_map): New array.
+ (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
+ (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
+ (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
+ (micromips_to_32_reg_q_map): Likewise.
+ (micromips_imm_b_map, micromips_imm_c_map): Likewise.
+ (micromips_ase): New variable.
+ (is_micromips): New function.
+ (set_default_mips_dis_options): Handle microMIPS ASE.
+ (print_insn_micromips): New function.
+ (is_compressed_mode_p): Likewise.
+ (_print_insn_mips): Handle microMIPS instructions.
+ * Makefile.am (CFILES): Add micromips-opc.c.
+ * configure.in (bfd_mips_arch): Add micromips-opc.lo.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+
+ * mips-dis.c (micromips_to_32_reg_h_map): New variable.
+ (micromips_to_32_reg_i_map): Likewise.
+ (micromips_to_32_reg_m_map): Likewise.
+ (micromips_to_32_reg_n_map): New macro.
+
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips-opc.c (NODS): New macro.
mep-ibld.c \
mep-opc.c \
microblaze-dis.c \
+ micromips-opc.c \
mips-dis.c \
mips-opc.c \
mips16-opc.c \
mep-ibld.c \
mep-opc.c \
microblaze-dis.c \
+ micromips-opc.c \
mips-dis.c \
mips-opc.c \
mips16-opc.c \
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;;
bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;;
- bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
+ bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo micromips-opc.lo" ;;
bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;
bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;;
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;;
bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;;
- bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
+ bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo micromips-opc.lo" ;;
bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;
bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;;
--- /dev/null
+/* micromips-opc.c. microMIPS opcode table.
+ Copyright 2008 Free Software Foundation, Inc.
+ Contributed by Chao-ying Fu, MIPS Technologies, Inc.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include <stdio.h>
+#include "sysdep.h"
+#include "opcode/mips.h"
+
+#define UBD INSN_UNCOND_BRANCH_DELAY
+#define CBD INSN_COND_BRANCH_DELAY
+#define TRAP INSN_TRAP
+#define SM INSN_STORE_MEMORY
+#define BD16 INSN2_BRANCH_DELAY_16BIT /* Used in pinfo2. */
+#define BD32 INSN2_BRANCH_DELAY_32BIT /* Used in pinfo2. */
+
+/* For 16-bit/32-bit microMIPS instructions. They are used in pinfo2. */
+#define UBR INSN2_UNCOND_BRANCH
+#define CBR INSN2_COND_BRANCH
+#define MOD_mb INSN2_MOD_GPR_MB
+#define MOD_mc INSN2_MOD_GPR_MC
+#define MOD_md INSN2_MOD_GPR_MD
+#define MOD_me INSN2_MOD_GPR_ME
+#define MOD_mf INSN2_MOD_GPR_MF
+#define MOD_mg INSN2_MOD_GPR_MG
+#define MOD_mhi INSN2_MOD_GPR_MHI
+#define MOD_mj INSN2_MOD_GPR_MJ
+#define MOD_ml MOD_mc /* Reuse, since the bit position is the same. */
+#define MOD_mm INSN2_MOD_GPR_MM
+#define MOD_mn INSN2_MOD_GPR_MN
+#define MOD_mp INSN2_MOD_GPR_MP
+#define MOD_mq INSN2_MOD_GPR_MQ
+#define MOD_sp INSN2_MOD_SP
+#define RD_31 INSN2_READ_GPR_31
+#define RD_gp INSN2_READ_GP
+#define RD_pc INSN2_READ_PC
+
+/* For 32-bit microMIPS instructions. */
+#define WR_s INSN2_WRITE_GPR_S /* Used in pinfo2. */
+#define WR_d INSN_WRITE_GPR_D
+#define WR_t INSN_WRITE_GPR_T
+#define WR_31 INSN_WRITE_GPR_31
+#define WR_D INSN_WRITE_FPR_D
+#define WR_T INSN_WRITE_FPR_T
+#define WR_S INSN_WRITE_FPR_S
+#define WR_CC INSN_WRITE_COND_CODE
+
+#define RD_s INSN_READ_GPR_S
+#define RD_b INSN_READ_GPR_S
+#define RD_t INSN_READ_GPR_T
+#define RD_T INSN_READ_FPR_T
+#define RD_S INSN_READ_FPR_S
+#define RD_R INSN_READ_FPR_R
+#define RD_D INSN2_READ_FPR_D /* Used in pinfo2. */
+#define RD_CC INSN_READ_COND_CODE
+#define RD_C0 INSN_COP
+#define RD_C1 INSN_COP
+#define RD_C2 INSN_COP
+#define WR_C0 INSN_COP
+#define WR_C1 INSN_COP
+#define WR_C2 INSN_COP
+#define CP INSN_COP
+
+#define WR_HI INSN_WRITE_HI
+#define RD_HI INSN_READ_HI
+
+#define WR_LO INSN_WRITE_LO
+#define RD_LO INSN_READ_LO
+
+#define WR_HILO WR_HI|WR_LO
+#define RD_HILO RD_HI|RD_LO
+#define MOD_HILO WR_HILO|RD_HILO
+
+/* Reuse INSN_ISA1 for 32-bit microMIPS ISA. All instructions in I1
+ are accepted as 32-bit microMIPS ISA.
+ Reuse INSN_ISA3 for 64-bit microMIPS ISA. All instructions in I3
+ are accepted as 64-bit microMIPS ISA. */
+#define I1 INSN_ISA1
+#define I3 INSN_ISA3
+
+const struct mips_opcode micromips_opcodes[] =
+{
+/* These instructions appear first so that the disassembler will find
+ them first. The assemblers uses a hash table based on the
+ instruction name anyhow. */
+/* name, args, match, mask, pinfo, pinfo2, membership */
+{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
+{"pref", "k,o(b)", 0, (int) M_PREF_OB, INSN_MACRO, 0, I1 },
+{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
+{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I1 },
+{"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1 },
+{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"ehb", "", 0x00001800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"pause", "", 0x00002800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"li", "md,mI", 0xec00, 0xfc00, 0, MOD_md, I1 },
+{"li", "t,j", 0x30000000, 0xfc1f0000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
+{"li", "t,i", 0x50000000, 0xfc1f0000, WR_t, INSN2_ALIAS, I1 }, /* ori */
+#if 0
+/* Disabled until we can handle 48-bit opcodes. */
+{"li", "s,I", 0x7c0000010000, 0xfc00001f0000, WR_t, 0, I3 }, /* li48 */
+#endif
+{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
+{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
+{"move", "mp,mj", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 },
+{"move", "d,s", 0x58000150, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I3 }, /* daddu */
+{"move", "d,s", 0x00000150, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I1 }, /* addu */
+{"move", "d,s", 0x00000290, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I1 }, /* or */
+{"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1 },
+{"b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1 }, /* beq 0, 0 */
+{"b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1 }, /* bgez 0 */
+{"bal", "p", 0x40600000, 0xffff0000, UBD|WR_31, INSN2_ALIAS|BD32, I1 }, /* bgezal 0 */
+{"bals", "p", 0x42600000, 0xffff0000, UBD|WR_31, INSN2_ALIAS|BD16, I1 }, /* bgezals 0 */
+{"bc", "p", 0x40e00000, 0xffff0000, TRAP, INSN2_ALIAS|UBR, I1 }, /* beqzc 0 */
+
+{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
+{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
+{"add.d", "D,V,T", 0x54000130, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"add.s", "D,V,T", 0x54000030, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+{"add.ps", "D,V,T", 0x54000230, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"addi", "t,r,j", 0x10000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"addiu", "mp,mj,mZ", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"addiu", "md,ms,mW", 0x6c01, 0xfc01, 0, MOD_md|MOD_sp, I1 }, /* addiur1sp */
+{"addiu", "md,mc,mB", 0x6c00, 0xfc01, 0, MOD_md|MOD_mc, I1 }, /* addiur2 */
+{"addiu", "ms,mt,mY", 0x4c01, 0xfc01, 0, MOD_sp, I1 }, /* addiusp */
+{"addiu", "mp,mt,mX", 0x4c00, 0xfc01, 0, MOD_mp, I1 }, /* addius5 */
+{"addiu", "mb,mr,mQ", 0x78000000, 0xfc000000, 0, MOD_mb|RD_pc, I1 }, /* addiupc */
+{"addiu", "t,r,j", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"addiupc", "mb,mQ", 0x78000000, 0xfc000000, 0, MOD_mb|RD_pc, I1 },
+{"addiur1sp", "md,mW", 0x6c01, 0xfc01, 0, MOD_md|MOD_sp, I1 },
+{"addiur2", "md,mc,mB", 0x6c00, 0xfc01, 0, MOD_md|MOD_mc, I1 },
+{"addiusp", "mY", 0x4c01, 0xfc01, 0, MOD_sp, I1 },
+{"addius5", "mp,mX", 0x4c00, 0xfc01, 0, MOD_mp, I1 },
+{"addu", "mp,mj,mz", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"addu", "mp,mz,mj", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"addu", "md,me,ml", 0x0400, 0xfc01, 0, MOD_md|MOD_me|MOD_ml, I1 },
+{"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
+/* We have no flag to mark the read from "y", so we use TRAP to disable
+ delay slot scheduling of ALNV.PS altogether. */
+{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, TRAP|WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"and", "mf,mt,mg", 0x4480, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"and", "mf,mg,mx", 0x4480, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
+{"andi", "md,mc,mC", 0x2c00, 0xfc00, 0, MOD_md|MOD_mc, I1 },
+{"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+/* b is at the top of the table. */
+/* bal is at the top of the table. */
+{"bc1f", "p", 0x43800000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1f", "N,p", 0x43800000, 0xffe30000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1fl", "p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc1fl", "N,p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc2f", "p", 0x42800000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc2f", "N,p", 0x42800000, 0xffe30000, CBD|RD_CC, 0, I1 },
+{"bc2fl", "p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1 },
+{"bc2fl", "N,p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1 },
+{"bc1t", "p", 0x43a00000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1t", "N,p", 0x43a00000, 0xffe30000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1tl", "p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc1tl", "N,p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc2t", "p", 0x42a00000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc2t", "N,p", 0x42a00000, 0xffe30000, CBD|RD_CC, 0, I1 },
+{"bc2tl", "p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1 },
+{"bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1 },
+{"beqz", "md,mE", 0x8c00, 0xfc00, CBD, MOD_md, I1 },
+{"beqz", "s,p", 0x94000000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"beqzc", "s,p", 0x40e00000, 0xffe00000, TRAP|RD_s, CBR, I1 },
+{"beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1 },
+{"beq", "md,mz,mE", 0x8c00, 0xfc00, CBD, MOD_md, I1 }, /* beqz */
+{"beq", "mz,md,mE", 0x8c00, 0xfc00, CBD, MOD_md, I1 }, /* beqz */
+{"beq", "s,t,p", 0x94000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
+{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
+{"beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1 },
+{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1 },
+{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
+{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
+{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I1 },
+{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I1 },
+{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
+{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
+{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I1 },
+{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I1 },
+{"bgez", "s,p", 0x40400000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bgezl", "s,p", 0, (int) M_BGEZL, INSN_MACRO, 0, I1 },
+{"bgezal", "s,p", 0x40600000, 0xffe00000, CBD|RD_s|WR_31, BD32, I1 },
+{"bgezals", "s,p", 0x42600000, 0xffe00000, CBD|RD_s|WR_31, BD16, I1 },
+{"bgezall", "s,p", 0, (int) M_BGEZALL, INSN_MACRO, 0, I1 },
+{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
+{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
+{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I1 },
+{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I1 },
+{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
+{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
+{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I1 },
+{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I1 },
+{"bgtz", "s,p", 0x40c00000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bgtzl", "s,p", 0, (int) M_BGTZL, INSN_MACRO, 0, I1 },
+{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
+{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
+{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I1 },
+{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I1 },
+{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
+{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
+{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I1 },
+{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I1 },
+{"blez", "s,p", 0x40800000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"blezl", "s,p", 0, (int) M_BLEZL, INSN_MACRO, 0, I1 },
+{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
+{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
+{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I1 },
+{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I1 },
+{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
+{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
+{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I1 },
+{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I1 },
+{"bltz", "s,p", 0x40000000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bltzl", "s,p", 0, (int) M_BLTZL, INSN_MACRO, 0, I1 },
+{"bltzal", "s,p", 0x40200000, 0xffe00000, CBD|RD_s|WR_31, BD32, I1 },
+{"bltzals", "s,p", 0x42200000, 0xffe00000, CBD|RD_s|WR_31, BD16, I1 },
+{"bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1 },
+{"bnez", "md,mE", 0xac00, 0xfc00, CBD, MOD_md, I1 },
+{"bnez", "s,p", 0xb4000000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bnezc", "s,p", 0x40a00000, 0xffe00000, TRAP|RD_s, CBR, I1 },
+{"bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1 },
+{"bne", "md,mz,mE", 0xac00, 0xfc00, CBD, MOD_md, I1 }, /* bnez */
+{"bne", "mz,md,mE", 0xac00, 0xfc00, CBD, MOD_md, I1 }, /* bnez */
+{"bne", "s,t,p", 0xb4000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
+{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
+{"bnel", "s,t,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1 },
+{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I1 },
+{"break", "", 0x4680, 0xffff, TRAP, 0, I1 },
+{"break", "", 0x00000007, 0xffffffff, TRAP, 0, I1 },
+{"break", "mF", 0x4680, 0xfff0, TRAP, 0, I1 },
+{"break", "c", 0x00000007, 0xfc00ffff, TRAP, 0, I1 },
+{"break", "c,q", 0x00000007, 0xfc00003f, TRAP, 0, I1 },
+{"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.un.s", "M,S,T", 0x5400007c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.un.ps", "S,T", 0x5400087c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.un.ps", "M,S,T", 0x5400087c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.eq.d", "S,T", 0x540004bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.eq.d", "M,S,T", 0x540004bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.eq.s", "S,T", 0x540000bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.eq.s", "M,S,T", 0x540000bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.eq.ps", "S,T", 0x540008bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.eq.ps", "M,S,T", 0x540008bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ueq.d", "S,T", 0x540004fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ueq.d", "M,S,T", 0x540004fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ueq.s", "S,T", 0x540000fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ueq.s", "M,S,T", 0x540000fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ueq.ps", "S,T", 0x540008fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ueq.ps", "M,S,T", 0x540008fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.olt.d", "S,T", 0x5400053c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.olt.d", "M,S,T", 0x5400053c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.olt.s", "S,T", 0x5400013c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.olt.s", "M,S,T", 0x5400013c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.olt.ps", "S,T", 0x5400093c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.olt.ps", "M,S,T", 0x5400093c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ult.d", "S,T", 0x5400057c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ult.d", "M,S,T", 0x5400057c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ult.s", "S,T", 0x5400017c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ult.s", "M,S,T", 0x5400017c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ult.ps", "S,T", 0x5400097c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ult.ps", "M,S,T", 0x5400097c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ole.d", "S,T", 0x540005bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ole.d", "M,S,T", 0x540005bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ole.s", "S,T", 0x540001bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ole.s", "M,S,T", 0x540001bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ole.ps", "S,T", 0x540009bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ole.ps", "M,S,T", 0x540009bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ule.d", "S,T", 0x540005fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ule.d", "M,S,T", 0x540005fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ule.s", "S,T", 0x540001fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ule.s", "M,S,T", 0x540001fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ule.ps", "S,T", 0x540009fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ule.ps", "M,S,T", 0x540009fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.sf.d", "S,T", 0x5400063c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.sf.d", "M,S,T", 0x5400063c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.sf.s", "S,T", 0x5400023c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.sf.s", "M,S,T", 0x5400023c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.sf.ps", "S,T", 0x54000a3c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.sf.ps", "M,S,T", 0x54000a3c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngle.d", "S,T", 0x5400067c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngle.d", "M,S,T", 0x5400067c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngle.s", "S,T", 0x5400027c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngle.s", "M,S,T", 0x5400027c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngle.ps", "S,T", 0x54000a7c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngle.ps", "M,S,T", 0x54000a7c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.seq.d", "S,T", 0x540006bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.seq.d", "M,S,T", 0x540006bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.seq.s", "S,T", 0x540002bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.seq.s", "M,S,T", 0x540002bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.seq.ps", "S,T", 0x54000abc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.seq.ps", "M,S,T", 0x54000abc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngl.d", "S,T", 0x540006fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngl.d", "M,S,T", 0x540006fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngl.s", "S,T", 0x540002fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngl.s", "M,S,T", 0x540002fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngl.ps", "S,T", 0x54000afc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngl.ps", "M,S,T", 0x54000afc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.lt.d", "S,T", 0x5400073c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.lt.d", "M,S,T", 0x5400073c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.lt.s", "S,T", 0x5400033c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.lt.s", "M,S,T", 0x5400033c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.lt.ps", "S,T", 0x54000b3c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.lt.ps", "M,S,T", 0x54000b3c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.nge.d", "S,T", 0x5400077c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.nge.d", "M,S,T", 0x5400077c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.nge.s", "S,T", 0x5400037c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.nge.s", "M,S,T", 0x5400037c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.nge.ps", "S,T", 0x54000b7c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.nge.ps", "M,S,T", 0x54000b7c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.le.d", "S,T", 0x540007bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.le.d", "M,S,T", 0x540007bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.le.s", "S,T", 0x540003bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.le.s", "M,S,T", 0x540003bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.le.ps", "S,T", 0x54000bbc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.le.ps", "M,S,T", 0x54000bbc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngt.d", "S,T", 0x540007fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngt.d", "M,S,T", 0x540007fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngt.s", "S,T", 0x540003fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngt.s", "M,S,T", 0x540003fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngt.ps", "S,T", 0x54000bfc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngt.ps", "M,S,T", 0x54000bfc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"cache", "k,~(b)", 0x20006000, 0xfc00f000, RD_b, 0, I1 },
+{"cache", "k,o(b)", 0, (int) M_CACHE_OB, INSN_MACRO, 0, I1 },
+{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I1 },
+{"ceil.l.d", "T,S", 0x5400533b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"ceil.w.d", "T,S", 0x54005b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"ceil.w.s", "T,S", 0x54001b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"cfc1", "t,G", 0x5400103b, 0xfc00ffff, WR_t|RD_C1|FP_S, 0, I1 },
+{"cfc1", "t,S", 0x5400103b, 0xfc00ffff, WR_t|RD_C1|FP_S, 0, I1 },
+{"cfc2", "t,G", 0x0000cd3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
+{"clo", "t,s", 0x00004b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
+{"clz", "t,s", 0x00005b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
+{"cop2", "C", 0x00000002, 0xfc000007, CP, 0, I1 },
+{"ctc1", "t,G", 0x5400183b, 0xfc00ffff, RD_t|WR_CC|FP_S, 0, I1 },
+{"ctc1", "t,S", 0x5400183b, 0xfc00ffff, RD_t|WR_CC|FP_S, 0, I1 },
+{"ctc2", "t,G", 0x0000dd3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
+{"cvt.d.l", "T,S", 0x5400537b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"cvt.d.s", "T,S", 0x5400137b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.d.w", "T,S", 0x5400337b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.l.d", "T,S", 0x5400413b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"cvt.l.s", "T,S", 0x5400013b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.s.l", "T,S", 0x54005b7b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.s.d", "T,S", 0x54001b7b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.s.w", "T,S", 0x54003b7b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"cvt.s.pl", "T,S", 0x5400213b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.s.pu", "T,S", 0x5400293b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.w.d", "T,S", 0x5400493b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.w.s", "T,S", 0x5400093b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"cvt.ps.s", "D,V,T", 0x54000180, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I1 },
+{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
+{"dadd", "d,v,t", 0x58000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
+{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
+{"daddi", "t,r,.", 0x5800001c, 0xfc00003f, WR_t|RD_s, 0, I3 },
+{"daddi", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
+{"daddiu", "t,r,j", 0x5c000000, 0xfc000000, WR_t|RD_s, 0, I3 },
+{"daddu", "d,v,t", 0x58000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
+{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
+{"dclo", "t,s", 0x58004b3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
+{"dclz", "t,s", 0x58005b3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
+{"deret", "", 0x0000e37c, 0xffffffff, 0, 0, I1 },
+{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I3 },
+{"dext", "t,r,+A,+C",0x5800002c, 0xfc00003f, WR_t|RD_s, 0, I3 },
+{"dextm", "t,r,+A,+G",0x58000024, 0xfc00003f, WR_t|RD_s, 0, I3 },
+{"dextu", "t,r,+E,+H",0x58000014, 0xfc00003f, WR_t|RD_s, 0, I3 },
+/* For ddiv, see the comments about div. */
+{"ddiv", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"ddiv", "z,t", 0x5800ab3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 },
+{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 },
+/* For ddivu, see the comments about div. */
+{"ddivu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"ddivu", "z,t", 0x5800bb3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
+{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
+{"di", "", 0x0000477c, 0xffffffff, RD_C0, WR_s, I1 },
+{"di", "s", 0x0000477c, 0xffe0ffff, RD_C0, WR_s, I1 },
+{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I3 },
+{"dins", "t,r,+A,+B",0x5800000c, 0xfc00003f, WR_t|RD_s, 0, I3 },
+{"dinsm", "t,r,+A,+F",0x58000004, 0xfc00003f, WR_t|RD_s, 0, I3 },
+{"dinsu", "t,r,+E,+F",0x58000034, 0xfc00003f, WR_t|RD_s, 0, I3 },
+/* The MIPS assembler treats the div opcode with two operands as
+ though the first operand appeared twice (the first operand is both
+ a source and a destination). To get the div machine instruction,
+ you must use an explicit destination of $0. */
+{"div", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"div", "z,t", 0x0000ab3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
+{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 },
+{"div.d", "D,V,T", 0x540001f0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"div.s", "D,V,T", 0x540000f0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+/* For divu, see the comments about div. */
+{"divu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"divu", "z,t", 0x0000bb3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
+{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 },
+{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 },
+{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 },
+{"dli", "t,j", 0x30000000, 0xfc1f0000, WR_t, 0, I3 }, /* addiu */
+{"dli", "t,i", 0x50000000, 0xfc1f0000, WR_t, 0, I3 }, /* ori */
+{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 },
+{"dmfc0", "t,G", 0x580000fc, 0xfc00ffff, WR_t|RD_C0, 0, I3 },
+{"dmfc0", "t,+D", 0x580000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I3 },
+{"dmfc0", "t,G,H", 0x580000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I3 },
+{"dmtc0", "t,G", 0x580002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I3 },
+{"dmtc0", "t,+D", 0x580002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I3 },
+{"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I3 },
+{"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I3 },
+{"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I3 },
+{"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I3 },
+{"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I3 },
+{"dmfc2", "t,G", 0x00006d3c, 0xfc00ffff, WR_t|RD_C2, 0, I3 },
+/*{"dmfc2", "t,G,H", 0x58000283, 0xfc001fff, WR_t|RD_C2, 0, I3 },*/
+{"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I3 },
+/*{"dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_t|WR_C2|WR_CC, 0, I3 },*/
+{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
+{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 },
+{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 },
+{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 },
+{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 },
+{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 },
+{"dmult", "s,t", 0x58008b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"dmultu", "s,t", 0x58009b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"dneg", "d,w", 0x58000190, 0xfc1f07ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */
+{"dnegu", "d,w", 0x580001d0, 0xfc1f07ff, WR_d|RD_t, 0, I3 }, /* dsubu 0 */
+{"drem", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3 },
+{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3 },
+{"dremu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
+{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
+{"dror", "t,r,<", 0x580000c0, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"drorv", "d,t,s", 0x580000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I3 },
+{"dror32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
+{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
+{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
+{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
+{"drotrv", "d,t,s", 0x580000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I3 },
+{"drotr32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsbh", "t,r", 0x58007b3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
+{"dshd", "t,r", 0x5800fb3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
+{"dsllv", "d,t,s", 0x58000010, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
+{"dsll32", "t,r,<", 0x58000008, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsll", "d,t,s", 0x58000010, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */
+{"dsll", "t,r,>", 0x58000008, 0xfc0007ff, WR_t|RD_s, 0, I3 }, /* dsll32 */
+{"dsll", "t,r,<", 0x58000000, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsrav", "d,t,s", 0x58000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
+{"dsra32", "t,r,<", 0x58000088, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsra", "d,t,s", 0x58000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */
+{"dsra", "t,r,>", 0x58000088, 0xfc0007ff, WR_t|RD_s, 0, I3 }, /* dsra32 */
+{"dsra", "t,r,<", 0x58000080, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsrlv", "d,t,s", 0x58000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
+{"dsrl32", "t,r,<", 0x58000048, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsrl", "d,t,s", 0x58000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */
+{"dsrl", "t,r,>", 0x58000048, 0xfc0007ff, WR_t|RD_s, 0, I3 }, /* dsrl32 */
+{"dsrl", "t,r,<", 0x58000040, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsub", "d,v,t", 0x58000190, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
+{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
+{"dsubu", "d,v,t", 0x580001d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
+{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
+{"ei", "", 0x0000577c, 0xffffffff, WR_C0, WR_s, I1 },
+{"ei", "s", 0x0000577c, 0xffe0ffff, WR_C0, WR_s, I1 },
+{"eret", "", 0x0000f37c, 0xffffffff, 0, 0, I1 },
+{"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_t|RD_s, 0, I1 },
+{"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"floor.w.s", "T,V", 0x54000b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_t|RD_s, 0, I1 },
+{"jr", "mj", 0x4580, 0xffe0, UBD, MOD_mj, I1 },
+{"jr", "s", 0x00000f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jalr */
+{"jrs", "s", 0x00004f3c, 0xffe0ffff, UBD|RD_s, BD16, I1 }, /* jalrs */
+{"jraddiusp", "mP", 0x4700, 0xffe0, TRAP, UBR|RD_31|MOD_sp, I1 },
+{"jrc", "mj", 0x45a0, 0xffe0, TRAP, UBR|MOD_mj, I1 },
+{"jr.hb", "s", 0x00001f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jalr.hb */
+{"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, UBD|RD_s, BD16, I1 }, /* jalrs.hb */
+{"j", "mj", 0x4580, 0xffe0, UBD, MOD_mj, I1 }, /* jr */
+{"j", "s", 0x00000f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jr */
+/* SVR4 PIC code requires special handling for j, so it must be a
+ macro. */
+{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 },
+/* This form of j is used by the disassembler and internally by the
+ assembler, but will never match user input (because the line above
+ will match first). */
+{"j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1 },
+{"jalr", "mj", 0x45c0, 0xffe0, UBD|WR_31, MOD_mj|BD32, I1 },
+{"jalr", "my,mj", 0x45c0, 0xffe0, UBD|WR_31, MOD_mj|BD32, I1 },
+{"jalr", "s", 0x03e00f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD32, I1 },
+{"jalr", "t,s", 0x00000f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD32, I1 },
+{"jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD32, I1 },
+{"jalr.hb", "t,s", 0x00001f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD32, I1 },
+{"jalrs", "mj", 0x45e0, 0xffe0, UBD|WR_31, MOD_mj|BD16, I1 },
+{"jalrs", "my,mj", 0x45e0, 0xffe0, UBD|WR_31, MOD_mj|BD16, I1 },
+{"jalrs", "s", 0x03e04f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD16, I1 },
+{"jalrs", "t,s", 0x00004f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD16, I1 },
+{"jalrs.hb", "s", 0x03e05f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD16, I1 },
+{"jalrs.hb", "t,s", 0x00005f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD16, I1 },
+/* SVR4 PIC code requires special handling for jal, so it must be a
+ macro. */
+{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 },
+{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 },
+{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 },
+/* This form of jal is used by the disassembler and internally by the
+ assembler, but will never match user input (because the line above
+ will match first). */
+{"jal", "a", 0xf4000000, 0xfc000000, UBD|WR_31, BD32, I1 },
+{"jals", "d,s", 0, (int) M_JALS_2, INSN_MACRO, 0, I1 },
+{"jals", "s", 0, (int) M_JALS_1, INSN_MACRO, 0, I1 },
+{"jals", "a", 0, (int) M_JALS_A, INSN_MACRO, 0, I1 },
+{"jals", "a", 0x74000000, 0xfc000000, UBD|WR_31, BD16, I1 },
+{"jalx", "a", 0xf0000000, 0xfc000000, UBD|WR_31, BD32, I1 },
+{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
+{"lb", "t,o(b)", 0x1c000000, 0xfc000000, RD_b|WR_t, 0, I1 },
+{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
+{"lbu", "md,mG(ml)", 0x0800, 0xfc00, 0, MOD_md|MOD_ml, I1 },
+{"lbu", "t,o(b)", 0x14000000, 0xfc000000, RD_b|WR_t, 0, I1 },
+{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
+{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
+/* The macro has to be first to handle o32 correctly. */
+{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
+{"ld", "t,o(b)", 0xdc000000, 0xfc000000, RD_b|WR_t, 0, I3 },
+{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
+{"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 },
+{"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 },
+{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_b|WR_CC, 0, I1 },
+{"ldc2", "E,o(b)", 0, (int) M_LDC2_OB, INSN_MACRO, 0, I1 },
+{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1 },
+{"l.d", "T,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 }, /* ldc1 */
+{"l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_t|RD_b, 0, I3 },
+{"ldl", "t,o(b)", 0, (int) M_LDL_OB, INSN_MACRO, 0, I3 },
+{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
+{"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_b, 0, I3 },
+{"ldm", "n,o(b)", 0, (int) M_LDM_OB, INSN_MACRO, 0, I3 },
+{"ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3 },
+{"ldp", "t,~(b)", 0x20004000, 0xfc00f000, RD_b|WR_t, 0, I3 },
+{"ldp", "t,o(b)", 0, (int) M_LDP_OB, INSN_MACRO, 0, I3 },
+{"ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3 },
+{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_t|RD_b, 0, I3 },
+{"ldr", "t,o(b)", 0, (int) M_LDR_OB, INSN_MACRO, 0, I3 },
+{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
+{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_D|RD_t|RD_b|FP_D, 0, I1 },
+{"lh", "t,o(b)", 0x3c000000, 0xfc000000, RD_b|WR_t, 0, I1 },
+{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 },
+{"lhu", "md,mH(ml)", 0x2800, 0xfc00, 0, MOD_md|MOD_ml, I1 },
+{"lhu", "t,o(b)", 0x34000000, 0xfc000000, RD_b|WR_t, 0, I1 },
+{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 },
+/* li is at the start of the table. */
+{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"ll", "t,~(b)", 0x60003000, 0xfc00f000, RD_b|WR_t, 0, I1 },
+{"ll", "t,o(b)", 0, (int) M_LL_OB, INSN_MACRO, 0, I1 },
+{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1 },
+{"lld", "t,~(b)", 0x60007000, 0xfc00f000, RD_b|WR_t, 0, I3 },
+{"lld", "t,o(b)", 0, (int) M_LLD_OB, INSN_MACRO, 0, I3 },
+{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
+{"lui", "s,u", 0x41a00000, 0xffe00000, 0, WR_s, I1 },
+{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_D|RD_t|RD_b|FP_D, 0, I1 },
+{"lw", "md,mJ(ml)", 0x6800, 0xfc00, 0, MOD_md|MOD_ml, I1 },
+{"lw", "mp,mU(ms)", 0x4800, 0xfc00, 0, MOD_mp|MOD_sp, I1 }, /* lwsp */
+{"lw", "md,mA(ma)", 0x6400, 0xfc00, 0, MOD_md|RD_gp, I1 }, /* lwgp */
+{"lw", "t,o(b)", 0xfc000000, 0xfc000000, RD_b|WR_t, 0, I1 },
+{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
+{"lwc1", "T,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 },
+{"lwc1", "E,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 },
+{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_b|WR_CC, 0, I1 },
+{"lwc2", "E,o(b)", 0, (int) M_LWC2_OB, INSN_MACRO, 0, I1 },
+{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
+{"l.s", "T,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
+{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, RD_b|WR_t, 0, I1 },
+{"lwl", "t,o(b)", 0, (int) M_LWL_OB, INSN_MACRO, 0, I1 },
+{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
+{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, RD_b|WR_t, 0, I1 }, /* same */
+{"lcache", "t,o(b)", 0, (int) M_LWL_OB, INSN_MACRO, 0, I1 },
+{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
+{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, TRAP, MOD_sp, I1 },
+{"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_b|TRAP, 0, I1 },
+{"lwm", "n,o(b)", 0, (int) M_LWM_OB, INSN_MACRO, 0, I1 },
+{"lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1 },
+{"lwp", "t,~(b)", 0x20001000, 0xfc00f000, RD_b|WR_t|TRAP, 0, I1 },
+{"lwp", "t,o(b)", 0, (int) M_LWP_OB, INSN_MACRO, 0, I1 },
+{"lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1 },
+{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, RD_b|WR_t, 0, I1 },
+{"lwr", "t,o(b)", 0, (int) M_LWR_OB, INSN_MACRO, 0, I1 },
+{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
+{"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, RD_b|WR_t, 0, I3 },
+{"lwu", "t,o(b)", 0, (int) M_LWU_OB, INSN_MACRO, 0, I3 },
+{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
+{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_D|RD_t|RD_b|FP_S, 0, I1 },
+{"flush", "t,~(b)", 0x60001000, 0xfc00f000, RD_b|WR_t, 0, I1 }, /* same */
+{"flush", "t,o(b)", 0, (int) M_LWR_OB, INSN_MACRO, 0, I1 },
+{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
+{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, RD_b|RD_t|WR_d, 0, I1 },
+{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
+{"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_t|RD_C0, 0, I1 },
+{"mfc0", "t,+D", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 },
+{"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 },
+{"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I1 },
+{"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I1 },
+{"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
+{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_t|RD_S|FP_D, 0, I1 },
+{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_t|RD_S|FP_D, 0, I1 },
+{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
+{"mfhi", "mj", 0x4600, 0xffe0, RD_HI, MOD_mj, I1 },
+{"mfhi", "s", 0x00000d7c, 0xffe0ffff, RD_HI, WR_s, I1 },
+{"mflo", "mj", 0x4640, 0xffe0, RD_LO, MOD_mj, I1 },
+{"mflo", "s", 0x00001d7c, 0xffe0ffff, RD_LO, WR_s, I1 },
+{"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"movep", "mh,mi,mm,mn", 0x8400, 0xfc01, TRAP, MOD_mhi|MOD_mm|MOD_mn, I1 },
+{"movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_t|RD_s|RD_CC|FP_S|FP_D, 0, I1 },
+{"movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
+{"movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_T|RD_S|RD_CC|FP_S, 0, I1 },
+{"movf.ps", "T,S,M", 0x54000420, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
+{"movn", "d,v,t", 0x00000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"movn.d", "D,S,t", 0x54000138, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
+{"movn.s", "D,S,t", 0x54000038, 0xfc0007ff, WR_D|RD_S|RD_t|FP_S, 0, I1 },
+{"movn.ps", "D,S,t", 0x54000238, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
+{"movt", "t,s,M", 0x5400097b, 0xfc001fff, WR_t|RD_s|RD_CC|FP_S|FP_D, 0, I1 },
+{"movt.d", "T,S,M", 0x54000260, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
+{"movt.s", "T,S,M", 0x54000060, 0xfc001fff, WR_T|RD_S|RD_CC|FP_S, 0, I1 },
+{"movt.ps", "T,S,M", 0x54000460, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
+{"movz", "d,v,t", 0x00000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"movz.d", "D,S,t", 0x54000178, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
+{"movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_D|RD_S|RD_t|FP_S, 0, I1 },
+{"movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
+{"msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
+{"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I1 },
+{"mtc0", "t,+D", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 },
+{"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 },
+{"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I1 },
+{"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I1 },
+{"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
+{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 },
+{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 },
+{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
+{"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_s|WR_HI, 0, I1 },
+{"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_s|WR_LO, 0, I1 },
+{"mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I1 },
+{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
+{"mul.d", "D,V,T", 0x540001b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"mul.s", "D,V,T", 0x540000b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+{"mul.ps", "D,V,T", 0x540002b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 },
+{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 },
+{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
+{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
+{"mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"neg", "d,w", 0x00000190, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
+{"negu", "d,w", 0x000001d0, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
+{"neg.d", "T,V", 0x54002b7b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"neg.s", "T,V", 0x54000b7b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"neg.ps", "T,V", 0x54004b7b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"nmadd.d", "D,R,S,T", 0x5400000a, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"nmadd.s", "D,R,S,T", 0x54000002, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
+{"nmadd.ps", "D,R,S,T", 0x54000012, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"nmsub.d", "D,R,S,T", 0x5400002a, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"nmsub.s", "D,R,S,T", 0x54000022, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
+{"nmsub.ps", "D,R,S,T", 0x54000032, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+/* nop is at the start of the table. */
+{"not", "mf,mg", 0x4400, 0xffc0, 0, MOD_mf|MOD_mg, I1 }, /* put not before nor */
+{"not", "d,v", 0x000002d0, 0xffe007ff, WR_d|RD_s|RD_t, 0, I1 }, /* nor d,s,0 */
+{"nor", "mf,mz,mg", 0x4400, 0xffc0, 0, MOD_mf|MOD_mg, I1 }, /* not */
+{"nor", "mf,mg,mz", 0x4400, 0xffc0, 0, MOD_mf|MOD_mg, I1 }, /* not */
+{"nor", "d,v,t", 0x000002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
+{"or", "mp,mj,mz", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"or", "mp,mz,mj", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"or", "mf,mt,mg", 0x44c0, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"or", "mf,mg,mx", 0x44c0, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"or", "d,v,t", 0x00000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
+{"ori", "mp,mj,mZ", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"ori", "t,r,i", 0x50000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"pll.ps", "D,V,T", 0x54000080, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"plu.ps", "D,V,T", 0x540000c0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"pul.ps", "D,V,T", 0x54000100, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"puu.ps", "D,V,T", 0x54000140, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+/* pref is at the start of the table. */
+{"recip.d", "T,S", 0x5400523b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"recip.s", "T,S", 0x5400123b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"rem", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
+{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 },
+{"remu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
+{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 },
+{"rdhwr", "t,K", 0x00006b3c, 0xfc00ffff, 0, WR_t, I1 },
+{"rdpgpr", "t,r", 0x0000e17c, 0xfc00ffff, WR_t, 0, I1 },
+{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
+{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
+{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
+{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
+{"ror", "t,r,<", 0x000000c0, 0xfc0007ff, WR_t|RD_s, 0, I1 },
+{"rorv", "d,t,s", 0x000000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I1 },
+{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
+{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
+{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
+{"rotr", "t,r,<", 0x000000c0, 0xfc0007ff, WR_t|RD_s, 0, I1 },
+{"rotrv", "d,t,s", 0x000000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I1 },
+{"round.l.d", "T,S", 0x5400733b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"round.l.s", "T,S", 0x5400333b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"round.w.d", "T,S", 0x54007b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"round.w.s", "T,S", 0x54003b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"rsqrt.d", "T,S", 0x5400423b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"rsqrt.s", "T,S", 0x5400023b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"sb", "mq,mL(ml)", 0x8800, 0xfc00, SM, MOD_mq|MOD_ml, I1 },
+{"sb", "t,o(b)", 0x18000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
+{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
+{"sc", "t,~(b)", 0x6000b000, 0xfc00f000, SM|RD_t|WR_t|RD_b, 0, I1 },
+{"sc", "t,o(b)", 0, (int) M_SC_OB, INSN_MACRO, 0, I1 },
+{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I1 },
+{"scd", "t,~(b)", 0x6000f000, 0xfc00f000, SM|RD_t|WR_t|RD_b, 0, I3 },
+{"scd", "t,o(b)", 0, (int) M_SCD_OB, INSN_MACRO, 0, I3 },
+{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
+/* The macro has to be first to handle o32 correctly. */
+{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
+{"sd", "t,o(b)", 0xd8000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
+{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
+{"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1 },
+{"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1 },
+{"sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1 },
+{"sdbbp", "B", 0x0000db7c, 0xfc00ffff, TRAP, 0, I1 },
+{"sdc1", "T,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 },
+{"sdc1", "E,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 },
+{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"sdc2", "E,~(b)", 0x2000a000, 0xfc00f000, SM|RD_C2|RD_b, 0, I1 },
+{"sdc2", "E,o(b)", 0, (int) M_SDC2_OB, INSN_MACRO, 0, I1 },
+{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I1 },
+{"s.d", "T,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 }, /* sdc1 */
+{"s.d", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"sdl", "t,~(b)", 0x6000c000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
+{"sdl", "t,o(b)", 0, (int) M_SDL_OB, INSN_MACRO, 0, I3 },
+{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
+{"sdm", "n,~(b)", 0x2000f000, 0xfc00f000, SM|RD_b, 0, I3 },
+{"sdm", "n,o(b)", 0, (int) M_SDM_OB, INSN_MACRO, 0, I3 },
+{"sdm", "n,A(b)", 0, (int) M_SDM_AB, INSN_MACRO, 0, I3 },
+{"sdp", "t,~(b)", 0x2000c000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
+{"sdp", "t,o(b)", 0, (int) M_SDP_OB, INSN_MACRO, 0, I3 },
+{"sdp", "t,A(b)", 0, (int) M_SDP_AB, INSN_MACRO, 0, I3 },
+{"sdr", "t,~(b)", 0x6000d000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
+{"sdr", "t,o(b)", 0, (int) M_SDR_OB, INSN_MACRO, 0, I3 },
+{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
+{"sdxc1", "D,t(b)", 0x54000108, 0xfc0007ff, SM|RD_t|RD_b|FP_D, RD_D, I1 },
+{"seb", "t,r", 0x00002b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
+{"seh", "t,r", 0x00003b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
+{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
+{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
+{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
+{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
+{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 },
+{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 },
+{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 },
+{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 },
+{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 },
+{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 },
+{"sh", "mq,mH(ml)", 0xa800, 0xfc00, SM, MOD_mq|MOD_ml, I1 },
+{"sh", "t,o(b)", 0x38000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
+{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 },
+{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
+{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
+{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
+{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
+{"sllv", "d,t,s", 0x00000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"sll", "md,mc,mM", 0x2400, 0xfc01, 0, MOD_md|MOD_mc, I1 },
+{"sll", "d,w,s", 0x00000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, /* sllv */
+{"sll", "t,r,<", 0x00000000, 0xfc0007ff, WR_t|RD_s, 0, I1 },
+{"slt", "d,v,t", 0x00000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
+{"slti", "t,r,j", 0x90000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"sltiu", "t,r,j", 0xb0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"sltu", "d,v,t", 0x00000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
+{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
+{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
+{"sqrt.d", "T,S", 0x54004a3b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"sqrt.s", "T,S", 0x54000a3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"srav", "d,t,s", 0x00000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
+{"sra", "d,w,s", 0x00000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
+{"sra", "t,r,<", 0x00000080, 0xfc0007ff, WR_t|RD_s, 0, I1 },
+{"srlv", "d,t,s", 0x00000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
+{"srl", "md,mc,mM", 0x2401, 0xfc01, 0, MOD_md|MOD_mc, I1 },
+{"srl", "d,w,s", 0x00000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
+{"srl", "t,r,<", 0x00000040, 0xfc0007ff, WR_t|RD_s, 0, I1 },
+/* ssnop is at the start of the table. */
+{"sub", "d,v,t", 0x00000190, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
+{"sub.d", "D,V,T", 0x54000170, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"sub.s", "D,V,T", 0x54000070, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+{"sub.ps", "D,V,T", 0x54000270, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"subu", "md,me,ml", 0x0401, 0xfc01, 0, MOD_md|MOD_me|MOD_ml, I1 },
+{"subu", "d,v,t", 0x000001d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
+{"suxc1", "D,t(b)", 0x54000188, 0xfc0007ff, SM|RD_t|RD_b|FP_D, RD_D, I1 },
+{"sw", "mq,mJ(ml)", 0xe800, 0xfc00, SM, MOD_mq|MOD_ml, I1 },
+{"sw", "mp,mU(ms)", 0xc800, 0xfc00, SM, MOD_mp|MOD_sp, I1 }, /* swsp */
+{"sw", "t,o(b)", 0xf8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
+{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
+{"swc1", "T,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
+{"swc1", "E,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
+{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"swc2", "E,~(b)", 0x20008000, 0xfc00f000, SM|RD_C2|RD_b, 0, I1 },
+{"swc2", "E,o(b)", 0, (int) M_SWC2_OB, INSN_MACRO, 0, I1 },
+{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
+{"s.s", "T,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
+{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"swl", "t,~(b)", 0x60008000, 0xfc00f000, SM|RD_t|RD_b, 0, I1 },
+{"swl", "t,o(b)", 0, (int) M_SWL_OB, INSN_MACRO, 0, I1 },
+{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
+{"scache", "t,~(b)", 0x60008000, 0xfc00f000, SM|RD_t|RD_b, 0, I1 }, /* same */
+{"scache", "t,o(b)", 0, (int) M_SWL_OB, INSN_MACRO, 0, I1 },
+{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
+{"swm", "mN,mJ(ms)", 0x4540, 0xffc0, TRAP, MOD_sp, I1 },
+{"swm", "n,~(b)", 0x2000d000, 0xfc00f000, SM|RD_b|TRAP, 0, I1 },
+{"swm", "n,o(b)", 0, (int) M_SWM_OB, INSN_MACRO, 0, I1 },
+{"swm", "n,A(b)", 0, (int) M_SWM_AB, INSN_MACRO, 0, I1 },
+{"swp", "t,~(b)", 0x20009000, 0xfc00f000, SM|RD_t|RD_b|TRAP, 0, I1 },
+{"swp", "t,o(b)", 0, (int) M_SWP_OB, INSN_MACRO, 0, I1 },
+{"swp", "t,A(b)", 0, (int) M_SWP_AB, INSN_MACRO, 0, I1 },
+{"swr", "t,~(b)", 0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 },
+{"swr", "t,o(b)", 0, (int) M_SWR_OB, INSN_MACRO, 0, I1 },
+{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
+{"invalidate", "t,~(b)",0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 }, /* same */
+{"invalidate", "t,o(b)",0, (int) M_SWR_OB, INSN_MACRO, 0, I1 },
+{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
+{"swxc1", "D,t(b)", 0x54000048, 0xfc0007ff, SM|RD_t|RD_b|FP_S, RD_D, I1 },
+{"sync_acquire", "", 0x00116b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync_mb", "", 0x00106b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync_release", "", 0x00126b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync_rmb", "", 0x00136b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync_wmb", "", 0x00046b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync", "", 0x00006b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync", "1", 0x00006b7c, 0xffe0ffff, INSN_SYNC, 0, I1 },
+{"synci", "o(b)", 0x42000000, 0xffe00000, SM|RD_b, 0, I1 },
+{"syscall", "", 0x00008b7c, 0xffffffff, TRAP, 0, I1 },
+{"syscall", "B", 0x00008b7c, 0xfc00ffff, TRAP, 0, I1 },
+{"teqi", "s,j", 0x41c00000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"teq", "s,t", 0x0000003c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"teq", "s,t,|", 0x0000003c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"teq", "s,j", 0x41c00000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* teqi */
+{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I1 },
+{"tgei", "s,j", 0x41200000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"tge", "s,t", 0x0000023c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"tge", "s,t,|", 0x0000023c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"tge", "s,j", 0x41200000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tgei */
+{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I1 },
+{"tgeiu", "s,j", 0x41600000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"tgeu", "s,t", 0x0000043c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"tgeu", "s,t,|", 0x0000043c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"tgeu", "s,j", 0x41600000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tgeiu */
+{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I1 },
+{"tlbp", "", 0x0000037c, 0xffffffff, INSN_TLB, 0, I1 },
+{"tlbr", "", 0x0000137c, 0xffffffff, INSN_TLB, 0, I1 },
+{"tlbwi", "", 0x0000237c, 0xffffffff, INSN_TLB, 0, I1 },
+{"tlbwr", "", 0x0000337c, 0xffffffff, INSN_TLB, 0, I1 },
+{"tlti", "s,j", 0x41000000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"tlt", "s,t", 0x0000083c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"tlt", "s,t,|", 0x0000083c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"tlt", "s,j", 0x41000000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tlti */
+{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I1 },
+{"tltiu", "s,j", 0x41400000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"tltu", "s,t", 0x00000a3c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"tltu", "s,t,|", 0x00000a3c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"tltu", "s,j", 0x41400000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tltiu */
+{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I1 },
+{"tnei", "s,j", 0x41800000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"tne", "s,t", 0x00000c3c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"tne", "s,t,|", 0x00000c3c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"tne", "s,j", 0x41800000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tnei */
+{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I1 },
+{"trunc.l.d", "T,S", 0x5400633b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"trunc.l.s", "T,S", 0x5400233b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"trunc.w.d", "T,S", 0x54006b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"trunc.w.s", "T,S", 0x54002b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
+{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
+{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
+{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
+{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
+{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
+{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
+{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
+{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I1 },
+{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I1 },
+{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
+{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
+{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
+{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
+{"wait", "", 0x0000937c, 0xffffffff, TRAP, 0, I1 },
+{"wait", "B", 0x0000937c, 0xfc00ffff, TRAP, 0, I1 },
+{"wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_s, 0, I1 },
+{"wsbh", "t,r", 0x00007b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
+{"xor", "mf,mt,mg", 0x4440, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"xor", "mf,mg,mx", 0x4440, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
+{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+};
+
+const int bfd_micromips_num_opcodes =
+ ((sizeof micromips_opcodes) / (sizeof (micromips_opcodes[0])));
16, 17, 2, 3, 4, 5, 6, 7
};
+/* The microMIPS registers with type b. */
+#define micromips_to_32_reg_b_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type c. */
+#define micromips_to_32_reg_c_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type d. */
+#define micromips_to_32_reg_d_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type e. */
+#define micromips_to_32_reg_e_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type f. */
+#define micromips_to_32_reg_f_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type g. */
+#define micromips_to_32_reg_g_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type h. */
+static const unsigned int micromips_to_32_reg_h_map[] =
+{
+ 5, 5, 6, 4, 4, 4, 4, 4
+};
+
+/* The microMIPS registers with type i. */
+static const unsigned int micromips_to_32_reg_i_map[] =
+{
+ 6, 7, 7, 21, 22, 5, 6, 7
+};
+
+/* The microMIPS registers with type j: 32 registers. */
+
+/* The microMIPS registers with type l. */
+#define micromips_to_32_reg_l_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type m. */
+static const unsigned int micromips_to_32_reg_m_map[] =
+{
+ 0, 17, 2, 3, 16, 18, 19, 20
+};
+
+/* The microMIPS registers with type n. */
+#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
+
+/* The microMIPS registers with type p: 32 registers. */
+
+/* The microMIPS registers with type q. */
+static const unsigned int micromips_to_32_reg_q_map[] =
+{
+ 0, 17, 2, 3, 4, 5, 6, 7
+};
+
+/* reg type s is $29. */
+
+/* reg type t is the same as the last register. */
+
+/* reg type y is $31. */
+
+/* reg type z is $0. */
+
+/* micromips imm B type. */
+static const int micromips_imm_b_map[8] =
+{
+ 1, 4, 8, 12, 16, 20, 24, -1
+};
+
+/* micromips imm C type. */
+static const int micromips_imm_c_map[16] =
+{
+ 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
+};
+
+/* micromips imm D type: (-512..511)<<1. */
+/* micromips imm E type: (-64..63)<<1. */
+/* micromips imm F type: (0..63). */
+/* micromips imm G type: (-1..14). */
+/* micromips imm H type: (0..15)<<1. */
+/* micromips imm I type: (-1..126). */
+/* micromips imm J type: (0..15)<<2. */
+/* micromips imm L type: (0..15). */
+/* micromips imm M type: (1..8). */
+/* micromips imm W type: (0..63)<<2. */
+/* micromips imm X type: (-8..7). */
+/* micromips imm Y type: (-258..-3, 2..257)<<2. */
+
#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
values. */
static int mips_processor;
static int mips_isa;
+static int micromips_ase;
static const char * const *mips_gpr_names;
static const char * const *mips_fpr_names;
static const char * const *mips_cp0_names;
return 0;
}
+/* Check if the object has microMIPS ASE code. */
+
+static int
+is_micromips (Elf_Internal_Ehdr *header)
+{
+ if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0)
+ return 1;
+
+ return 0;
+}
+
static void
set_default_mips_dis_options (struct disassemble_info *info)
{
const struct mips_arch_choice *chosen_arch;
- /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
- and numeric FPR, CP0 register, and HWR names. */
+ /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code
+ is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR,
+ CP0 register, and HWR names. */
mips_isa = ISA_MIPS3;
- mips_processor = CPU_R3000;
+ mips_processor = CPU_R3000;
+ micromips_ase = 0;
mips_gpr_names = mips_gpr_names_oldabi;
mips_fpr_names = mips_fpr_names_numeric;
mips_cp0_names = mips_cp0_names_numeric;
mips_hwr_names = mips_hwr_names_numeric;
no_aliases = 0;
- /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
+ /* Update settings according to the ELF file header flags. */
if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
{
Elf_Internal_Ehdr *header;
header = elf_elfheader (info->section->owner);
+ /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
if (is_newabi (header))
mips_gpr_names = mips_gpr_names_newabi;
+ /* If a microMIPS binary, then don't use MIPS16 bindings. */
+ micromips_ase = is_micromips (header);
}
/* Set ISA, architecture, and cp0 register names as best we can. */
return length;
}
+/* Disassemble microMIPS instructions. */
+
+static int
+print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
+{
+ const fprintf_ftype iprintf = info->fprintf_func;
+ const struct mips_opcode *op, *opend;
+ unsigned int lsb, msbd, msb;
+ void *is = info->stream;
+ unsigned int regno;
+ bfd_byte buffer[2];
+ int lastregno = 0;
+ int higher;
+ int length;
+ int status;
+ int delta;
+ int immed;
+ int insn;
+
+ lsb = 0;
+
+ info->bytes_per_chunk = 2;
+ info->display_endian = info->endian;
+ info->insn_info_valid = 1;
+ info->branch_delay_insns = 0;
+ info->data_size = 0;
+ info->insn_type = dis_nonbranch;
+ info->target = 0;
+ info->target2 = 0;
+
+ status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, memaddr, info);
+ return -1;
+ }
+
+ length = 2;
+
+ if (info->endian == BFD_ENDIAN_BIG)
+ insn = bfd_getb16 (buffer);
+ else
+ insn = bfd_getl16 (buffer);
+
+ if ((insn & 0xfc00) == 0x7c00)
+ {
+ /* This is a 48-bit microMIPS instruction. */
+ higher = insn;
+
+ status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
+ if (status != 0)
+ {
+ iprintf (is, "micromips 0x%x", higher);
+ (*info->memory_error_func) (status, memaddr + 2, info);
+ return -1;
+ }
+ if (info->endian == BFD_ENDIAN_BIG)
+ insn = bfd_getb16 (buffer);
+ else
+ insn = bfd_getl16 (buffer);
+ higher = (higher << 16) | insn;
+
+ status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info);
+ if (status != 0)
+ {
+ iprintf (is, "micromips 0x%x", higher);
+ (*info->memory_error_func) (status, memaddr + 4, info);
+ return -1;
+ }
+ if (info->endian == BFD_ENDIAN_BIG)
+ insn = bfd_getb16 (buffer);
+ else
+ insn = bfd_getl16 (buffer);
+ iprintf (is, "0x%x%04x (48-bit insn)", higher, insn);
+
+ info->insn_type = dis_noninsn;
+ return 6;
+ }
+ else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
+ {
+ /* This is a 32-bit microMIPS instruction. */
+ higher = insn;
+
+ status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
+ if (status != 0)
+ {
+ iprintf (is, "micromips 0x%x", higher);
+ (*info->memory_error_func) (status, memaddr + 2, info);
+ return -1;
+ }
+
+ if (info->endian == BFD_ENDIAN_BIG)
+ insn = bfd_getb16 (buffer);
+ else
+ insn = bfd_getl16 (buffer);
+
+ insn = insn | (higher << 16);
+
+ length += 2;
+ }
+
+ /* FIXME: Should probably use a hash table on the major opcode here. */
+
+#define GET_OP(insn, field) \
+ (((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field)
+ opend = micromips_opcodes + bfd_micromips_num_opcodes;
+ for (op = micromips_opcodes; op < opend; op++)
+ {
+ if (op->pinfo != INSN_MACRO
+ && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
+ && (insn & op->mask) == op->match
+ && ((length == 2 && (op->mask & 0xffff0000) == 0)
+ || (length == 4 && (op->mask & 0xffff0000) != 0)))
+ {
+ const char *s;
+
+ iprintf (is, "%s", op->name);
+ if (op->args[0] != '\0')
+ iprintf (is, "\t");
+
+ for (s = op->args; *s != '\0'; s++)
+ {
+ switch (*s)
+ {
+ case ',':
+ case '(':
+ case ')':
+ iprintf (is, "%c", *s);
+ break;
+
+ case '.':
+ delta = GET_OP (insn, OFFSET10);
+ if (delta & 0x200)
+ delta |= ~0x3ff;
+ iprintf (is, "%d", delta);
+ break;
+
+ case '1':
+ iprintf (is, "0x%lx", GET_OP (insn, STYPE));
+ break;
+
+ case '<':
+ iprintf (is, "0x%lx", GET_OP (insn, SHAMT));
+ break;
+
+ case '|':
+ iprintf (is, "0x%lx", GET_OP (insn, TRAP));
+ break;
+
+ case '~':
+ delta = GET_OP (insn, OFFSET12);
+ if (delta & 0x800)
+ delta |= ~0x7ff;
+ iprintf (is, "%d", delta);
+ break;
+
+ case 'a':
+ if (strcmp (op->name, "jalx") == 0)
+ info->target = (((memaddr + 4) & ~(bfd_vma) 0x0fffffff)
+ | (GET_OP (insn, TARGET) << 2));
+ else
+ info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff)
+ | ((GET_OP (insn, TARGET)) << 1));
+ /* For gdb disassembler, force odd address on jalx. */
+ if (info->flavour == bfd_target_unknown_flavour
+ && strcmp (op->name, "jalx") == 0)
+ info->target |= 1;
+ (*info->print_address_func) (info->target, info);
+ break;
+
+ case 'b':
+ case 'r':
+ case 's':
+ case 'v':
+ iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS)]);
+ break;
+
+ case 'c':
+ iprintf (is, "0x%lx", GET_OP (insn, CODE));
+ break;
+
+ case 'd':
+ iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RD)]);
+ break;
+
+ case 'h':
+ iprintf (is, "0x%lx", GET_OP (insn, PREFX));
+ break;
+
+ case 'i':
+ case 'u':
+ iprintf (is, "0x%lx", GET_OP (insn, IMMEDIATE));
+ break;
+
+ case 'j': /* Same as i, but sign-extended. */
+ case 'o':
+ delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
+ iprintf (is, "%d", delta);
+ break;
+
+ case 'k':
+ iprintf (is, "0x%x", GET_OP (insn, CACHE));
+ break;
+
+ case 'n':
+ {
+ int s_reg_encode;
+
+ immed = GET_OP (insn, RT);
+ s_reg_encode = immed & 0xf;
+ if (s_reg_encode != 0)
+ {
+ if (s_reg_encode == 1)
+ iprintf (is, "%s", mips_gpr_names[16]);
+ else if (s_reg_encode < 9)
+ iprintf (is, "%s-%s",
+ mips_gpr_names[16],
+ mips_gpr_names[15 + s_reg_encode]);
+ else if (s_reg_encode == 9)
+ iprintf (is, "%s-%s,%s",
+ mips_gpr_names[16],
+ mips_gpr_names[23],
+ mips_gpr_names[30]);
+ else
+ iprintf (is, "UNKNOWN");
+ }
+
+ if (immed & 0x10) /* For ra. */
+ {
+ if (s_reg_encode == 0)
+ iprintf (is, "%s", mips_gpr_names[31]);
+ else
+ iprintf (is, ",%s", mips_gpr_names[31]);
+ }
+ break;
+ }
+
+ case 'p':
+ /* Sign-extend the displacement. */
+ delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
+ info->target = (delta << 1) + memaddr + length;
+ (*info->print_address_func) (info->target, info);
+ break;
+
+ case 'q':
+ iprintf (is, "0x%lx", GET_OP (insn, CODE2));
+ break;
+
+ case 't':
+ case 'w':
+ iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RT)]);
+ break;
+
+ case 'y':
+ iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS3)]);
+ break;
+
+ case 'z':
+ iprintf (is, "%s", mips_gpr_names[0]);
+ break;
+
+ case 'B':
+ iprintf (is, "0x%lx", GET_OP (insn, CODE10));
+ break;
+
+ case 'C':
+ iprintf (is, "0x%lx", GET_OP (insn, COPZ));
+ break;
+
+ case 'D':
+ iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FD)]);
+ break;
+
+ case 'E':
+ /* Coprocessor register for lwcN instructions, et al.
+
+ Note that there is no load/store cp0 instructions, and
+ that FPU (cp1) instructions disassemble this field using
+ 'T' format. Therefore, until we gain understanding of
+ cp2 register names, we can simply print the register
+ numbers. */
+ iprintf (is, "$%ld", GET_OP (insn, RT));
+ break;
+
+ case 'G':
+ /* Coprocessor register for mtcN instructions, et al. Note
+ that FPU (cp1) instructions disassemble this field using
+ 'S' format. Therefore, we only need to worry about cp0,
+ cp2, and cp3.
+ The microMIPS encoding does not have a coprocessor
+ identifier field as such, so we must work out the
+ coprocessor number by looking at the opcode. */
+ switch (insn
+ & ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
+ | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)))
+ {
+ case 0x000000fc: /* mfc0 */
+ case 0x000002fc: /* mtc0 */
+ case 0x580000fc: /* dmfc0 */
+ case 0x580002fc: /* dmtc0 */
+ iprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]);
+ break;
+ default:
+ iprintf (is, "$%ld", GET_OP (insn, RS));
+ break;
+ }
+ break;
+
+ case 'H':
+ iprintf (is, "%ld", GET_OP (insn, SEL));
+ break;
+
+ case 'K':
+ iprintf (is, "%s", mips_hwr_names[GET_OP (insn, RS)]);
+ break;
+
+ case 'M':
+ iprintf (is, "$fcc%ld", GET_OP (insn, CCC));
+ break;
+
+ case 'N':
+ iprintf (is,
+ (op->pinfo & (FP_D | FP_S)) != 0
+ ? "$fcc%ld" : "$cc%ld",
+ GET_OP (insn, BCC));
+ break;
+
+ case 'R':
+ iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FR)]);
+ break;
+
+ case 'S':
+ case 'V':
+ iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FS)]);
+ break;
+
+ case 'T':
+ iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FT)]);
+ break;
+
+ case '+':
+ /* Extension character; switch for second char. */
+ s++;
+ switch (*s)
+ {
+ case 'A':
+ lsb = GET_OP (insn, EXTLSB);
+ iprintf (is, "0x%x", lsb);
+ break;
+
+ case 'B':
+ msb = GET_OP (insn, INSMSB);
+ iprintf (is, "0x%x", msb - lsb + 1);
+ break;
+
+ case 'C':
+ case 'H':
+ msbd = GET_OP (insn, EXTMSBD);
+ iprintf (is, "0x%x", msbd + 1);
+ break;
+
+ case 'D':
+ {
+ const struct mips_cp0sel_name *n;
+ unsigned int cp0reg, sel;
+
+ cp0reg = GET_OP (insn, RS);
+ sel = GET_OP (insn, SEL);
+
+ /* CP0 register including 'sel' code for mtcN
+ (et al.), to be printed textually if known.
+ If not known, print both CP0 register name and
+ sel numerically since CP0 register with sel 0 may
+ have a name unrelated to register being printed. */
+ n = lookup_mips_cp0sel_name (mips_cp0sel_names,
+ mips_cp0sel_names_len,
+ cp0reg, sel);
+ if (n != NULL)
+ iprintf (is, "%s", n->name);
+ else
+ iprintf (is, "$%d,%d", cp0reg, sel);
+ break;
+ }
+
+ case 'E':
+ lsb = GET_OP (insn, EXTLSB) + 32;
+ iprintf (is, "0x%x", lsb);
+ break;
+
+ case 'F':
+ msb = GET_OP (insn, INSMSB) + 32;
+ iprintf (is, "0x%x", msb - lsb + 1);
+ break;
+
+ case 'G':
+ msbd = GET_OP (insn, EXTMSBD) + 32;
+ iprintf (is, "0x%x", msbd + 1);
+ break;
+
+ default:
+ /* xgettext:c-format */
+ iprintf (is,
+ _("# internal disassembler error, "
+ "unrecognized modifier (+%c)"),
+ *s);
+ abort ();
+ }
+ break;
+
+ case 'm':
+ /* Extension character; switch for second char. */
+ s++;
+ switch (*s)
+ {
+ case 'a': /* global pointer. */
+ iprintf (is, "%s", mips_gpr_names[28]);
+ break;
+
+ case 'b':
+ regno = micromips_to_32_reg_b_map[GET_OP (insn, MB)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'c':
+ regno = micromips_to_32_reg_c_map[GET_OP (insn, MC)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'd':
+ regno = micromips_to_32_reg_d_map[GET_OP (insn, MD)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'e':
+ regno = micromips_to_32_reg_e_map[GET_OP (insn, ME)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'f':
+ /* Save lastregno for "mt" to print out later. */
+ lastregno = micromips_to_32_reg_f_map[GET_OP (insn, MF)];
+ iprintf (is, "%s", mips_gpr_names[lastregno]);
+ break;
+
+ case 'g':
+ regno = micromips_to_32_reg_g_map[GET_OP (insn, MG)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'h':
+ regno = micromips_to_32_reg_h_map[GET_OP (insn, MH)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'i':
+ regno = micromips_to_32_reg_i_map[GET_OP (insn, MI)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'j':
+ iprintf (is, "%s", mips_gpr_names[GET_OP (insn, MJ)]);
+ break;
+
+ case 'l':
+ regno = micromips_to_32_reg_l_map[GET_OP (insn, ML)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'm':
+ regno = micromips_to_32_reg_m_map[GET_OP (insn, MM)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'n':
+ regno = micromips_to_32_reg_n_map[GET_OP (insn, MN)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'p':
+ /* Save lastregno for "mt" to print out later. */
+ lastregno = GET_OP (insn, MP);
+ iprintf (is, "%s", mips_gpr_names[lastregno]);
+ break;
+
+ case 'q':
+ regno = micromips_to_32_reg_q_map[GET_OP (insn, MQ)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'r': /* program counter. */
+ iprintf (is, "$pc");
+ break;
+
+ case 's': /* stack pointer. */
+ lastregno = 29;
+ iprintf (is, "%s", mips_gpr_names[29]);
+ break;
+
+ case 't':
+ iprintf (is, "%s", mips_gpr_names[lastregno]);
+ break;
+
+ case 'z': /* $0. */
+ iprintf (is, "%s", mips_gpr_names[0]);
+ break;
+
+ case 'A':
+ /* Sign-extend the immediate. */
+ immed = ((GET_OP (insn, IMMA) ^ 0x40) - 0x40) << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'B':
+ immed = micromips_imm_b_map[GET_OP (insn, IMMB)];
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'C':
+ immed = micromips_imm_c_map[GET_OP (insn, IMMC)];
+ iprintf (is, "0x%lx", immed);
+ break;
+
+ case 'D':
+ /* Sign-extend the displacement. */
+ delta = (GET_OP (insn, IMMD) ^ 0x200) - 0x200;
+ info->target = (delta << 1) + memaddr + length;
+ (*info->print_address_func) (info->target, info);
+ break;
+
+ case 'E':
+ /* Sign-extend the displacement. */
+ delta = (GET_OP (insn, IMME) ^ 0x40) - 0x40;
+ info->target = (delta << 1) + memaddr + length;
+ (*info->print_address_func) (info->target, info);
+ break;
+
+ case 'F':
+ immed = GET_OP (insn, IMMF);
+ iprintf (is, "0x%x", immed);
+ break;
+
+ case 'G':
+ immed = (insn >> MICROMIPSOP_SH_IMMG) + 1;
+ immed = (immed & MICROMIPSOP_MASK_IMMG) - 1;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'H':
+ immed = GET_OP (insn, IMMH) << 1;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'I':
+ immed = (insn >> MICROMIPSOP_SH_IMMI) + 1;
+ immed = (immed & MICROMIPSOP_MASK_IMMI) - 1;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'J':
+ immed = GET_OP (insn, IMMJ) << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'L':
+ immed = GET_OP (insn, IMML);
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'M':
+ immed = (insn >> MICROMIPSOP_SH_IMMM) - 1;
+ immed = (immed & MICROMIPSOP_MASK_IMMM) + 1;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'N':
+ immed = GET_OP (insn, IMMN);
+ if (immed == 0)
+ iprintf (is, "%s,%s",
+ mips_gpr_names[16],
+ mips_gpr_names[31]);
+ else
+ iprintf (is, "%s-%s,%s",
+ mips_gpr_names[16],
+ mips_gpr_names[16 + immed],
+ mips_gpr_names[31]);
+ break;
+
+ case 'O':
+ immed = GET_OP (insn, IMMO);
+ iprintf (is, "0x%x", immed);
+ break;
+
+ case 'P':
+ immed = GET_OP (insn, IMMP) << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'Q':
+ /* Sign-extend the immediate. */
+ immed = (GET_OP (insn, IMMQ) ^ 0x400000) - 0x400000;
+ immed <<= 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'U':
+ immed = GET_OP (insn, IMMU) << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'W':
+ immed = GET_OP (insn, IMMW) << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'X':
+ /* Sign-extend the immediate. */
+ immed = (GET_OP (insn, IMMX) ^ 0x8) - 0x8;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'Y':
+ /* Sign-extend the immediate. */
+ immed = (GET_OP (insn, IMMY) ^ 0x100) - 0x100;
+ if (immed >= -2 && immed <= 1)
+ immed ^= 0x100;
+ immed = immed << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ default:
+ /* xgettext:c-format */
+ iprintf (is,
+ _("# internal disassembler error, "
+ "unrecognized modifier (m%c)"),
+ *s);
+ abort ();
+ }
+ break;
+
+ default:
+ /* xgettext:c-format */
+ iprintf (is,
+ _("# internal disassembler error, "
+ "unrecognized modifier (%c)"),
+ *s);
+ abort ();
+ }
+ }
+
+ /* Figure out instruction type and branch delay information. */
+ if ((op->pinfo
+ & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0)
+ info->branch_delay_insns = 1;
+ if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
+ | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
+ {
+ if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_GPR_T)) != 0)
+ info->insn_type = dis_jsr;
+ else
+ info->insn_type = dis_branch;
+ }
+ else if (((op->pinfo & INSN_COND_BRANCH_DELAY)
+ | (op->pinfo2 & INSN2_COND_BRANCH)) != 0)
+ {
+ if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
+ info->insn_type = dis_condjsr;
+ else
+ info->insn_type = dis_condbranch;
+ }
+ else if ((op->pinfo
+ & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0)
+ info->insn_type = dis_dref;
+
+ return length;
+ }
+ }
+#undef GET_OP
+
+ iprintf (is, "0x%x", insn);
+ info->insn_type = dis_noninsn;
+
+ return length;
+}
+
+/* Return 1 if a symbol associated with the location being disassembled
+ indicates a compressed (MIPS16 or microMIPS) mode. We iterate over
+ all the symbols at the address being considered assuming if at least
+ one of them indicates code compression, then such code has been
+ genuinely produced here (other symbols could have been derived from
+ function symbols defined elsewhere or could define data). Otherwise,
+ return 0. */
+
+static bfd_boolean
+is_compressed_mode_p (struct disassemble_info *info)
+{
+ elf_symbol_type *symbol;
+ int pos;
+ int i;
+
+ for (i = 0; i < info->num_symbols; i++)
+ {
+ pos = info->symtab_pos + i;
+
+ if (bfd_asymbol_flavour (info->symtab[pos]) != bfd_target_elf_flavour)
+ continue;
+
+ symbol = (elf_symbol_type *) info->symtab[pos];
+ if ((!micromips_ase
+ && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
+ || (micromips_ase
+ && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
+ return 1;
+ }
+
+ return 0;
+}
+
/* In an environment where we do not know the symbol type of the
instruction we are forced to assume that the low order bit of the
instructions' address may mark it as a mips16 instruction. If we
struct disassemble_info *info,
enum bfd_endian endianness)
{
+ int (*print_insn_compr) (bfd_vma, struct disassemble_info *);
bfd_byte buffer[INSNLEN];
int status;
set_default_mips_dis_options (info);
parse_mips_dis_options (info->disassembler_options);
+ if (info->mach == bfd_mach_mips16)
+ return print_insn_mips16 (memaddr, info);
+ if (info->mach == bfd_mach_mips_micromips)
+ return print_insn_micromips (memaddr, info);
+
+ print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips;
+
#if 1
- /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
+ /* FIXME: If odd address, this is CLEARLY a compressed instruction. */
/* Only a few tools will work this way. */
if (memaddr & 0x01)
- return print_insn_mips16 (memaddr, info);
+ return print_insn_compr (memaddr, info);
#endif
#if SYMTAB_AVAILABLE
- if (info->mach == bfd_mach_mips16
- || (info->symbols != NULL
- && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
- && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
- ->internal_elf_sym.st_other)))
- return print_insn_mips16 (memaddr, info);
+ if (is_compressed_mode_p (info))
+ return print_insn_compr (memaddr, info);
#endif
status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
projects / binutils-gdb.git / commitdiff