i386.c (ix86_decompose_address): Use simplify_gen_subreg to generate SImode equivalen...

	* config/i386/i386.c (ix86_decompose_address): Use simplify_gen_subreg
	to generate SImode equivalent of address, zero-extended with AND RTX.
	* config/i386/i386.md (ashift to lea splitter): Split to SImode mult.
	(simple lea to add/shift peephole2s): Remove peephole2s that operate
	on subregs of DImode operations.

From-SVN: r192908

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 107d6f6f651a50e870b0aeb1c8ce6e9cc0804ee9..54b596b1f86db8270af3b1085ff8331f603eee67 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,10 +1,17 @@
+2012-10-29  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.c (ix86_decompose_address): Use simplify_gen_subreg
+       to generate SImode equivalent of address, zero-extended with AND RTX.
+       * config/i386/i386.md (ashift to lea splitter): Split to SImode mult.
+       (simple lea to add/shift peephole2s): Remove peephole2s that operate
+       on subregs of DImode operations.
+
 2012-10-28  Vladimir Makarov  <vmakarov@redhat.com>
 
        PR rtl-optimization/55106
        * lra-constraints.c (skip_usage_debug_insns): New function.
        (check_secondary_memory_needed_p): Ditto.
-       (inherit_reload_reg): Use the new functions.  Improve debug
-       output.
+       (inherit_reload_reg): Use the new functions.  Improve debug output.
 
 2012-10-29  Jonathan Wakely  <jwakely.gcc@gmail.com>
 
@@ -47,7 +54,8 @@
 
        * ipa-inline.c (edge_badness): Reduce precision; use scc hints.
        (inline_small_functions): Fix dumps; update all callees after inlining.
-       * ipa-inline.h (INLINE_HINT_in_scc, INLINE_HINT_same_scc): New constants.
+       * ipa-inline.h (INLINE_HINT_in_scc, INLINE_HINT_same_scc): New
+       constants.
        (inline summary): Add SCC_NO.
        * ipa-inline-analysis.c (dump_inline_hints): Dump SCC hints.
        (reset_inline_summary): Reset scc_no.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index b575dc20aae1084f876e8963b364d523620980eb..2931e62bed9e8ae5b64f6f0d7e5a16887bcb850b 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -11821,7 +11821,11 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
                return 0;
            }
          else if (GET_MODE (addr) == DImode)
-           addr = gen_rtx_SUBREG (SImode, addr, 0);
+           {
+             addr = simplify_gen_subreg (SImode, addr, DImode, 0);
+             if (addr == NULL_RTX)
+               return 0;
+           }
          else if (GET_MODE (addr) != VOIDmode)
            return 0;
        }

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index cdbf73123864d553a1372ad2ae4b44a27464f563..538120c8f2264e275ec42c2d9377a4f393ec1504 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -9600,10 +9600,10 @@
   "TARGET_64BIT && reload_completed
    && true_regnum (operands[0]) != true_regnum (operands[1])"
   [(set (match_dup 0)
-       (zero_extend:DI (subreg:SI (mult:DI (match_dup 1) (match_dup 2)) 0)))]
+       (zero_extend:DI (mult:SI (match_dup 1) (match_dup 2))))]
 {
-  operands[1] = gen_lowpart (DImode, operands[1]);
-  operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
 })
 
 ;; This pattern can't accept a variable shift count, since shifts by
@@ -17357,28 +17357,6 @@
   [(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1)))
              (clobber (reg:CC FLAGS_REG))])])
 
-(define_peephole2
-  [(set (match_operand:SI 0 "register_operand")
-       (subreg:SI (plus:DI (match_operand:DI 1 "register_operand")
-                           (match_operand:DI 2 "nonmemory_operand")) 0))]
-  "TARGET_64BIT && !TARGET_OPT_AGU
-   && REGNO (operands[0]) == REGNO (operands[1])
-   && peep2_regno_dead_p (0, FLAGS_REG)"
-  [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
-             (clobber (reg:CC FLAGS_REG))])]
-  "operands[2] = gen_lowpart (SImode, operands[2]);")
-
-(define_peephole2
-  [(set (match_operand:SI 0 "register_operand")
-       (subreg:SI (plus:DI (match_operand:DI 1 "nonmemory_operand")
-                           (match_operand:DI 2 "register_operand")) 0))]
-  "TARGET_64BIT && !TARGET_OPT_AGU
-   && REGNO (operands[0]) == REGNO (operands[2])
-   && peep2_regno_dead_p (0, FLAGS_REG)"
-  [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
-             (clobber (reg:CC FLAGS_REG))])]
-  "operands[1] = gen_lowpart (SImode, operands[1]);")
-
 (define_peephole2
   [(set (match_operand:DI 0 "register_operand")
        (zero_extend:DI
@@ -17403,36 +17381,6 @@
                   (zero_extend:DI (plus:SI (match_dup 2) (match_dup 1))))
              (clobber (reg:CC FLAGS_REG))])])
 
-(define_peephole2
-  [(set (match_operand:DI 0 "register_operand")
-       (zero_extend:DI
-         (subreg:SI (plus:DI (match_dup 0)
-                             (match_operand:DI 1 "nonmemory_operand")) 0)))]
-  "TARGET_64BIT && !TARGET_OPT_AGU
-   && peep2_regno_dead_p (0, FLAGS_REG)"
-  [(parallel [(set (match_dup 0)
-                  (zero_extend:DI (plus:SI (match_dup 2) (match_dup 1))))
-             (clobber (reg:CC FLAGS_REG))])]
-{
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_lowpart (SImode, operands[0]);
-})
-
-(define_peephole2
-  [(set (match_operand:DI 0 "register_operand")
-       (zero_extend:DI
-         (subreg:SI (plus:DI (match_operand:DI 1 "nonmemory_operand")
-                             (match_dup 0)) 0)))]
-  "TARGET_64BIT && !TARGET_OPT_AGU
-   && peep2_regno_dead_p (0, FLAGS_REG)"
-  [(parallel [(set (match_dup 0)
-                  (zero_extend:DI (plus:SI (match_dup 2) (match_dup 1))))
-             (clobber (reg:CC FLAGS_REG))])]
-{
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_lowpart (SImode, operands[0]);
-})
-
 (define_peephole2
   [(set (match_operand:SWI48 0 "register_operand")
        (mult:SWI48 (match_dup 0)
@@ -17443,18 +17391,6 @@
              (clobber (reg:CC FLAGS_REG))])]
   "operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
 
-(define_peephole2
-  [(set (match_operand:SI 0 "register_operand")
-       (subreg:SI (mult:DI (match_operand:DI 1 "register_operand")
-                           (match_operand:DI 2 "const_int_operand")) 0))]
-  "TARGET_64BIT
-   && exact_log2 (INTVAL (operands[2])) >= 0
-   && REGNO (operands[0]) == REGNO (operands[1])
-   && peep2_regno_dead_p (0, FLAGS_REG)"
-  [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
-             (clobber (reg:CC FLAGS_REG))])]
-  "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
-
 (define_peephole2
   [(set (match_operand:DI 0 "register_operand")
        (zero_extend:DI
@@ -17469,22 +17405,6 @@
              (clobber (reg:CC FLAGS_REG))])]
   "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
 
-(define_peephole2
-  [(set (match_operand:DI 0 "register_operand")
-       (zero_extend:DI
-         (subreg:SI (mult:DI (match_dup 0)
-                             (match_operand:DI 1 "const_int_operand")) 0)))]
-  "TARGET_64BIT
-   && exact_log2 (INTVAL (operands[2])) >= 0
-   && peep2_regno_dead_p (0, FLAGS_REG)"
-  [(parallel [(set (match_dup 0)
-                  (zero_extend:DI (ashift:SI (match_dup 2) (match_dup 1))))
-             (clobber (reg:CC FLAGS_REG))])]
-{
-  operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));
-  operands[2] = gen_lowpart (SImode, operands[0]);
-})
-
 ;; The ESP adjustments can be done by the push and pop instructions.  Resulting
 ;; code is shorter, since push is only 1 byte, while add imm, %esp is 3 bytes.
 ;; On many CPUs it is also faster, since special hardware to avoid esp