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diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 3aeb658592d47ee78b2633ff55113125c21898b5..9d8a484af567c35d60b48c503f504aabd4ae437b 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -1,6 +1,4 @@
-# OpenPOWER Foundation External RFC LS001
-
-Links
+# OPF ISA WG External RFC LS001 08Sep2022
 
 * <https://git.openpower.foundation/isa/PowerISA/issues/64>
 * <https://libre-soc.org/openpower/sv/>
@@ -20,13 +18,11 @@ This proposal is to extend the Power ISA with an Abstract RISC-Paradigm
 Vectorisation Concept that may be applied to **all and any** suitable
 Scalar instructions, present and future, in the Scalar Power ISA.
 The Vectorisation System is called "Simple-V" and the Prefix Format
-is called "SVP64".
-
-**Simple-V is not a Traditional Vector ISA and therefore does not add Vector opcodes of any kind**.
+is called "SVP64". **Simple-V is not a Traditional Vector ISA and therefore does not add Vector opcodes**.
 
-An ISA Concept similar to Simple-V was originally invented in 1994 by Peter Hsu
-(Architect of the MIPS R8000) but was dropped as MIPS did not have an
-Out-of-Order Microarchitecture on which to best exploit it.
+An ISA Concept similar to Simple-V was originally invented in 1994 by
+Peter Hsu (Architect of the MIPS R8000) but was dropped as MIPS did
+not have an Out-of-Order Microarchitecture on which to best exploit it.
 
 Simple-V is designed for Embedded Scenarios right the way through
 Audio/Visual DSPs to 3D GPUs and Supercomputing.  As it does **not**