mixxeo: use -2 speed grade

diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py
index cfd1d144cb6434e50f5eb33c6cf43f155cfd907e..52318d7f850d7245276e226893119208525a3ebe 100644 (file)
--- a/mibuild/platforms/mixxeo.py
+++ b/mibuild/platforms/mixxeo.py
@@ -144,7 +144,7 @@ _io = [
 
 class Platform(XilinxISEPlatform):
        def __init__(self):
-               XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-3", _io,
+               XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
                        lambda p: CRG_SE(p, "clk50", None))
                self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")