correct RS/RA/CR0 for rlwinm which is 2P-1S1D

diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py
index 48f88da9a5e8456dc4fc05167f418b250fb27dd5..17239ec97927321808b9dc7cf9e834013379fa23 100644 (file)
--- a/src/openpower/sv/sv_analysis.py
+++ b/src/openpower/sv/sv_analysis.py
@@ -478,6 +478,10 @@ def extra_classifier(insn_name, value, name, res, regs):
         if insn_name == 'mtspr':
             res['0'] = 'd:SPR'  # SPR: Rdest1_EXTRA3
             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
+        elif insn_name == 'rlwinm':
+            # weird one, RA is a dest but not in bits 6:10
+            res['0'] = 'd:RA;d:CR0'  # RA: Rdest1_EXTRA3
+            res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
         elif insn_name == 'mfspr':
             res['0'] = 'd:RS'  # RS: Rdest1_EXTRA3
             res['1'] = 's:SPR'  # SPR: Rsrc1_EXTRA3
@@ -656,6 +660,10 @@ def extra_classifier(insn_name, value, name, res, regs):
     else:
         raise NotImplementedError(insn_name)
 
+    #if insn_name.startswith("rlw"):
+    #    print("regs ", value, insn_name, regs, res)
+
+
 
 def process_csvs(format):
 
@@ -793,6 +801,9 @@ def process_csvs(format):
             condition = row[3]
             insn = insns[(insn_name, condition)]
 
+            #if insn_name == 'rlwinm':
+            #    print ("upd rlwinm", insn)
+
             # start constructing svp64 CSV row
             res = OrderedDict()
             res['insn'] = insn_name