sim/erc32: Corrected wrong CPU implementation and version ID in psr

diff --git a/sim/erc32/ChangeLog b/sim/erc32/ChangeLog
index 4a316bcde5d51b045839d0074b9413cdc3ba8399..3757e5b1858f6bb2e3a2973107cfb2b6b5ebd415 100644 (file)
--- a/sim/erc32/ChangeLog
+++ b/sim/erc32/ChangeLog
@@ -1,3 +1,7 @@
+2015-02-21  Jiri Gaisler  <jiri@gaisler.se>
+
+       * exec.c (init_regs): erc32 has vendor ID 1 and version ID 1 in %psr.
+
 2015-02-21  Jiri Gaisler  <jiri@gaisler.se>
 
        * func.c (print_insn_sparc_sis): Add helper function for disassembly.

diff --git a/sim/erc32/exec.c b/sim/erc32/exec.c
index dc86ba3b8a73cbc9c06461b0743224e3fc35becd..07f35861c4b6cf1a56888682415167bcc04c03a0 100644 (file)
--- a/sim/erc32/exec.c
+++ b/sim/erc32/exec.c
@@ -2011,7 +2011,7 @@ init_regs(sregs)
     sregs->npc = 4;
     sregs->trap = 0;
     sregs->psr &= 0x00f03fdf;
-    sregs->psr |= 0x080;       /* Set supervisor bit */
+    sregs->psr |= 0x11000080;  /* Set supervisor bit */
     sregs->breakpoint = 0;
     sregs->annul = 0;
     sregs->fpstate = FP_EXE_MODE;