i965: Implement ARB_stencil_texturing on Gen8+.

On earlier hardware, we had to implement math in the shader to translate
Y-tiled or untiled coordinates to W-tiled coordinates (which is what
BLORP does today in order to texture from stencil buffers).

On Broadwell, we can simply state that it's W-tiled in SURFACE_STATE,
and adjust the pitch.  This is much easier.

In the surface state code, I chose to handle the "should we sample depth
or stencil?" question separately from the setup for sampling from
stencil.  This should make it work with the BindRenderbufferTexImage
hook as well, and hopefully be reusable for GL_ARB_texture_stencil8
someday.

v2: Update docs/GL3.txt (caught by Matt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/docs/GL3.txt b/docs/GL3.txt
index f0e95c563e5c00eec271b361151aae48cd9dfdb2..432a056421bc5b4730b3a15519121e6bf9400725 100644 (file)
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -158,7 +158,7 @@ GL 4.3:
   GL_ARB_robust_buffer_access_behavior                 not started
   GL_ARB_shader_image_size                             not started
   GL_ARB_shader_storage_buffer_object                  not started
-  GL_ARB_stencil_texturing                             API exists, no drivers
+  GL_ARB_stencil_texturing                             DONE (i965/gen8+)
   GL_ARB_texture_buffer_range                          DONE (nv50, nvc0, i965, r600, radeonsi)
   GL_ARB_texture_query_levels                          DONE (i965)
   GL_ARB_texture_storage_multisample                   DONE (all drivers that support GL_ARB_texture_multisample)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 01d3cb614146f2fac491c958f5f88331cfe57af1..8a4879ba44704e7c1ed1630aa14bf042bc85c037 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -264,6 +264,7 @@
 #define GEN8_SURFACE_HALIGN_8                       (2 << 14)
 #define GEN8_SURFACE_HALIGN_16                      (3 << 14)
 #define GEN8_SURFACE_TILING_NONE                    (0 << 12)
+#define GEN8_SURFACE_TILING_W                       (1 << 12)
 #define GEN8_SURFACE_TILING_X                       (2 << 12)
 #define GEN8_SURFACE_TILING_Y                       (3 << 12)
 #define BRW_SURFACE_RC_READ_WRITE      (1 << 8)

diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 9acece592abec6869dfec3ea09fc51e267c3b98e..0c95e865956fec09a4c00a05956a20ae991d27a9 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -363,7 +363,7 @@ brw_format_for_mesa_format(mesa_format mesa_format)
       [MESA_FORMAT_Z24_UNORM_X8_UINT] = 0,
       [MESA_FORMAT_X8Z24_UNORM] = 0,
       [MESA_FORMAT_Z_UNORM32] = 0,
-      [MESA_FORMAT_S_UINT8] = 0,
+      [MESA_FORMAT_S_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 
       [MESA_FORMAT_BGR_SRGB8] = 0,
       [MESA_FORMAT_A8B8G8R8_SRGB] = 0,

diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 594e53122c6c91cafd9c8c9c9cd3ab8102824573..27af6ad5ec59be23538fa0136b81e2877c8451a1 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -139,6 +139,18 @@ gen8_update_texture_surface(struct gl_context *ctx,
       return;
    }
 
+   if (tObj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL)
+      mt = mt->stencil_mt;
+
+   unsigned tiling_mode, pitch;
+   if (mt->format == MESA_FORMAT_S_UINT8) {
+      tiling_mode = GEN8_SURFACE_TILING_W;
+      pitch = 2 * mt->region->pitch;
+   } else {
+      tiling_mode = surface_tiling_mode(mt->region->tiling);
+      pitch = mt->region->pitch;
+   }
+
    uint32_t tex_format = translate_tex_format(brw,
                                               mt->format,
                                               sampler->sRGBDecode);
@@ -150,7 +162,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
              tex_format << BRW_SURFACE_FORMAT_SHIFT |
              vertical_alignment(mt) |
              horizontal_alignment(mt) |
-             surface_tiling_mode(mt->region->tiling);
+             tiling_mode;
 
    if (tObj->Target == GL_TEXTURE_CUBE_MAP ||
        tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
@@ -165,8 +177,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 
-   surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
-             (mt->region->pitch - 1);
+   surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
 
    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index ef9aa555ec23d95f121229008e745e12e33d352b..5094c2b1aeddf6349d1c55c8c9a7a531143e1a31 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -303,6 +303,10 @@ intelInitExtensions(struct gl_context *ctx)
          ctx->Extensions.ARB_compute_shader = true;
    }
 
+   if (brw->gen >= 8) {
+      ctx->Extensions.ARB_stencil_texturing = true;
+   }
+
    if (brw->gen == 5 || can_write_oacontrol(brw))
       ctx->Extensions.AMD_performance_monitor = true;