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diff --git a/openpower/sv/predication.mdwn b/openpower/sv/predication.mdwn
index 23a06bb6a555f3427dbbfecf6177cd9c6d96be04..7bc116211ad36ecf4d5436946d15742d97e0dd2f 100644 (file)
--- a/openpower/sv/predication.mdwn
+++ b/openpower/sv/predication.mdwn
@@ -17,11 +17,13 @@
 * must cover up to 64 elements
 * must still work for elwidth over-rides
 
-# Capabilities
+## Additional Capabilities
 
 * two modes, "zeroing" and "non-zeroing". zeroing mode places a zero in the masked-out element results, where non-zeroing leaves the destination (result) element unmodified.
 * predicate must be invertable via an opcode bit (to avoid the need for an instruction which inverts all bits of the predicate mask)
 
+Implementation note: even in in-order microarchitectures it is strongly adviseable to use byte-level write-enable lines on the register file.  This in combination with 8b-bit SIMD element overrides allows, in "non-zeroing" mode, the predicate mask to be directly ANDed with the regfile write-enable lines to achieve the required functionality.  The alternative is to perform a READ-MODIFY-MASK-WRITE cycle which is costly and compromises performance.  Avoided very simply with byte-level write-enable.
+
 # Proposals
 
 ## Adding new predicate register types and associated opcodes