i965/wm: Set copy of sample mask in 3DSTATE_PS correctly for Haswell

The bspec says:

"SW must program the sample mask value in this field so that it matches
with 3DSTATE_SAMPLE_MASK"

I haven't observed this to actually fix anything, but stumbled across it
while adding the rest of the support for CMS layout for multisample
   textures.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 65c9bbf2ba1c80eb77aa705739b176a1da4db874..abbc73c21426bda6c7bdc36c5f7d0e5874562d39 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -173,8 +173,11 @@ upload_ps_state(struct brw_context *brw)
    if (ctx->Shader.CurrentFragmentProgram == NULL)
       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 
+   /* Haswell requires the sample mask to be set in this packet as well as
+    * in 3DSTATE_SAMPLE_MASK; the values should match. */
+   /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
    if (brw->is_haswell)
-      dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
+      dw4 |= SET_FIELD(gen6_determine_sample_mask(brw), HSW_PS_SAMPLE_MASK);
 
    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 
@@ -274,7 +277,9 @@ upload_ps_state(struct brw_context *brw)
 const struct brw_tracked_state gen7_ps_state = {
    .dirty = {
       .mesa  = (_NEW_PROGRAM_CONSTANTS |
-               _NEW_COLOR),
+               _NEW_COLOR |
+                _NEW_BUFFERS |
+                _NEW_MULTISAMPLE),
       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
                BRW_NEW_PS_BINDING_TABLE |
                BRW_NEW_BATCH |