litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet...

diff --git a/misoclib/com/litepcie/common.py b/misoclib/com/litepcie/common.py
index 4f16c7e68f318fe7246444bee444a0200dfd6ffb..81f75cb7b013e8499c434fcd8e6a9453d70ac283 100644 (file)
--- a/misoclib/com/litepcie/common.py
+++ b/misoclib/com/litepcie/common.py
@@ -63,5 +63,5 @@ def interrupt_layout():
 
 
 def dma_layout(dw):
-    layout = [("dat", dw)]
+    layout = [("data", dw)]
     return EndpointDescription(layout, packetized=True)

diff --git a/misoclib/com/litepcie/frontend/dma/reader.py b/misoclib/com/litepcie/frontend/dma/reader.py
index c2bbfe2f0821683de4c346c18b160c8d295d15cb..de39e5e8ae107a9b87f7d42f0ea5bd832baf53ff 100644 (file)
--- a/misoclib/com/litepcie/frontend/dma/reader.py
+++ b/misoclib/com/litepcie/frontend/dma/reader.py
@@ -70,7 +70,7 @@ class DMAReader(Module, AutoCSR):
         self.comb += [
             fifo.sink.stb.eq(port.sink.stb),
             fifo.sink.sop.eq(port.sink.sop & (port.sink.user_id != last_user_id)),
-            fifo.sink.dat.eq(port.sink.dat),
+            fifo.sink.data.eq(port.sink.dat),
             port.sink.ack.eq(fifo.sink.ack | ~enable),
         ]
         self.comb += Record.connect(fifo.source, self.source)

diff --git a/misoclib/com/litepcie/frontend/dma/writer.py b/misoclib/com/litepcie/frontend/dma/writer.py
index 0522398e4f1e0c6b152dd0846a924a1e6818c5db..2f6131d0eb2bbe807539289ed9d718189a71e1f9 100644 (file)
--- a/misoclib/com/litepcie/frontend/dma/writer.py
+++ b/misoclib/com/litepcie/frontend/dma/writer.py
@@ -28,7 +28,7 @@ class DMAWriter(Module, AutoCSR):
         self.comb += [
             fifo.we.eq(sink.stb & enable),
             sink.ack.eq(fifo.writable & sink.stb & enable),
-            fifo.din.eq(sink.dat),
+            fifo.din.eq(sink.data),
             fifo.reset.eq(~enable)
         ]