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Quick fix
author
Miodrag Milanovic
<mmicko@gmail.com>
Mon, 28 Feb 2022 10:40:06 +0000
(11:40 +0100)
committer
Miodrag Milanovic
<mmicko@gmail.com>
Mon, 28 Feb 2022 10:40:06 +0000
(11:40 +0100)
passes/sat/sim.cc
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diff --git
a/passes/sat/sim.cc
b/passes/sat/sim.cc
index 304dfef13b268d5fd06477af1e0851e7812c931a..1ce563ac28e62771b3864d536c5978801db730ab 100644
(file)
--- a/
passes/sat/sim.cc
+++ b/
passes/sat/sim.cc
@@
-1304,6
+1304,8
@@
struct SimWorker : SimShared
state = 3;
break;
default:
+ log("Simulating cycle %d.\n", cycle);
+ top->setState(inputs, line);
if (cycle) {
set_inports(clock, State::S1);
set_inports(clockn, State::S0);