Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions.

        bfd/
        * elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations.
        (ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15.
        (ppc_elf_vle_split16): Clear field before inserting.

        opcodes/
        * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
        'e_cmplwi' to 'e_cmpli' instead.
        (OPVUPRT, OPVUPRT_MASK): Define.
        (powerpc_opcodes): Add E200Z4 insns.
        (vle_opcodes): Add context save/restore insns.

        include/
        * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index b60d8d2b3998025d001aea2fb816bd1aa3ace806..72e928229c5a5a267ad1edb9708b4c72b79ea452 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,10 @@
+2016-08-01  Andrew Jenner  <andrew@codesourcery.com>
+       Kwok Cheung Yeung  <kcy@codesourcery.com>
+
+       * elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations.
+       (ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15.
+       (ppc_elf_vle_split16): Clear field before inserting.
+
 2016-08-01  Nick Clifton  <nickc@redhat.com>
 
        * po/sv.po: Updated Swedish translation.

diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index 81b3d84d822ccef8a2a2d1192cadab4288fd12a7..8d5131a31ef1d827d00f08991045961cf65806a3 100644 (file)
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -1425,7 +1425,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
         "R_PPC_VLE_REL15",     /* name */
         FALSE,                 /* partial_inplace */
         0,                     /* src_mask */
-        0xfe,                  /* dst_mask */
+        0xfffe,                /* dst_mask */
         TRUE),                 /* pcrel_offset */
 
   /* A relative 24 bit branch.  */
@@ -3948,7 +3948,8 @@ is_branch_reloc (enum elf_ppc_reloc_type r_type)
          || r_type == R_PPC_ADDR24
          || r_type == R_PPC_ADDR14
          || r_type == R_PPC_ADDR14_BRTAKEN
-         || r_type == R_PPC_ADDR14_BRNTAKEN);
+         || r_type == R_PPC_ADDR14_BRNTAKEN
+         || r_type == R_PPC_VLE_REL24);
 }
 
 static void
@@ -4899,6 +4900,7 @@ ppc_elf_vle_split16 (bfd *output_bfd, bfd_byte *loc,
   insn = bfd_get_32 (output_bfd, loc);
   top5 = value & 0xf800;
   top5 = top5 << (split16_format == split16a_type ? 9 : 5);
+  insn &= (split16_format == split16a_type ? ~0x1f007ff : ~0x1f07ff);
   insn |= top5;
   insn |= value & 0x7ff;
   bfd_put_32 (output_bfd, insn, loc);

diff --git a/include/ChangeLog b/include/ChangeLog
index a87c9b6048f075ee043dedc6a7c90dfc97e88eae..673f7571d0add4de32638b5d1658662a35a4815a 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2016-08-01  Andrew Jenner  <andrew@codesourcery.com>
+
+       * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
+
 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 
         * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,

diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 628a7a184bc4f2159e5ea164bf894b3bd5a0e38a..d9f973ddea89134c111d22c934f17cedfd1504cf 100644 (file)
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -214,6 +214,9 @@ extern const int vle_num_opcodes;
 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08.  */
 #define PPC_OPCODE_VSX3       0x40000000000ull
 
+  /* Opcode is supported by e200z4.  */
+#define PPC_OPCODE_E200Z4     0x80000000000ull
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 609058538fb9d0289115cdaeb52cde614ad0669b..0d3a4bb26453c9649b1de1c51f867af93fc92c15 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
+       Kwok Cheung Yeung  <kcy@codesourcery.com>
+
+       opcodes/
+       * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
+       'e_cmplwi' to 'e_cmpli' instead.
+       (OPVUPRT, OPVUPRT_MASK): Define.
+       (powerpc_opcodes): Add E200Z4 insns.
+       (vle_opcodes): Add context save/restore insns.
+
 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 
        * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",

diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 77a2a60643b68739af26b6ede405c01799aab44d..da1301e6aeaf5c148e70f8eab618a6754bc87d4a 100644 (file)
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -105,6 +105,11 @@ struct ppc_mopt ppc_opts[] = {
     0 },
   { "com",     PPC_OPCODE_COMMON,
     0 },
+  { "e200z4",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
+               | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
+               | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+               | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4),
+    PPC_OPCODE_VLE },
   { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
     0 },
   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 8106ab72216f1c52c7462396b5a9caf4b00381fe..d4fc7c0455c9ff91fecdd7f981f0aa767a2ad242 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2374,6 +2374,12 @@ extract_vleil (unsigned long insn,
 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
 #define OPVUP_MASK OPVUP (0x3f,  0xff)
 
+/* The main opcode combined with an update code and the RT fields specified in
+   D form instruction.  Used for VLE volatile context save/restore
+   instructions.  */
+#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
+#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
+
 /* An A form instruction.  */
 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
 #define A_MASK A (0x3f, 0x1f, 1)
@@ -3055,6 +3061,7 @@ extract_vleil (unsigned long insn,
 #define E6500  PPC_OPCODE_E6500
 #define PPCVLE  PPC_OPCODE_VLE
 #define PPCHTM  PPC_OPCODE_HTM
+#define E200Z4  PPC_OPCODE_E200Z4
 /* The list of embedded processors that use the embedded operand ordering
    for the 3 operand dcbt and dcbtst instructions.  */
 #define DCBT_EO        (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
@@ -5815,6 +5822,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mcrxr",      X(31,512),      XBFRARB_MASK, COM,      POWER7,         {BF}},
 
+{"lbdcbx",     X(31,514),      X_MASK,      E200Z4,    0,              {RT, RA, RB}},
 {"lbdx",       X(31,515),      X_MASK,      E500MC,    0,              {RT, RA, RB}},
 
 {"bblels",     X(31,518),      X_MASK,      PPCBRLK,   0,              {0}},
@@ -5865,6 +5873,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"maskir",     XRC(31,541,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
 {"maskir.",    XRC(31,541,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
+{"lhdcbx",     X(31,546),      X_MASK,      E200Z4,    0,              {RT, RA, RB}},
 {"lhdx",       X(31,547),      X_MASK,      E500MC,    0,              {RT, RA, RB}},
 
 {"lvtrx",      X(31,549),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
@@ -5888,6 +5897,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mcrxrx",     X(31,576),     XBFRARB_MASK, POWER9,    0,              {BF}},
 
+{"lwdcbx",     X(31,578),      X_MASK,      E200Z4,    0,              {RT, RA, RB}},
 {"lwdx",       X(31,579),      X_MASK,      E500MC,    0,              {RT, RA, RB}},
 
 {"lvtlx",      X(31,581),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
@@ -5938,6 +5948,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lfdux",      X(31,631),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
 
+{"stbdcbx",    X(31,642),      X_MASK,      E200Z4,    0,              {RS, RA, RB}},
 {"stbdx",      X(31,643),      X_MASK,      E500MC,    0,              {RS, RA, RB}},
 
 {"stvlx",      X(31,647),      X_MASK,      CELL,      0,              {VS, RA0, RB}},
@@ -5975,6 +5986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sre",                XRC(31,665,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
 {"sre.",       XRC(31,665,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
+{"sthdcbx",    X(31,674),      X_MASK,      E200Z4,    0,              {RS, RA, RB}},
 {"sthdx",      X(31,675),      X_MASK,      E500MC,    0,              {RS, RA, RB}},
 
 {"stvfrx",     X(31,677),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
@@ -5992,6 +6004,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sriq",       XRC(31,696,0),  X_MASK,      M601,      0,              {RA, RS, SH}},
 {"sriq.",      XRC(31,696,1),  X_MASK,      M601,      0,              {RA, RS, SH}},
 
+{"stwdcbx",    X(31,706),      X_MASK,      E200Z4,    0,              {RS, RA, RB}},
 {"stwdx",      X(31,707),      X_MASK,      E500MC,    0,              {RS, RA, RB}},
 
 {"stvflx",     X(31,709),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
@@ -7070,7 +7083,9 @@ const struct powerpc_opcode vle_opcodes[] = {
 {"se_cmphl",   SE_RR(3,3),     SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
 
 {"e_cmpi",     SCI8BF(6,0,21), SCI8BF_MASK,    PPCVLE, 0,              {CRD32, RA, SCLSCI8}},
+{"e_cmpwi",    SCI8BF(6,0,21), SCI8BF_MASK,    PPCVLE, 0,              {CRD32, RA, SCLSCI8}},
 {"e_cmpli",    SCI8BF(6,1,21), SCI8BF_MASK,    PPCVLE, 0,              {CRD32, RA, SCLSCI8}},
+{"e_cmplwi",   SCI8BF(6,1,21), SCI8BF_MASK,    PPCVLE, 0,              {CRD32, RA, SCLSCI8}},
 {"e_addi",     SCI8(6,16),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8}},
 {"e_subi",     SCI8(6,16),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8N}},
 {"e_addi.",    SCI8(6,17),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8}},
@@ -7097,6 +7112,16 @@ const struct powerpc_opcode vle_opcodes[] = {
 {"e_sthu",     OPVUP(6,5),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
 {"e_stwu",     OPVUP(6,6),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
 {"e_stmw",     OPVUP(6,9),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
+{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK,   PPCVLE, 0,              {D8, RA0}},
+{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK,   PPCVLE, 0,              {D8, RA0}},
+{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK,   PPCVLE, 0,              {D8, RA0}},
+{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK,   PPCVLE, 0,              {D8, RA0}},
+{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK,   PPCVLE, 0,              {D8, RA0}},
+{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK,   PPCVLE, 0,              {D8, RA0}},
+{"e_ldmvcsrrw",        OPVUPRT(6,16,5),OPVUPRT_MASK,   PPCVLE, 0,              {D8, RA0}},
+{"e_stmvcsrrw",        OPVUPRT(6,17,5),OPVUPRT_MASK,   PPCVLE, 0,              {D8, RA0}},
+{"e_ldmvdsrrw",        OPVUPRT(6,16,6),OPVUPRT_MASK,   PPCVLE, 0,              {D8, RA0}},
+{"e_stmvdsrrw",        OPVUPRT(6,17,6),OPVUPRT_MASK,   PPCVLE, 0,              {D8, RA0}},
 {"e_add16i",   OP(7),          OP_MASK,        PPCVLE, 0,              {RT, RA, SI}},
 {"e_la",       OP(7),          OP_MASK,        PPCVLE, 0,              {RT, D, RA0}},
 {"e_sub16i",   OP(7),          OP_MASK,        PPCVLE, 0,              {RT, RA, NSI}},
@@ -7144,10 +7169,8 @@ const struct powerpc_opcode vle_opcodes[] = {
 {"e_cmphl16i", IA16(28,23),    IA16_MASK,      PPCVLE, 0,              {RA, VLEUIMM}},
 {"e_cmph16i",  IA16(28,22),    IA16_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
 {"e_cmpl16i",  I16A(28,21),    I16A_MASK,      PPCVLE, 0,              {RA, VLEUIMM}},
-{"e_cmplwi",   I16A(28,21),    I16A_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
 {"e_mull2i",   I16A(28,20),    I16A_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
 {"e_cmp16i",   IA16(28,19),    IA16_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
-{"e_cmpwi",    IA16(28,19),    IA16_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
 {"e_sub2is",   I16A(28,18),    I16A_MASK,      PPCVLE, 0,              {RA, VLENSIMM}},
 {"e_add2is",   I16A(28,18),    I16A_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
 {"e_sub2i.",   I16A(28,17),    I16A_MASK,      PPCVLE, 0,              {RA, VLENSIMM}},