+++ /dev/null
-[root]
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-
-[system]
-type=System
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-symbolfile=
-thermal_components=
-thermal_model=Null
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-
-[system.clk_domain]
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-
-[system.cpu]
-type=MinorCPU
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-
-[system.cpu.branchPred]
-type=TournamentBP
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-
-[system.cpu.dcache]
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-system=system
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-
-[system.cpu.dcache.tags]
-type=LRU
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-
-[system.cpu.dstage2_mmu]
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-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
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-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
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-
-[system.cpu.dtb]
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-[system.cpu.dtb.walker]
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-
-[system.cpu.executeFuncUnits]
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-[system.cpu.executeFuncUnits.funcUnits0]
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-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:42:59
-gem5 executing on e108600-lin, pid 17323
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/arm/linux/minor-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Exiting @ tick 60130734500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.060161 # Number of seconds simulated
-sim_ticks 60161166500 # Number of ticks simulated
-final_tick 60161166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 318648 # Simulator instruction rate (inst/s)
-host_op_rate 407504 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 270326146 # Simulator tick rate (ticks/s)
-host_mem_usage 281460 # Number of bytes of host memory used
-host_seconds 222.55 # Real time elapsed on the host
-sim_insts 70915150 # Number of instructions simulated
-sim_ops 90690106 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 286272 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7938560 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8224832 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 286272 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 286272 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 4473 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 124040 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 128513 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 4758418 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 131954888 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 136713307 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 4758418 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 4758418 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 92074810 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 92074810 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 92074810 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 4758418 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 131954888 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 228788117 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128513 # Number of read requests accepted
-system.physmem.writeReqs 86552 # Number of write requests accepted
-system.physmem.readBursts 128513 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5537792 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 8224832 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 8086 # Per bank write bursts
-system.physmem.perBankRdBursts::1 8337 # Per bank write bursts
-system.physmem.perBankRdBursts::2 8257 # Per bank write bursts
-system.physmem.perBankRdBursts::3 8155 # Per bank write bursts
-system.physmem.perBankRdBursts::4 8300 # Per bank write bursts
-system.physmem.perBankRdBursts::5 8411 # Per bank write bursts
-system.physmem.perBankRdBursts::6 8071 # Per bank write bursts
-system.physmem.perBankRdBursts::7 7917 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8054 # Per bank write bursts
-system.physmem.perBankRdBursts::9 7612 # Per bank write bursts
-system.physmem.perBankRdBursts::10 7771 # Per bank write bursts
-system.physmem.perBankRdBursts::11 7824 # Per bank write bursts
-system.physmem.perBankRdBursts::12 7888 # Per bank write bursts
-system.physmem.perBankRdBursts::13 7869 # Per bank write bursts
-system.physmem.perBankRdBursts::14 7983 # Per bank write bursts
-system.physmem.perBankRdBursts::15 7973 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5399 # Per bank write bursts
-system.physmem.perBankWrBursts::1 5549 # Per bank write bursts
-system.physmem.perBankWrBursts::2 5478 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5349 # Per bank write bursts
-system.physmem.perBankWrBursts::4 5387 # Per bank write bursts
-system.physmem.perBankWrBursts::5 5588 # Per bank write bursts
-system.physmem.perBankWrBursts::6 5325 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5260 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5187 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5136 # Per bank write bursts
-system.physmem.perBankWrBursts::10 5306 # Per bank write bursts
-system.physmem.perBankWrBursts::11 5279 # Per bank write bursts
-system.physmem.perBankWrBursts::12 5541 # Per bank write bursts
-system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5706 # Per bank write bursts
-system.physmem.perBankWrBursts::15 5441 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 60161135000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 128513 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 86552 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 116119 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 12356 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::15 434 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 440 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4772 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5355 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::23 5355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5361 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::28 5427 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5453 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5436 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5416 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 32871 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 418.627483 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 258.357746 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 362.584215 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 8602 26.17% 26.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 6385 19.42% 45.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 3434 10.45% 56.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2432 7.40% 63.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2215 6.74% 70.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1621 4.93% 75.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1317 4.01% 79.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1216 3.70% 82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 5649 17.19% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 32871 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5351 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 24.014390 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 17.652764 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 347.251849 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5349 99.96% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5351 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5351 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.170435 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.160762 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.581098 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 4912 91.80% 91.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 3 0.06% 91.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 408 7.62% 99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 22 0.41% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 5 0.09% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5351 # Writes before turning the bus around for reads
-system.physmem.totQLat 3055484500 # Total ticks spent queuing
-system.physmem.totMemAccLat 5465009500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 23776.61 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 42526.61 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 136.71 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 92.05 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 136.71 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 92.07 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 1.79 # Data bus utilization in percentage
-system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing
-system.physmem.readRowHits 112270 # Number of row buffer hits during reads
-system.physmem.writeRowHits 69886 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 87.36 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 80.74 # Row buffer hit rate for writes
-system.physmem.avgGap 279734.66 # Average gap between requests
-system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 123657660 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 65710425 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 226208700 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 2513877600.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 2171898930 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 163742880 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 5875439160 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 3027961440 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 8657105625 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 23294071200 # Total energy per rank (pJ)
-system.physmem_0.averagePower 387.194467 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 54970200750 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 277627750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1068464000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 34200521750 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 7885291750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 3844571250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 12884690000 # Time in different power states
-system.physmem_1.actEnergy 111105540 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 59035020 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 449634360 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 225467460 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 2466550320.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 2149128000 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 155904480 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 5311061070 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 3203698560 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 8880552330 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 23012901840 # Total energy per rank (pJ)
-system.physmem_1.averagePower 382.520865 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 55040293250 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 259491500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1048576000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 35050414500 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 8342978750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 3812745000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 11646960750 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 14829931 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9922625 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 344341 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9711925 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6581090 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 67.762982 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1720914 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 175731 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 158482 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 17249 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 24894 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 1946 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 60161166500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 120322333 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 70915150 # Number of instructions committed
-system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1183243 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.696708 # CPI: cycles per instruction
-system.cpu.ipc 0.589376 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction
-system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 20555707 22.67% 100.00% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction
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-system.cpu.op_class_0::total 90690106 # Class of committed instruction
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-system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
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-system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26323.005553 # average ReadReq mshr miss latency
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-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78896.946565 # average SoftPFReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75135.486304 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75135.486304 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75697.160903 # average overall mshr miss latency
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-system.cpu.icache.tags.replacements 43580 # number of replacements
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-system.cpu.icache.tags.age_task_id_blocks_1024::3 897 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1022 # Occupied blocks per task id
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-system.cpu.icache.demand_avg_miss_latency::total 22903.951954 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22903.951954 # average overall miss latency
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-system.cpu.icache.overall_mshr_miss_latency::total 999325000 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21903.973873 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21903.973873 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21903.973873 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21903.973873 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21903.973873 # average overall mshr miss latency
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12846 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17826 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 783 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 3316701 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 3316701 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks 128143 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 128143 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 39976 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 39976 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 4721 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 4721 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41137 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 41137 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31723 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 31723 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 41137 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 36444 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 77581 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 41137 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 36444 # number of overall hits
-system.cpu.l2cache.overall_hits::total 77581 # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 102318 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 102318 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4486 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 4486 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21782 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 21782 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 4486 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 124100 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 128586 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 4486 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 124100 # number of overall misses
-system.cpu.l2cache.overall_misses::total 128586 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9273780500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 9273780500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 495081500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 495081500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2251192500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 2251192500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 495081500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 11524973000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 12020054500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 495081500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 11524973000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 12020054500 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 128143 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 128143 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 39976 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 39976 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 107039 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 107039 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45623 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 45623 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53505 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 53505 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 45623 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 160544 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 206167 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 45623 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 160544 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 206167 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955895 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.955895 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098328 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098328 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407102 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407102 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098328 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.772997 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.623698 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098328 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.772997 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.623698 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90636.842980 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90636.842980 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110361.457869 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110361.457869 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103351.046736 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103351.046736 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110361.457869 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92868.436745 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 93478.718523 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110361.457869 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92868.436745 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 93478.718523 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks
-system.cpu.l2cache.writebacks::total 86552 # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102318 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 102318 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4474 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4474 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21722 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21722 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 4474 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 124040 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 128514 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 4474 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 124040 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 128514 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8250600500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8250600500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 448924000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 448924000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029137000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029137000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 448924000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10279737500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 10728661500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 448924000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10279737500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 10728661500 # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955895 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955895 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098065 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405981 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405981 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772623 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.623349 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772623 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.623349 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80636.842980 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80636.842980 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100340.634779 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100340.634779 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93413.912163 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93413.912163 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100340.634779 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82874.375202 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83482.433820 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100340.634779 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82874.375202 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83482.433820 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 406195 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 200065 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7850 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 99127 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 214695 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 43580 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 38926 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 45623 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 53505 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134825 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 612361 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5708928 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18475968 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 24184896 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 97173 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 303340 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.037578 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.190694 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 291971 96.25% 96.25% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 11339 3.74% 99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 303340 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 374820500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 68448469 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 240848435 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 222299 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 93862 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 26195 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution
-system.membus.trans_dist::CleanEvict 7234 # Transaction distribution
-system.membus.trans_dist::ReadExReq 102318 # Transaction distribution
-system.membus.trans_dist::ReadExResp 102318 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 26195 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350812 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 350812 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764160 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 13764160 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 128513 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 128513 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 128513 # Request fanout histogram
-system.membus.reqLayer0.occupancy 588234000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 677366750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
-
-[system.cpu.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList26]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList27]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=12
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=vortex lendian.raw
-cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 17:55:48
-gem5 started Apr 3 2017 17:56:13
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54227
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/50.vortex/arm/linux/o3-timing
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 37944194500 because exiting with last active thread context
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.037944
-sim_ticks 37944194500
-final_tick 37944194500
-sim_freq 1000000000000
-host_inst_rate 98071
-host_op_rate 125422
-host_tick_rate 52480065
-host_mem_usage 294796
-host_seconds 723.02
-sim_insts 70907652
-sim_ops 90682607
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 37944194500
-system.physmem.bytes_read::cpu.inst 2366464
-system.physmem.bytes_read::cpu.data 5687552
-system.physmem.bytes_read::cpu.l2cache.prefetcher 6178176
-system.physmem.bytes_read::total 14232192
-system.physmem.bytes_inst_read::cpu.inst 2366464
-system.physmem.bytes_inst_read::total 2366464
-system.physmem.bytes_written::writebacks 6224000
-system.physmem.bytes_written::total 6224000
-system.physmem.num_reads::cpu.inst 36976
-system.physmem.num_reads::cpu.data 88868
-system.physmem.num_reads::cpu.l2cache.prefetcher 96534
-system.physmem.num_reads::total 222378
-system.physmem.num_writes::writebacks 97250
-system.physmem.num_writes::total 97250
-system.physmem.bw_read::cpu.inst 62366958
-system.physmem.bw_read::cpu.data 149892548
-system.physmem.bw_read::cpu.l2cache.prefetcher 162822695
-system.physmem.bw_read::total 375082201
-system.physmem.bw_inst_read::cpu.inst 62366958
-system.physmem.bw_inst_read::total 62366958
-system.physmem.bw_write::writebacks 164030363
-system.physmem.bw_write::total 164030363
-system.physmem.bw_total::writebacks 164030363
-system.physmem.bw_total::cpu.inst 62366958
-system.physmem.bw_total::cpu.data 149892548
-system.physmem.bw_total::cpu.l2cache.prefetcher 162822695
-system.physmem.bw_total::total 539112564
-system.physmem.readReqs 222379
-system.physmem.writeReqs 97250
-system.physmem.readBursts 222379
-system.physmem.writeBursts 97250
-system.physmem.bytesReadDRAM 14222400
-system.physmem.bytesReadWrQ 9856
-system.physmem.bytesWritten 6222336
-system.physmem.bytesReadSys 14232256
-system.physmem.bytesWrittenSys 6224000
-system.physmem.servicedByWrQ 154
-system.physmem.mergedWrBursts 1
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 9631
-system.physmem.perBankRdBursts::1 9947
-system.physmem.perBankRdBursts::2 12518
-system.physmem.perBankRdBursts::3 24674
-system.physmem.perBankRdBursts::4 17362
-system.physmem.perBankRdBursts::5 22065
-system.physmem.perBankRdBursts::6 11751
-system.physmem.perBankRdBursts::7 14087
-system.physmem.perBankRdBursts::8 11655
-system.physmem.perBankRdBursts::9 16110
-system.physmem.perBankRdBursts::10 11699
-system.physmem.perBankRdBursts::11 11328
-system.physmem.perBankRdBursts::12 9447
-system.physmem.perBankRdBursts::13 9546
-system.physmem.perBankRdBursts::14 9858
-system.physmem.perBankRdBursts::15 20547
-system.physmem.perBankWrBursts::0 5941
-system.physmem.perBankWrBursts::1 6221
-system.physmem.perBankWrBursts::2 6116
-system.physmem.perBankWrBursts::3 6136
-system.physmem.perBankWrBursts::4 6032
-system.physmem.perBankWrBursts::5 6294
-system.physmem.perBankWrBursts::6 6000
-system.physmem.perBankWrBursts::7 5967
-system.physmem.perBankWrBursts::8 5964
-system.physmem.perBankWrBursts::9 6073
-system.physmem.perBankWrBursts::10 6219
-system.physmem.perBankWrBursts::11 5919
-system.physmem.perBankWrBursts::12 6077
-system.physmem.perBankWrBursts::13 6073
-system.physmem.perBankWrBursts::14 6160
-system.physmem.perBankWrBursts::15 6032
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 0
-system.physmem.totGap 37944183500
-system.physmem.readPktSize::0 0
-system.physmem.readPktSize::1 0
-system.physmem.readPktSize::2 0
-system.physmem.readPktSize::3 0
-system.physmem.readPktSize::4 0
-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 222379
-system.physmem.writePktSize::0 0
-system.physmem.writePktSize::1 0
-system.physmem.writePktSize::2 0
-system.physmem.writePktSize::3 0
-system.physmem.writePktSize::4 0
-system.physmem.writePktSize::5 0
-system.physmem.writePktSize::6 97250
-system.physmem.rdQLenPdf::0 111691
-system.physmem.rdQLenPdf::1 60016
-system.physmem.rdQLenPdf::2 15678
-system.physmem.rdQLenPdf::3 10788
-system.physmem.rdQLenPdf::4 6218
-system.physmem.rdQLenPdf::5 5274
-system.physmem.rdQLenPdf::6 4596
-system.physmem.rdQLenPdf::7 4274
-system.physmem.rdQLenPdf::8 3538
-system.physmem.rdQLenPdf::9 92
-system.physmem.rdQLenPdf::10 47
-system.physmem.rdQLenPdf::11 9
-system.physmem.rdQLenPdf::12 4
-system.physmem.rdQLenPdf::13 0
-system.physmem.rdQLenPdf::14 0
-system.physmem.rdQLenPdf::15 0
-system.physmem.rdQLenPdf::16 0
-system.physmem.rdQLenPdf::17 0
-system.physmem.rdQLenPdf::18 0
-system.physmem.rdQLenPdf::19 0
-system.physmem.rdQLenPdf::20 0
-system.physmem.rdQLenPdf::21 0
-system.physmem.rdQLenPdf::22 0
-system.physmem.rdQLenPdf::23 0
-system.physmem.rdQLenPdf::24 0
-system.physmem.rdQLenPdf::25 0
-system.physmem.rdQLenPdf::26 0
-system.physmem.rdQLenPdf::27 0
-system.physmem.rdQLenPdf::28 0
-system.physmem.rdQLenPdf::29 0
-system.physmem.rdQLenPdf::30 0
-system.physmem.rdQLenPdf::31 0
-system.physmem.wrQLenPdf::0 1
-system.physmem.wrQLenPdf::1 1
-system.physmem.wrQLenPdf::2 1
-system.physmem.wrQLenPdf::3 1
-system.physmem.wrQLenPdf::4 1
-system.physmem.wrQLenPdf::5 1
-system.physmem.wrQLenPdf::6 1
-system.physmem.wrQLenPdf::7 1
-system.physmem.wrQLenPdf::8 1
-system.physmem.wrQLenPdf::9 1
-system.physmem.wrQLenPdf::10 1
-system.physmem.wrQLenPdf::11 1
-system.physmem.wrQLenPdf::12 1
-system.physmem.wrQLenPdf::13 1
-system.physmem.wrQLenPdf::14 1
-system.physmem.wrQLenPdf::15 1121
-system.physmem.wrQLenPdf::16 1197
-system.physmem.wrQLenPdf::17 1883
-system.physmem.wrQLenPdf::18 2533
-system.physmem.wrQLenPdf::19 3231
-system.physmem.wrQLenPdf::20 4047
-system.physmem.wrQLenPdf::21 4920
-system.physmem.wrQLenPdf::22 5457
-system.physmem.wrQLenPdf::23 5977
-system.physmem.wrQLenPdf::24 6465
-system.physmem.wrQLenPdf::25 6839
-system.physmem.wrQLenPdf::26 7294
-system.physmem.wrQLenPdf::27 7804
-system.physmem.wrQLenPdf::28 8411
-system.physmem.wrQLenPdf::29 8593
-system.physmem.wrQLenPdf::30 8015
-system.physmem.wrQLenPdf::31 6688
-system.physmem.wrQLenPdf::32 6307
-system.physmem.wrQLenPdf::33 243
-system.physmem.wrQLenPdf::34 104
-system.physmem.wrQLenPdf::35 40
-system.physmem.wrQLenPdf::36 33
-system.physmem.wrQLenPdf::37 12
-system.physmem.wrQLenPdf::38 8
-system.physmem.wrQLenPdf::39 7
-system.physmem.wrQLenPdf::40 4
-system.physmem.wrQLenPdf::41 1
-system.physmem.wrQLenPdf::42 0
-system.physmem.wrQLenPdf::43 0
-system.physmem.wrQLenPdf::44 0
-system.physmem.wrQLenPdf::45 0
-system.physmem.wrQLenPdf::46 0
-system.physmem.wrQLenPdf::47 0
-system.physmem.wrQLenPdf::48 0
-system.physmem.wrQLenPdf::49 0
-system.physmem.wrQLenPdf::50 0
-system.physmem.wrQLenPdf::51 0
-system.physmem.wrQLenPdf::52 0
-system.physmem.wrQLenPdf::53 0
-system.physmem.wrQLenPdf::54 0
-system.physmem.wrQLenPdf::55 0
-system.physmem.wrQLenPdf::56 0
-system.physmem.wrQLenPdf::57 0
-system.physmem.wrQLenPdf::58 0
-system.physmem.wrQLenPdf::59 0
-system.physmem.wrQLenPdf::60 0
-system.physmem.wrQLenPdf::61 0
-system.physmem.wrQLenPdf::62 0
-system.physmem.wrQLenPdf::63 0
-system.physmem.bytesPerActivate::samples 132661
-system.physmem.bytesPerActivate::mean 154.093818
-system.physmem.bytesPerActivate::gmean 102.620444
-system.physmem.bytesPerActivate::stdev 209.524421
-system.physmem.bytesPerActivate::0-127 82661 62.31% 62.31%
-system.physmem.bytesPerActivate::128-255 32331 24.37% 86.68%
-system.physmem.bytesPerActivate::256-383 6343 4.78% 91.46%
-system.physmem.bytesPerActivate::384-511 2828 2.13% 93.59%
-system.physmem.bytesPerActivate::512-639 1153 0.87% 94.46%
-system.physmem.bytesPerActivate::640-767 1000 0.75% 95.22%
-system.physmem.bytesPerActivate::768-895 785 0.59% 95.81%
-system.physmem.bytesPerActivate::896-1023 836 0.63% 96.44%
-system.physmem.bytesPerActivate::1024-1151 4724 3.56% 100.00%
-system.physmem.bytesPerActivate::total 132661
-system.physmem.rdPerTurnAround::samples 5873
-system.physmem.rdPerTurnAround::mean 37.833986
-system.physmem.rdPerTurnAround::stdev 211.191475
-system.physmem.rdPerTurnAround::0-511 5868 99.91% 99.91%
-system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98%
-system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00%
-system.physmem.rdPerTurnAround::total 5873
-system.physmem.wrPerTurnAround::samples 5873
-system.physmem.wrPerTurnAround::mean 16.554401
-system.physmem.wrPerTurnAround::gmean 16.514141
-system.physmem.wrPerTurnAround::stdev 1.221324
-system.physmem.wrPerTurnAround::16 4642 79.04% 79.04%
-system.physmem.wrPerTurnAround::17 60 1.02% 80.06%
-system.physmem.wrPerTurnAround::18 721 12.28% 92.34%
-system.physmem.wrPerTurnAround::19 237 4.04% 96.37%
-system.physmem.wrPerTurnAround::20 117 1.99% 98.37%
-system.physmem.wrPerTurnAround::21 50 0.85% 99.22%
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-system.cpu.toL2Bus.snoop_filter.tot_requests 1620984
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 810002
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-system.cpu.toL2Bus.snoop_fanout::stdev 0.288334
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-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570155
-system.membus.pkt_count::total 570155
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20456192
-system.membus.pkt_size::total 20456192
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 222393
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 222393 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 222393
-system.membus.reqLayer0.occupancy 835299244
-system.membus.reqLayer0.utilization 2.2
-system.membus.respLayer1.occupancy 1174434906
-system.membus.respLayer1.utilization 3.1
-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Korey Sewell
-
-m5.util.addToPath('../configs/common')
-from cpu2000 import vortex
-
-workload = vortex(isa, opsys, 'smred')
-root.system.cpu[0].workload = workload.makeProcess()
projects / gem5.git / commitdiff