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XLEN-ify maddedu
authorJacob Lifshay <programmerjake@gmail.com>
Fri, 11 Nov 2022 08:49:52 +0000 (00:49 -0800)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:16 +0000 (19:51 +0100)
openpower/isa/svfixedarith.mdwn patch | blob | history

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 02bb5d62ce4c8ea985ca5741abd4590f686e6133..c7050133f2eae8c4d9d8f864a07621f046dc2158 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -9,10 +9,10 @@ Pseudo-code:
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
-    prod[0:127] <- (RA) * (RB)
-    sum[0:127] <- ([0] * 64 || (RC)) + prod
-    RT <- sum[64:127]
-    RS <- sum[0:63]
+    prod[0:2*XLEN-1] <- (RA) * (RB)
+    sum[0:2*XLEN-1] <- ([0] * XLEN || (RC)) + prod
+    RT <- sum[XLEN:2*XLEN-1]
+    RS <- sum[0:XLEN-1]
 
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