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re PR target/88461 (AVX512: gcc should keep value in kN registers if possible)
authorJakub Jelinek <jakub@redhat.com>
Thu, 13 Dec 2018 08:00:42 +0000 (09:00 +0100)
committerJakub Jelinek <jakub@gcc.gnu.org>
Thu, 13 Dec 2018 08:00:42 +0000 (09:00 +0100)
PR target/88461
* config/i386/sse.md (VI1248_AVX512VLBW, AVX512ZEXTMASK): New
mode iterators.
(<avx512>_testm<mode>3<mask_scalar_merge_name>,
<avx512>_testnm<mode>3<mask_scalar_merge_name>): Merge patterns
with VI12_AVX512VL and VI48_AVX512VL iterators into ones with
VI1248_AVX512VLBW iterator.
(*<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext,
*<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext_mask,
*<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext,
*<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext_mask): New
define_insns.

* gcc.target/i386/pr88461.c: New test.

From-SVN: r267077

gcc/ChangeLog patch | blob | history
gcc/config/i386/sse.md patch | blob | history
gcc/testsuite/ChangeLog patch | blob | history
gcc/testsuite/gcc.target/i386/pr88461.c [new file with mode: 0644] patch | blob

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4e96dd061cab4493a70a02f0a3fa18c9fb29c6cf..55c291b8e592df0c3ad594e97e353a7901749a75 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,18 @@
 2018-12-13  Jakub Jelinek  <jakub@redhat.com>
 
+       PR target/88461
+       * config/i386/sse.md (VI1248_AVX512VLBW, AVX512ZEXTMASK): New
+       mode iterators.
+       (<avx512>_testm<mode>3<mask_scalar_merge_name>,
+       <avx512>_testnm<mode>3<mask_scalar_merge_name>): Merge patterns
+       with VI12_AVX512VL and VI48_AVX512VL iterators into ones with
+       VI1248_AVX512VLBW iterator.
+       (*<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext,
+       *<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext_mask,
+       *<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext,
+       *<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext_mask): New
+       define_insns.
+
        PR target/88461
        * config/i386/i386.md (*zero_extendsidi2, zero_extend<mode>di2,
        *zero_extend<mode>si2, *zero_extendqihi2): Add =*k, *km alternatives.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 52db04dda970c73387109d83c69fc35678cb5061..be65f902d9ebe48d79aac7c2519b758232c65ebb 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -12322,22 +12322,22 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
-  [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
-       (unspec:<avx512fmaskmode>
-        [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
-         (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
-        UNSPEC_TESTM))]
-  "TARGET_AVX512BW"
-  "vptestm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
-  [(set_attr "prefix" "evex")
-   (set_attr "mode"  "<sseinsnmode>")])
+(define_mode_iterator VI1248_AVX512VLBW
+  [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL && TARGET_AVX512BW")
+   (V16QI "TARGET_AVX512VL && TARGET_AVX512BW")
+   (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW")
+   (V8HI "TARGET_AVX512VL && TARGET_AVX512BW")
+   V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")
+   V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
+
+(define_mode_iterator AVX512ZEXTMASK
+  [(DI "TARGET_AVX512BW") (SI "TARGET_AVX512BW") HI])
 
 (define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
        (unspec:<avx512fmaskmode>
-        [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
-         (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
+        [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
+         (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
         UNSPEC_TESTM))]
   "TARGET_AVX512F"
   "vptestm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
@@ -12347,24 +12347,73 @@
 (define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
        (unspec:<avx512fmaskmode>
-        [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
-         (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
+        [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
+         (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
         UNSPEC_TESTNM))]
-  "TARGET_AVX512BW"
+  "TARGET_AVX512F"
   "vptestnm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
   [(set_attr "prefix" "evex")
    (set_attr "mode"  "<sseinsnmode>")])
 
-(define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"
-  [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
-       (unspec:<avx512fmaskmode>
-        [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
-         (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
-        UNSPEC_TESTNM))]
-  "TARGET_AVX512F"
-  "vptestnm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
+(define_insn "*<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext"
+  [(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk")
+       (zero_extend:AVX512ZEXTMASK
+         (unspec:<VI1248_AVX512VLBW:avx512fmaskmode>
+          [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
+           (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
+          UNSPEC_TESTM)))]
+  "TARGET_AVX512BW
+   && (<AVX512ZEXTMASK:MODE_SIZE>
+       > GET_MODE_SIZE (<VI1248_AVX512VLBW:avx512fmaskmode>mode))"
+  "vptestm<VI1248_AVX512VLBW:ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "prefix" "evex")
-   (set_attr "mode"  "<sseinsnmode>")])
+   (set_attr "mode"  "<VI1248_AVX512VLBW:sseinsnmode>")])
+
+(define_insn "*<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext_mask"
+  [(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk")
+       (zero_extend:AVX512ZEXTMASK
+         (and:<VI1248_AVX512VLBW:avx512fmaskmode>
+           (unspec:<VI1248_AVX512VLBW:avx512fmaskmode>
+            [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
+             (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
+            UNSPEC_TESTM)
+           (match_operand:<VI1248_AVX512VLBW:avx512fmaskmode> 3 "register_operand" "Yk"))))]
+  "TARGET_AVX512BW
+   && (<AVX512ZEXTMASK:MODE_SIZE>
+       > GET_MODE_SIZE (<VI1248_AVX512VLBW:avx512fmaskmode>mode))"
+  "vptestm<VI1248_AVX512VLBW:ssemodesuffix>\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}"
+  [(set_attr "prefix" "evex")
+   (set_attr "mode"  "<VI1248_AVX512VLBW:sseinsnmode>")])
+
+(define_insn "*<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext"
+  [(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk")
+       (zero_extend:AVX512ZEXTMASK
+         (unspec:<VI1248_AVX512VLBW:avx512fmaskmode>
+          [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
+           (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
+          UNSPEC_TESTNM)))]
+  "TARGET_AVX512BW
+   && (<AVX512ZEXTMASK:MODE_SIZE>
+       > GET_MODE_SIZE (<VI1248_AVX512VLBW:avx512fmaskmode>mode))"
+  "vptestnm<VI1248_AVX512VLBW:ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "prefix" "evex")
+   (set_attr "mode"  "<VI1248_AVX512VLBW:sseinsnmode>")])
+
+(define_insn "*<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext_mask"
+  [(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk")
+       (zero_extend:AVX512ZEXTMASK
+         (and:<VI1248_AVX512VLBW:avx512fmaskmode>
+           (unspec:<VI1248_AVX512VLBW:avx512fmaskmode>
+            [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
+             (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
+            UNSPEC_TESTNM)
+           (match_operand:<VI1248_AVX512VLBW:avx512fmaskmode> 3 "register_operand" "Yk"))))]
+  "TARGET_AVX512BW
+   && (<AVX512ZEXTMASK:MODE_SIZE>
+       > GET_MODE_SIZE (<VI1248_AVX512VLBW:avx512fmaskmode>mode))"
+  "vptestnm<VI1248_AVX512VLBW:ssemodesuffix>\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}"
+  [(set_attr "prefix" "evex")
+   (set_attr "mode"  "<VI1248_AVX512VLBW:sseinsnmode>")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 856dfdf8d4593798c65eafa6199d023499237421..295b160ee54d44a3a3c86307e8bec35bf61ebe59 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-12-13  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/88461
+       * gcc.target/i386/pr88461.c: New test.
+       
 2018-12-12  Paolo Carlini  <paolo.carlini@oracle.com>
 
        * g++.dg/other/static5.C: New.
diff --git a/gcc/testsuite/gcc.target/i386/pr88461.c b/gcc/testsuite/gcc.target/i386/pr88461.c
new file mode 100644 (file)
index 0000000..68349c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr88461.c
@@ -0,0 +1,16 @@
+/* PR target/88461 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw" } */
+/* { dg-final { scan-assembler-times "kmovw\[ \t]" 2 } } */
+
+#include <x86intrin.h>
+
+int
+foo (const __m128i *data, int a)
+{
+  __m128i v = _mm_load_si128 (data);
+  __mmask16 m = _mm_testn_epi16_mask (v, v);
+  m = _kshiftli_mask16 (m, 1);
+  m = _kandn_mask16 (m, a);
+  return m;
+}