if (!rmesa->radeon.radeonScreen->kernel_mm) {
OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
- OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset,
- rmesa->tcl.elt_dma_bo,
- rmesa->tcl.elt_dma_offset,
+ OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
+ rmesa->radeon.tcl.elt_dma_bo,
+ rmesa->radeon.tcl.elt_dma_offset,
RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_BATCH(vertex_count/2);
} else {
OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
- OUT_BATCH(rmesa->tcl.elt_dma_offset);
+ OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
OUT_BATCH(vertex_count/2);
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.elt_dma_bo,
+ rmesa->radeon.tcl.elt_dma_bo,
RADEON_GEM_DOMAIN_GTT, 0, 0);
}
END_BATCH();
nr = elt_used / 2;
- radeon_bo_unmap(rmesa->tcl.elt_dma_bo);
+ radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
- radeon_bo_unref(rmesa->tcl.elt_dma_bo);
- rmesa->tcl.elt_dma_bo = NULL;
+ radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
+ rmesa->radeon.tcl.elt_dma_bo = NULL;
if (R200_DEBUG & DEBUG_SYNC) {
fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
radeonEmitState(&rmesa->radeon);
- rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
+ rmesa->radeon.tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
0, R200_ELT_BUF_SZ, 4,
RADEON_GEM_DOMAIN_GTT, 0);
- rmesa->tcl.elt_dma_offset = 0;
+ rmesa->radeon.tcl.elt_dma_offset = 0;
rmesa->tcl.elt_used = min_nr * 2;
- radeon_bo_map(rmesa->tcl.elt_dma_bo, 1);
- retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset;
+ radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
+ retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
if (R200_DEBUG & DEBUG_PRIMS)
if (!rmesa->radeon.radeonScreen->kernel_mm) {
for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
- (rmesa->tcl.aos[i].stride << 8) |
- (rmesa->tcl.aos[i + 1].components << 16) |
- (rmesa->tcl.aos[i + 1].stride << 24));
+ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+ (rmesa->radeon.tcl.aos[i].stride << 8) |
+ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[i].bo,
+ rmesa->radeon.tcl.aos[i].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[i+1].bo,
+ rmesa->radeon.tcl.aos[i+1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
- OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
- (rmesa->tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[nr - 1].bo,
+ rmesa->radeon.tcl.aos[nr - 1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
} else {
for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
- (rmesa->tcl.aos[i].stride << 8) |
- (rmesa->tcl.aos[i + 1].components << 16) |
- (rmesa->tcl.aos[i + 1].stride << 24));
+ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+ (rmesa->radeon.tcl.aos[i].stride << 8) |
+ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH(voffset);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH(voffset);
}
if (nr & 1) {
- OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
- (rmesa->tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH(voffset);
}
for (i = 0; i + 1 < nr; i += 2) {
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[i+0].bo,
+ rmesa->radeon.tcl.aos[i+0].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[i+1].bo,
+ rmesa->radeon.tcl.aos[i+1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[nr-1].bo,
+ rmesa->radeon.tcl.aos[nr-1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
}
-/* Destroy the device specific context.
- */
-/* Destroy the Mesa and driver specific context data.
- */
-void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
-{
- GET_CURRENT_CONTEXT(ctx);
- r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate;
- r200ContextPtr current = ctx ? R200_CONTEXT(ctx) : NULL;
-
- /* check if we're deleting the currently bound context */
- if (rmesa == current) {
- radeon_firevertices(&rmesa->radeon);
- _mesa_make_current(NULL, NULL, NULL);
- }
-
- /* Free r200 context resources */
- assert(rmesa); /* should never be null */
- if ( rmesa ) {
-
- _swsetup_DestroyContext( rmesa->radeon.glCtx );
- _tnl_DestroyContext( rmesa->radeon.glCtx );
- _vbo_DestroyContext( rmesa->radeon.glCtx );
- _swrast_DestroyContext( rmesa->radeon.glCtx );
-
- r200DestroySwtcl( rmesa->radeon.glCtx );
- r200ReleaseArrays( rmesa->radeon.glCtx, ~0 );
-
- if (rmesa->radeon.dma.current) {
- radeonReleaseDmaRegion( &rmesa->radeon );
- rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
- }
-
- if (rmesa->radeon.state.scissor.pClipRects) {
- FREE(rmesa->radeon.state.scissor.pClipRects);
- rmesa->radeon.state.scissor.pClipRects = NULL;
- }
-
- radeonCleanupContext(&rmesa->radeon);
-
- FREE( rmesa );
- }
-}
-
-
-
-/* Force the context `c' to be unbound from its buffer.
- */
-GLboolean
-r200UnbindContext( __DRIcontextPrivate *driContextPriv )
-{
- r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate;
-
- if (R200_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)rmesa->radeon.glCtx);
-
- return GL_TRUE;
-}
struct r200_tcl_info {
GLuint hw_primitive;
-/* hw can handle 12 components max */
- struct radeon_aos aos[12];
- GLuint nr_aos_components;
-
GLuint *Elts;
- struct radeon_bo *elt_dma_bo;
- int elt_dma_offset; /** Offset into this buffer object, in bytes */
int elt_used;
};
#include "r200_context.h"
extern void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev );
-extern void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs );
#endif
case 3:
/* special handling to fix up fog. Will get us into trouble with vbos...*/
assert(attrib == VERT_ATTRIB_FOG);
- if (!rmesa->tcl.aos[i].bo) {
+ if (!rmesa->radeon.tcl.aos[i].bo) {
if (ctx->VertexProgram._Enabled)
rcommon_emit_vector( ctx,
- &(rmesa->tcl.aos[nr]),
+ &(rmesa->radeon.tcl.aos[nr]),
(char *)VB->AttribPtr[attrib]->data,
1,
VB->AttribPtr[attrib]->stride,
count);
else
r200_emit_vecfog( ctx,
- &(rmesa->tcl.aos[nr]),
+ &(rmesa->radeon.tcl.aos[nr]),
(char *)VB->AttribPtr[attrib]->data,
VB->AttribPtr[attrib]->stride,
count);
default:
assert(0);
}
- if (!rmesa->tcl.aos[nr].bo) {
+ if (!rmesa->radeon.tcl.aos[nr].bo) {
rcommon_emit_vector( ctx,
- &(rmesa->tcl.aos[nr]),
+ &(rmesa->radeon.tcl.aos[nr]),
(char *)VB->AttribPtr[attrib]->data,
emitsize,
VB->AttribPtr[attrib]->stride,
rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = vfmt1;
}
- rmesa->tcl.nr_aos_components = nr;
+ rmesa->radeon.tcl.aos_count = nr;
}
-
-void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs )
-{
- r200ContextPtr rmesa = R200_CONTEXT( ctx );
- int i;
- for (i = 0; i < rmesa->tcl.nr_aos_components; i++) {
- if (rmesa->tcl.aos[i].bo) {
- radeon_bo_unref(rmesa->tcl.aos[i].bo);
- rmesa->tcl.aos[i].bo = NULL;
- }
- }
-}
extern GLboolean r200ValidateState( GLcontext *ctx );
-extern void r200PrintDirty( r200ContextPtr rmesa,
- const char *msg );
-
-
extern void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode );
#define FALLBACK( rmesa, bit, mode ) do { \
if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n", \
/* =============================================================
* State initialization
*/
-
-void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
-{
- struct radeon_state_atom *l;
-
- fprintf(stderr, msg);
- fprintf(stderr, ": ");
-
- foreach(l, &rmesa->radeon.hw.atomlist) {
- if (l->dirty || rmesa->radeon.hw.all_dirty)
- fprintf(stderr, "%s, ", l->name);
- }
-
- fprintf(stderr, "\n");
-}
-
static int cmdpkt( r200ContextPtr rmesa, int id )
{
drm_radeon_cmd_header_t h;
rmesa->radeon.swtcl.hw_primitive = 0;
}
-
-void r200DestroySwtcl( GLcontext *ctx )
-{
-}
#include "r200_context.h"
extern void r200InitSwtcl( GLcontext *ctx );
-extern void r200DestroySwtcl( GLcontext *ctx );
extern void r200ChooseRenderState( GLcontext *ctx );
extern void r200ChooseVertexState( GLcontext *ctx );
if (rmesa->radeon.dma.flush == r200FlushElts &&
rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) {
- GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr +
+ GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr +
rmesa->tcl.elt_used);
rmesa->tcl.elt_used += nr*2;
if (rmesa->radeon.dma.flush)
rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
- rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__);
+ rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__);
r200EmitAOS( rmesa,
- rmesa->tcl.nr_aos_components, 0 );
+ rmesa->radeon.tcl.aos_count, 0 );
return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr );
}
r200ContextPtr rmesa = R200_CONTEXT( ctx );
r200TclPrimitive( ctx, prim, hwprim );
- // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components);
+ // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count);
rcommonEnsureCmdBufSpace( &rmesa->radeon,
- AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
+ AOS_BUFSZ(rmesa->radeon.tcl.aos_count) +
rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
r200EmitAOS( rmesa,
- rmesa->tcl.nr_aos_components,
+ rmesa->radeon.tcl.aos_count,
start );
/* Why couldn't this packet have taken an offset param?
/* Do the actual work:
*/
- r200ReleaseArrays( ctx, ~0 /* stage->changed_inputs */ );
+ radeonReleaseArrays( ctx, ~0 /* stage->changed_inputs */ );
r200EmitArrays( ctx, vimap_rev );
rmesa->tcl.Elts = VB->Elts;
tnl->Driver.NotifyMaterialChange =
_mesa_validate_all_lighting_tables;
- r200ReleaseArrays( ctx, ~0 );
+ radeonReleaseArrays( ctx, ~0 );
/* Still using the D3D based hardware-rasterizer from the radeon;
* need to put the card into D3D mode to make it work:
rcommonInitCmdBuf(&r300->radeon);
}
-
-/**
- * Destroy the command buffer and state atoms.
- */
-void r300DestroyCmdBuf(r300ContextPtr r300)
-{
- struct radeon_state_atom *atom;
-
- foreach(atom, &r300->radeon.hw.atomlist) {
- FREE(atom->cmd);
- }
-
-}
#include "r300_context.h"
extern void r300InitCmdBuf(r300ContextPtr r300);
-extern void r300DestroyCmdBuf(r300ContextPtr r300);
-
void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom);
int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom);
return GL_TRUE;
}
-/* Destroy the device specific context.
- */
-void r300DestroyContext(__DRIcontextPrivate * driContextPriv)
-{
- GET_CURRENT_CONTEXT(ctx);
- r300ContextPtr r300 = (r300ContextPtr) driContextPriv->driverPrivate;
- radeonContextPtr radeon = (radeonContextPtr) r300;
- radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
-
- if (RADEON_DEBUG & DEBUG_DRI) {
- fprintf(stderr, "Destroying context !\n");
- }
-
- /* check if we're deleting the currently bound context */
- if (&r300->radeon == current) {
- radeonFlush(r300->radeon.glCtx);
- _mesa_make_current(NULL, NULL, NULL);
- }
-
- /* Free r300 context resources */
- assert(r300); /* should never be null */
-
- if (r300) {
- _swsetup_DestroyContext(r300->radeon.glCtx);
- _tnl_DestroyContext(r300->radeon.glCtx);
- _vbo_DestroyContext(r300->radeon.glCtx);
- _swrast_DestroyContext(r300->radeon.glCtx);
-
- radeon_firevertices(&r300->radeon);
-
- if (radeon->state.scissor.pClipRects) {
- FREE(radeon->state.scissor.pClipRects);
- radeon->state.scissor.pClipRects = NULL;
- }
-
- r300DestroyCmdBuf(r300);
-
- radeonCleanupContext(&r300->radeon);
-
-
- /* the memory manager might be accessed when Mesa frees the shared
- * state, so don't destroy it earlier
- */
-
-
- FREE(r300);
- }
-}
struct r300_texture_state texture;
int sw_tcl_inputs[VERT_ATTRIB_MAX];
struct r300_vertex_shader_state vertex_shader;
- struct radeon_aos aos[R300_MAX_AOS_ARRAYS];
- int aos_count;
- struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
- int elt_dma_offset; /** Offset into this buffer object, in bytes */
DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for.
They are the same as tnl->render_inputs for fixed pipeline */
for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) {
swizzle[i][ci] = ci;
}
- rcommon_emit_vector(ctx, &rmesa->state.aos[i],
+ rcommon_emit_vector(ctx, &rmesa->radeon.tcl.aos[i],
vb->AttribPtr[tab[i]]->data,
vb->AttribPtr[tab[i]]->size,
vb->AttribPtr[tab[i]]->stride, count);
rmesa->hw.vof.cmd[R300_VOF_CNTL_1] =
r300VAPOutputCntl1(ctx, OutputsWritten);
- rmesa->state.aos_count = nr;
+ rmesa->radeon.tcl.aos_count = nr;
return R300_FALLBACK_NONE;
}
-void r300ReleaseArrays(GLcontext * ctx)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- int i;
-
- if (rmesa->state.elt_dma_bo) {
- radeon_bo_unref(rmesa->state.elt_dma_bo);
- rmesa->state.elt_dma_bo = NULL;
- }
- for (i = 0; i < rmesa->state.aos_count; i++) {
- if (rmesa->state.aos[i].bo) {
- radeon_bo_unref(rmesa->state.aos[i].bo);
- rmesa->state.aos[i].bo = NULL;
- }
- }
-}
-
void r300EmitCacheFlush(r300ContextPtr rmesa)
{
BATCH_LOCALS(&rmesa->radeon);
extern int r300EmitArrays(GLcontext * ctx);
-extern void r300ReleaseArrays(GLcontext * ctx);
extern int r300PrimitiveType(r300ContextPtr rmesa, int prim);
extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
r300ContextPtr rmesa = R300_CONTEXT(ctx);
void *out;
- radeonAllocDmaRegion(&rmesa->radeon, &rmesa->state.elt_dma_bo,
- &rmesa->state.elt_dma_offset, n_elts * 4, 4);
- radeon_bo_map(rmesa->state.elt_dma_bo, 1);
- out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset;
+ radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo,
+ &rmesa->radeon.tcl.elt_dma_offset, n_elts * 4, 4);
+ radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
+ out = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
memcpy(out, elts, n_elts * 4);
- radeon_bo_unmap(rmesa->state.elt_dma_bo);
+ radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
}
static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
(R300_VAP_PORT_IDX0 >> 2));
- OUT_BATCH_RELOC(rmesa->state.elt_dma_offset,
- rmesa->state.elt_dma_bo,
- rmesa->state.elt_dma_offset,
+ OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
+ rmesa->radeon.tcl.elt_dma_bo,
+ rmesa->radeon.tcl.elt_dma_offset,
RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_BATCH(vertex_count);
} else {
OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
(R300_VAP_PORT_IDX0 >> 2));
- OUT_BATCH(rmesa->state.elt_dma_offset);
+ OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
OUT_BATCH(vertex_count);
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->state.elt_dma_bo,
+ rmesa->radeon.tcl.elt_dma_bo,
RADEON_GEM_DOMAIN_GTT, 0, 0);
}
END_BATCH();
OUT_BATCH(nr);
for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->state.aos[i].components << 0) |
- (rmesa->state.aos[i].stride << 8) |
- (rmesa->state.aos[i + 1].components << 16) |
- (rmesa->state.aos[i + 1].stride << 24));
+ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+ (rmesa->radeon.tcl.aos[i].stride << 8) |
+ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
- voffset = rmesa->state.aos[i + 0].offset +
- offset * 4 * rmesa->state.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->state.aos[i].bo,
+ rmesa->radeon.tcl.aos[i].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
- voffset = rmesa->state.aos[i + 1].offset +
- offset * 4 * rmesa->state.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->state.aos[i+1].bo,
+ rmesa->radeon.tcl.aos[i+1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
- OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) |
- (rmesa->state.aos[nr - 1].stride << 8));
- voffset = rmesa->state.aos[nr - 1].offset +
- offset * 4 * rmesa->state.aos[nr - 1].stride;
+ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->state.aos[nr - 1].bo,
+ rmesa->radeon.tcl.aos[nr - 1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
OUT_BATCH(nr);
for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->state.aos[i].components << 0) |
- (rmesa->state.aos[i].stride << 8) |
- (rmesa->state.aos[i + 1].components << 16) |
- (rmesa->state.aos[i + 1].stride << 24));
+ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+ (rmesa->radeon.tcl.aos[i].stride << 8) |
+ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
- voffset = rmesa->state.aos[i + 0].offset +
- offset * 4 * rmesa->state.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH(voffset);
- voffset = rmesa->state.aos[i + 1].offset +
- offset * 4 * rmesa->state.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH(voffset);
}
if (nr & 1) {
- OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) |
- (rmesa->state.aos[nr - 1].stride << 8));
- voffset = rmesa->state.aos[nr - 1].offset +
- offset * 4 * rmesa->state.aos[nr - 1].stride;
+ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH(voffset);
}
for (i = 0; i + 1 < nr; i += 2) {
- voffset = rmesa->state.aos[i + 0].offset +
- offset * 4 * rmesa->state.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->state.aos[i+0].bo,
+ rmesa->radeon.tcl.aos[i+0].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
- voffset = rmesa->state.aos[i + 1].offset +
- offset * 4 * rmesa->state.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->state.aos[i+1].bo,
+ rmesa->radeon.tcl.aos[i+1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
- voffset = rmesa->state.aos[nr - 1].offset +
- offset * 4 * rmesa->state.aos[nr - 1].stride;
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->state.aos[nr-1].bo,
+ rmesa->radeon.tcl.aos[nr-1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
* arrays. *sigh*
*/
r300EmitElts(ctx, vb->Elts, num_verts);
- r300EmitAOS(rmesa, rmesa->state.aos_count, start);
+ r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
r300FireEB(rmesa, num_verts, type);
} else {
- r300EmitAOS(rmesa, rmesa->state.aos_count, start);
+ r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
r300FireAOS(rmesa, num_verts, type);
}
COMMIT_BATCH();
r300EmitCacheFlush(rmesa);
- r300ReleaseArrays(ctx);
+ radeonReleaseArrays(ctx, ~0);
return GL_FALSE;
}
radeon_bo_legacy.c \
radeon_cs_legacy.c \
radeon_mipmap_tree.c \
- radeon_span.c
+ radeon_span.c \
+ radeon_fbo.c
DRIVER_SOURCES = \
radeon_context.c \
#include "utils.h"
#include "vblank.h"
#include "drirenderbuffer.h"
+#include "main/context.h"
#include "main/framebuffer.h"
#include "main/state.h"
+#include "main/simple_list.h"
+#include "swrast/swrast.h"
+#include "swrast_setup/swrast_setup.h"
+#include "tnl/tnl.h"
#define DRIVER_DATE "20090101"
return GL_TRUE;
}
+
+
+/**
+ * Destroy the command buffer and state atoms.
+ */
+static void radeon_destroy_atom_list(radeonContextPtr radeon)
+{
+ struct radeon_state_atom *atom;
+
+ foreach(atom, &radeon->hw.atomlist) {
+ FREE(atom->cmd);
+ if (atom->lastcmd)
+ FREE(atom->lastcmd);
+ }
+
+}
+
/**
* Cleanup common context fields.
* Called by r200DestroyContext/r300DestroyContext
*/
-void radeonCleanupContext(radeonContextPtr radeon)
+void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
{
#ifdef RADEON_BO_TRACK
FILE *track;
#endif
- struct radeon_framebuffer *rfb;
-
- radeonDestroyBuffer(radeon->dri.drawable);
- radeonDestroyBuffer(radeon->dri.readable);
-
- /* free the Mesa context */
- _mesa_destroy_context(radeon->glCtx);
-
- /* _mesa_destroy_context() might result in calls to functions that
- * depend on the DriverCtx, so don't set it to NULL before.
- *
- * radeon->glCtx->DriverCtx = NULL;
- */
-
+ GET_CURRENT_CONTEXT(ctx);
+ radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
+ radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
+ if (radeon == current) {
+ radeon_firevertices(radeon);
+ _mesa_make_current(NULL, NULL, NULL);
+ }
+
+ assert(radeon);
+ if (radeon) {
- /* free the option cache */
- driDestroyOptionCache(&radeon->optionCache);
+ if (radeon->dma.current) {
+ radeonReleaseDmaRegion( radeon );
+ rcommonFlushCmdBuf( radeon, __FUNCTION__ );
+ }
- rcommonDestroyCmdBuf(radeon);
+ radeonReleaseArrays(ctx, ~0);
- if (radeon->state.scissor.pClipRects) {
- FREE(radeon->state.scissor.pClipRects);
- radeon->state.scissor.pClipRects = 0;
+ if (radeon->vtbl.free_context)
+ radeon->vtbl.free_context(radeon->glCtx);
+ _swsetup_DestroyContext( radeon->glCtx );
+ _tnl_DestroyContext( radeon->glCtx );
+ _vbo_DestroyContext( radeon->glCtx );
+ _swrast_DestroyContext( radeon->glCtx );
+
+ radeonDestroyBuffer(radeon->dri.drawable);
+ radeonDestroyBuffer(radeon->dri.readable);
+
+ /* free atom list */
+ /* free the Mesa context */
+ _mesa_destroy_context(radeon->glCtx);
+
+ /* _mesa_destroy_context() might result in calls to functions that
+ * depend on the DriverCtx, so don't set it to NULL before.
+ *
+ * radeon->glCtx->DriverCtx = NULL;
+ */
+ /* free the option cache */
+ driDestroyOptionCache(&radeon->optionCache);
+
+ rcommonDestroyCmdBuf(radeon);
+
+ radeon_destroy_atom_list(radeon);
+
+ if (radeon->state.scissor.pClipRects) {
+ FREE(radeon->state.scissor.pClipRects);
+ radeon->state.scissor.pClipRects = 0;
+ }
}
#ifdef RADEON_BO_TRACK
track = fopen("/tmp/tracklog", "w");
fclose(track);
}
#endif
+ FREE(radeon);
}
/* Force the context `c' to be unbound from its buffer.
};
+#define RADEON_MAX_AOS_ARRAYS 16
+struct radeon_tcl_info {
+ struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
+ GLuint aos_count;
+ struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
+ int elt_dma_offset; /** Offset into this buffer object, in bytes */
+};
+
struct radeon_ioctl {
GLuint vertex_offset;
struct radeon_bo *bo;
#define DEBUG_MEMORY 0x4000
-
typedef void (*radeon_tri_func) (radeonContextPtr,
radeonVertex *,
radeonVertex *, radeonVertex *);
struct radeon_state state;
struct radeon_swtcl_info swtcl;
+ struct radeon_tcl_info tcl;
/* Configuration cache
*/
driOptionCache optionCache;
void (*pre_emit_atoms)(radeonContextPtr rmesa);
void (*pre_emit_state)(radeonContextPtr rmesa);
void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
+ void (*free_context)(GLcontext *ctx);
} vtbl;
};
GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
__DRIdrawablePrivate * driDrawPriv,
__DRIdrawablePrivate * driReadPriv);
+extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
/* ================================================================
* Debugging:
radeon->hw.is_dirty = 1;
}
+static void r100_vtbl_free_context(GLcontext *ctx)
+{
+ r100ContextPtr rmesa = R100_CONTEXT(ctx);
+ _mesa_vector4f_free( &rmesa->tcl.ObjClean );
+}
static void r100_init_vtbl(radeonContextPtr radeon)
{
/* Create the device specific context.
*/
GLboolean
-radeonCreateContext( const __GLcontextModes *glVisual,
+r100CreateContext( const __GLcontextModes *glVisual,
__DRIcontextPrivate *driContextPriv,
void *sharedContextPrivate)
{
}
return GL_TRUE;
}
-
-
-/* Destroy the device specific context.
- */
-/* Destroy the Mesa and driver specific context data.
- */
-void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
-{
- GET_CURRENT_CONTEXT(ctx);
- r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate;
- r100ContextPtr current = ctx ? R100_CONTEXT(ctx) : NULL;
-
- /* check if we're deleting the currently bound context */
- if (rmesa == current) {
- radeon_firevertices(&rmesa->radeon);
- _mesa_make_current(NULL, NULL, NULL);
- }
-
- /* Free radeon context resources */
- assert(rmesa); /* should never be null */
- if ( rmesa ) {
-
- _swsetup_DestroyContext( rmesa->radeon.glCtx );
- _tnl_DestroyContext( rmesa->radeon.glCtx );
- _vbo_DestroyContext( rmesa->radeon.glCtx );
- _swrast_DestroyContext( rmesa->radeon.glCtx );
-
- radeonDestroySwtcl( rmesa->radeon.glCtx );
- radeonReleaseArrays( rmesa->radeon.glCtx, ~0 );
- if (rmesa->radeon.dma.current) {
- radeonReleaseDmaRegion( &rmesa->radeon );
- rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
- }
-
- _mesa_vector4f_free( &rmesa->tcl.ObjClean );
-
- if (rmesa->radeon.state.scissor.pClipRects) {
- FREE(rmesa->radeon.state.scissor.pClipRects);
- rmesa->radeon.state.scissor.pClipRects = NULL;
- }
-
- radeonCleanupContext(&rmesa->radeon);
-
- FREE( rmesa );
- }
-}
-
#define R200_ELT_BUF_SZ (8*1024)
/* radeon_tcl.c
*/
-struct radeon_tcl_info {
+struct r100_tcl_info {
GLuint vertex_format;
GLuint hw_primitive;
*/
GLvector4f ObjClean;
- struct radeon_aos aos[8];
- GLuint nr_aos_components;
-
GLuint *Elts;
- struct radeon_bo *indexed_bo;
-
- int elt_cmd_offset; /** Offset into the cmdbuf */
+ int elt_cmd_offset;
int elt_cmd_start;
int elt_used;
};
/* radeon_tcl.c
*/
- struct radeon_tcl_info tcl;
+ struct r100_tcl_info tcl;
/* radeon_swtcl.c
*/
#define RADEON_OLD_PACKETS 1
-extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
-extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
- __DRIcontextPrivate * driContextPriv,
- void *sharedContextPrivate);
-extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
- __DRIdrawablePrivate * driDrawPriv,
- __DRIdrawablePrivate * driReadPriv);
-extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
-
+extern GLboolean r100CreateContext( const __GLcontextModes *glVisual,
+ __DRIcontextPrivate *driContextPriv,
+ void *sharedContextPrivate);
+
#endif /* __RADEON_CONTEXT_H__ */
rmesa->swtcl.numverts += nverts;
return head;
}
+
+void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
+{
+ radeonContextPtr radeon = RADEON_CONTEXT( ctx );
+ int i;
+
+ if (radeon->tcl.elt_dma_bo) {
+ radeon_bo_unref(radeon->tcl.elt_dma_bo);
+ radeon->tcl.elt_dma_bo = NULL;
+ }
+ for (i = 0; i < radeon->tcl.aos_count; i++) {
+ if (radeon->tcl.aos[i].bo) {
+ radeon_bo_unref(radeon->tcl.aos[i].bo);
+ radeon->tcl.aos[i].bo = NULL;
+ }
+ }
+}
void rcommon_flush_last_swtcl_prim(GLcontext *ctx);
void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize);
+void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs );
#endif
{
#if RADEON_OLD_PACKETS
assert( nr == 1 );
- rmesa->ioctl.bo = rmesa->tcl.aos[0].bo;
+ rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
rmesa->ioctl.vertex_offset =
- (rmesa->tcl.aos[0].offset + offset * rmesa->tcl.aos[0].stride * 4);
+ (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4);
#else
BATCH_LOCALS(&rmesa->radeon);
uint32_t voffset;
if (!rmesa->radeon.radeonScreen->kernel_mm) {
for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
- (rmesa->tcl.aos[i].stride << 8) |
- (rmesa->tcl.aos[i + 1].components << 16) |
- (rmesa->tcl.aos[i + 1].stride << 24));
+ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+ (rmesa->radeon.tcl.aos[i].stride << 8) |
+ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[i].bo,
+ rmesa->radeon.tcl.aos[i].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[i+1].bo,
+ rmesa->radeon.tcl.aos[i+1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
- OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
- (rmesa->tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[nr - 1].bo,
+ rmesa->radeon.tcl.aos[nr - 1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
} else {
for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
- (rmesa->tcl.aos[i].stride << 8) |
- (rmesa->tcl.aos[i + 1].components << 16) |
- (rmesa->tcl.aos[i + 1].stride << 24));
+ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+ (rmesa->radeon.tcl.aos[i].stride << 8) |
+ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH(voffset);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH(voffset);
}
if (nr & 1) {
- OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
- (rmesa->tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH(voffset);
}
for (i = 0; i + 1 < nr; i += 2) {
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[i+0].bo,
+ rmesa->radeon.tcl.aos[i+0].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[i+1].bo,
+ rmesa->radeon.tcl.aos[i+1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[nr-1].bo,
+ rmesa->radeon.tcl.aos[nr-1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
#include "radeon_context.h"
extern void radeonEmitArrays( GLcontext *ctx, GLuint inputs );
-extern void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs );
#endif
rmesa->tcl.vertex_format = vfmt;
}
-
-void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
-{
- r100ContextPtr rmesa = R100_CONTEXT( ctx );
- int i;
-
- for (i = 0; i < rmesa->tcl.nr_aos_components; i++) {
- if (rmesa->tcl.aos[i].bo) {
- radeon_bo_unref(rmesa->tcl.aos[i].bo);
- rmesa->tcl.aos[i].bo = NULL;
- }
- }
-}
break;
if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
- rmesa->tcl.aos[0].bo)
+ rmesa->radeon.tcl.aos[0].bo)
return;
- if (rmesa->tcl.aos[0].bo)
+ if (rmesa->radeon.tcl.aos[0].bo)
radeonReleaseArrays( ctx, ~0 );
radeonAllocDmaRegion( &rmesa->radeon,
- &rmesa->tcl.aos[0].bo,
- &rmesa->tcl.aos[0].offset,
+ &rmesa->radeon.tcl.aos[0].bo,
+ &rmesa->radeon.tcl.aos[0].offset,
VB->Count * setup_tab[i].vertex_size * 4,
4);
setup_tab[i].emit( ctx, 0, VB->Count,
- rmesa->tcl.aos[0].bo->ptr + rmesa->tcl.aos[0].offset);
+ rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset);
- // rmesa->tcl.aos[0].size = setup_tab[i].vertex_size;
- rmesa->tcl.aos[0].stride = setup_tab[i].vertex_size;
+ // rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size;
+ rmesa->radeon.tcl.aos[0].stride = setup_tab[i].vertex_size;
rmesa->tcl.vertex_format = setup_tab[i].vertex_format;
- rmesa->tcl.nr_aos_components = 1;
+ rmesa->radeon.tcl.aos_count = 1;
}
-
-void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
-{
- r100ContextPtr rmesa = R100_CONTEXT( ctx );
- int i;
-
- for (i = 0; i < rmesa->tcl.nr_aos_components; i++) {
- if (rmesa->tcl.aos[i].bo) {
- radeon_bo_unref(rmesa->tcl.aos[i].bo);
- rmesa->tcl.aos[i].bo = NULL;
- }
- }
-}
_mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
}
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
/**
* Choose the appropriate CreateContext function based on the chipset.
* Eventually, all drivers will go through this process.
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
-
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
if (IS_R300_CLASS(screen))
return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
- return GL_FALSE;
-}
-
-/**
- * Choose the appropriate DestroyContext function based on the chipset.
- */
-static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
-{
- radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
-
- if (IS_R300_CLASS(radeon->radeonScreen))
- return r300DestroyContext(driContextPriv);
-}
+#endif
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+ if (IS_R200_CLASS(screen))
+ return r200CreateContext(glVisual, driContextPriv, sharedContextPriv);
+#endif
+#if !RADEON_COMMON
+ return r100CreateContext(glVisual, driContextPriv, sharedContextPriv);
#endif
+ return GL_FALSE;
+}
/**
return 0;
}
-#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
const struct __DriverAPIRec driDriverAPI = {
.InitScreen = radeonInitScreen,
.DestroyScreen = radeonDestroyScreen,
/* DRI2 */
.InitScreen2 = radeonInitScreen2,
};
-#else
-const struct __DriverAPIRec driDriverAPI = {
- .InitScreen = radeonInitScreen,
- .DestroyScreen = radeonDestroyScreen,
- .CreateContext = r200CreateContext,
- .DestroyContext = r200DestroyContext,
- .CreateBuffer = radeonCreateBuffer,
- .DestroyBuffer = radeonDestroyBuffer,
- .SwapBuffers = radeonSwapBuffers,
- .MakeCurrent = radeonMakeCurrent,
- .UnbindContext = radeonUnbindContext,
- .GetSwapInfo = getSwapInfo,
- .GetDrawableMSC = driDrawableGetMSC32,
- .WaitForMSC = driWaitForMSC32,
- .WaitForSBC = NULL,
- .SwapBuffersMSC = NULL,
- .CopySubBuffer = radeonCopySubBuffer,
- .InitScreen2 = radeonInitScreen2,
-};
-#endif
extern void radeonValidateState( GLcontext *ctx );
-extern void radeonPrintDirty( r100ContextPtr rmesa,
- const char *msg );
-
extern void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode );
#define FALLBACK( rmesa, bit, mode ) do { \
/* =============================================================
* State initialization
*/
-
-void radeonPrintDirty( r100ContextPtr rmesa, const char *msg )
-{
- struct radeon_state_atom *l;
-
- fprintf(stderr, msg);
- fprintf(stderr, ": ");
-
- foreach(l, &rmesa->radeon.hw.atomlist) {
- if (l->dirty || rmesa->radeon.hw.all_dirty)
- fprintf(stderr, "%s, ", l->name);
- }
-
- fprintf(stderr, "\n");
-}
-
static int cmdpkt( r100ContextPtr rmesa, int id )
{
drm_radeon_cmd_header_t h;
rmesa->radeon.swtcl.hw_primitive = 0;
}
-
-void radeonDestroySwtcl( GLcontext *ctx )
-{
-}
#include "radeon_context.h"
extern void radeonInitSwtcl( GLcontext *ctx );
-extern void radeonDestroySwtcl( GLcontext *ctx );
extern void radeonChooseRenderState( GLcontext *ctx );
extern void radeonChooseVertexState( GLcontext *ctx );
rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + ELTS_BUFSZ(nr) +
- AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__);
+ AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__);
radeonEmitAOS( rmesa,
- rmesa->tcl.nr_aos_components, 0 );
+ rmesa->radeon.tcl.aos_count, 0 );
return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format,
rmesa->tcl.hw_primitive, nr );
radeonTclPrimitive( ctx, prim, hwprim );
rcommonEnsureCmdBufSpace( &rmesa->radeon,
- AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
+ AOS_BUFSZ(rmesa->radeon.tcl.aos_count) +
rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
radeonEmitAOS( rmesa,
- rmesa->tcl.nr_aos_components,
+ rmesa->radeon.tcl.aos_count,
start );
/* Why couldn't this packet have taken an offset param?