radeonsi: set SPI color formats and CB_SHADER_MASK outside of compilation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index f322c4e3f5a04bdeb694c2eba1fab4804f82288b..85113c00f5bd02737fbc6c4f80db2a0b336d8690 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1302,18 +1302,8 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
        if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
                int cbuf = target - V_008DFC_SQ_EXP_MRT;
 
-               if (cbuf >= 0 && cbuf < 8) {
+               if (cbuf >= 0 && cbuf < 8)
                        compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
-
-                       if (compressed)
-                               si_shader_ctx->shader->spi_shader_col_format |=
-                                       V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
-                       else
-                               si_shader_ctx->shader->spi_shader_col_format |=
-                                       V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
-
-                       si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
-               }
        }
 
        /* Set COMPR flag */

diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index 3d14c79b803a787c1e16d6ba83f1be508e12e145..b89d3b29e690d1e5784f41d5b3396a515e789d7e 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -277,8 +277,6 @@ struct si_shader {
        unsigned                        spi_ps_input_ena;
        unsigned                        float_mode;
        unsigned                        scratch_bytes_per_wave;
-       unsigned                        spi_shader_col_format;
-       unsigned                        cb_shader_mask;
        union si_shader_key             key;
 
        unsigned                nparam;

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 4b007ec887823af45d9c101200eeadd1712f08aa..b08b035f62f7d9656ffc529f3cf7fd9d0bb8bc07 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -387,6 +387,8 @@ static void si_shader_ps(struct si_shader *shader)
        struct tgsi_shader_info *info = &shader->selector->info;
        struct si_pm4_state *pm4;
        unsigned i, spi_ps_in_control;
+       unsigned spi_shader_col_format = 0, cb_shader_mask = 0;
+       unsigned colors_written, export_16bpc;
        unsigned num_sgprs, num_user_sgprs;
        unsigned spi_baryc_cntl = 0;
        uint64_t va;
@@ -422,12 +424,35 @@ static void si_shader_ps(struct si_shader *shader)
                }
        }
 
+       /* Find out what SPI_SHADER_COL_FORMAT and CB_SHADER_MASK should be. */
+       colors_written = info->colors_written;
+       export_16bpc = shader->key.ps.export_16bpc;
+
+       if (info->colors_written == 0x0) {
+               colors_written = 0x1; /* dummy export */
+               export_16bpc = 0;
+       } else if (info->colors_written == 0x1 &&
+                  info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS]) {
+               colors_written |= (1 << (shader->key.ps.last_cbuf + 1)) - 1;
+       }
+
+       while (colors_written) {
+               i = u_bit_scan(&colors_written);
+               if (export_16bpc & (1 << i))
+                       spi_shader_col_format |= V_028714_SPI_SHADER_FP16_ABGR << (4 * i);
+               else
+                       spi_shader_col_format |= V_028714_SPI_SHADER_32_ABGR << (4 * i);
+               cb_shader_mask |= 0xf << (4 * i);
+       }
+
+       /* Set interpolation controls. */
        has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->spi_ps_input_ena) ||
                       G_0286CC_LINEAR_CENTROID_ENA(shader->spi_ps_input_ena);
 
        spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
                            S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
 
+       /* Set registers. */
        si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
        si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
 
@@ -437,9 +462,8 @@ static void si_shader_ps(struct si_shader *shader)
                       info->writes_z ? V_028710_SPI_SHADER_32_R :
                       V_028710_SPI_SHADER_ZERO);
 
-       si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
-                      shader->spi_shader_col_format);
-       si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
+       si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
+       si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
 
        va = shader->bo->gpu_address;
        si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);