scons,arch: Remove simple scalar compatibility.

This was primarily in Alpha where disassmbly output could be compatible
(default off, probably not usd in a long time), and floating point
could be compatible (default on). A small bit had crept into x86 from
long ago which is also removed.

Change-Id: Ibb68b63787f370259bd1613b393e0b057c007704
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25012
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/SConstruct b/SConstruct
index eb3a9e465db5770b1e40aa113842e173eb6e7f90..d8158fa4faf833b6052732b1bb0ba2eda344e528 100755 (executable)
--- a/SConstruct
+++ b/SConstruct
@@ -971,9 +971,6 @@ sticky_vars.AddVariables(
                  sorted(CpuModel.dict.keys())),
     BoolVariable('EFENCE', 'Link with Electric Fence malloc debugger',
                  False),
-    BoolVariable('SS_COMPATIBLE_FP',
-                 'Make floating-point results compatible with SimpleScalar',
-                 False),
     BoolVariable('USE_SSE2',
                  'Compile for SSE2 (-msse2) to get IEEE FP on x86 hosts',
                  False),
@@ -998,9 +995,9 @@ sticky_vars.AddVariables(
     )
 
 # These variables get exported to #defines in config/*.hh (see src/SConscript).
-export_vars += ['USE_FENV', 'SS_COMPATIBLE_FP', 'TARGET_ISA', 'TARGET_GPU_ISA',
-                'CP_ANNOTATE', 'USE_POSIX_CLOCK', 'USE_KVM', 'USE_TUNTAP',
-                'PROTOCOL', 'HAVE_PROTOBUF', 'HAVE_VALGRIND',
+export_vars += ['USE_FENV', 'TARGET_ISA', 'TARGET_GPU_ISA', 'CP_ANNOTATE',
+                'USE_POSIX_CLOCK', 'USE_KVM', 'USE_TUNTAP', 'PROTOCOL',
+                'HAVE_PROTOBUF', 'HAVE_VALGRIND',
                 'HAVE_PERF_ATTR_EXCLUDE_HOST', 'USE_PNG',
                 'NUMBER_BITS_PER_SET', 'USE_HDF5']
 

diff --git a/build_opts/ALPHA b/build_opts/ALPHA
index d1f82ce38574ecf7fe8720d98ebfb4f721c9fd1b..f4e8ae3e1926f97891ce7e1c21f0f657f6fbbf04 100644 (file)
--- a/build_opts/ALPHA
+++ b/build_opts/ALPHA
@@ -1,4 +1,3 @@
 TARGET_ISA = 'alpha'
-SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
 PROTOCOL = 'MI_example'

diff --git a/build_opts/ALPHA_MESI_Two_Level b/build_opts/ALPHA_MESI_Two_Level
index 123b85d83b9d02a82574b74ef6dec671314e79a5..89b0e1b8bfd14edc0f26cbe8dcc3fe23a5d5cf2c 100644 (file)
--- a/build_opts/ALPHA_MESI_Two_Level
+++ b/build_opts/ALPHA_MESI_Two_Level
@@ -1,3 +1,2 @@
-SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
 PROTOCOL = 'MESI_Two_Level'

diff --git a/build_opts/ALPHA_MOESI_CMP_directory b/build_opts/ALPHA_MOESI_CMP_directory
index 816453ea5835d6388fdff4e2d75ea665382a8a0f..ef00ae1562ea9ffbe0997e61ca498199983bf25d 100644 (file)
--- a/build_opts/ALPHA_MOESI_CMP_directory
+++ b/build_opts/ALPHA_MOESI_CMP_directory
@@ -1,3 +1,2 @@
-SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
 PROTOCOL = 'MOESI_CMP_directory'

diff --git a/build_opts/ALPHA_MOESI_CMP_token b/build_opts/ALPHA_MOESI_CMP_token
index 3851c512620e554f1bb10f2c1f7ce7f2c7bd4f12..d3a97edc87944f4c63cc49d11c8ca9ffca9e280f 100644 (file)
--- a/build_opts/ALPHA_MOESI_CMP_token
+++ b/build_opts/ALPHA_MOESI_CMP_token
@@ -1,3 +1,2 @@
-SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
 PROTOCOL = 'MOESI_CMP_token'

diff --git a/build_opts/ALPHA_MOESI_hammer b/build_opts/ALPHA_MOESI_hammer
index 4639cacdaacdfb89e518ac160cf39f49c1345af3..91e01d61e4b48dd82b6597d98e26539c4de835cc 100644 (file)
--- a/build_opts/ALPHA_MOESI_hammer
+++ b/build_opts/ALPHA_MOESI_hammer
@@ -1,3 +1,2 @@
-SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
 PROTOCOL = 'MOESI_hammer'

diff --git a/build_opts/Garnet_standalone b/build_opts/Garnet_standalone
index 46ae29a45b3458fa39c4067e7cca3c3298768c8b..df97b5b31362e050df6c4cc510b4d11ec821f63e 100644 (file)
--- a/build_opts/Garnet_standalone
+++ b/build_opts/Garnet_standalone
@@ -1,4 +1,3 @@
 TARGET_ISA = 'alpha'
-SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
 PROTOCOL = 'Garnet_standalone'

diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa
index 8f641a4b4581b84b7741327ceb406273c25fc097..36418615e921b77dd8f58fa0efa46982c32dcd6d 100644 (file)
--- a/src/arch/alpha/isa/branch.isa
+++ b/src/arch/alpha/isa/branch.isa
@@ -175,13 +175,6 @@ output decoder {{
             ss << ",";
         }
 
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        if (_numSrcRegs == 0 && _numDestRegs == 0) {
-            printReg(ss, 31);
-            ss << ",";
-        }
-#endif
-
         Addr target = pc + 4 + disp;
 
         std::string str;
@@ -200,13 +193,6 @@ output decoder {{
 
         ccprintf(ss, "%-10s ", mnemonic);
 
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        if (_numDestRegs == 0) {
-            printReg(ss, 31);
-            ss << ",";
-        }
-#endif
-
         if (_numDestRegs > 0) {
             printReg(ss, _destRegIdx[0]);
             ss << ",";

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index abf6fb24a9a1c743cddac99b92168d6306e79459..a61db0bca57c3f5324ef7d2ef4de9074f8449582 100644 (file)
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -600,19 +600,11 @@ decode OPCODE default Unknown::unknown() {
         0xb: decode FA {
             31: decode FP_TYPEFUNC {
                 format FloatingPointOperate {
-#if SS_COMPATIBLE_FP
-                    0x0b: sqrts({{
-                        if (Fb < 0.0)
-                            fault = std::make_shared<ArithmeticFault>();
-                        Fc = sqrt(Fb);
-                    }}, FloatSqrtOp);
-#else
                     0x0b: sqrts({{
                         if (Fb_sf < 0.0)
                             fault = std::make_shared<ArithmeticFault>();
                         Fc_sf = sqrt(Fb_sf);
                     }}, FloatSqrtOp);
-#endif
                     0x2b: sqrtt({{
                         if (Fb < 0.0)
                             fault = std::make_shared<ArithmeticFault>();
@@ -644,17 +636,10 @@ decode OPCODE default Unknown::unknown() {
             // check for valid trapping modes here
             0,1,5,7: decode FP_TYPEFUNC {
                    format FloatingPointOperate {
-#if SS_COMPATIBLE_FP
-                       0x00: adds({{ Fc = Fa + Fb; }});
-                       0x01: subs({{ Fc = Fa - Fb; }});
-                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
-                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
-#else
                        0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }});
                        0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }});
                        0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp);
                        0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp);
-#endif
 
                        0x20: addt({{ Fc = Fa + Fb; }});
                        0x21: subt({{ Fc = Fa - Fb; }});

diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 6e03f4654c392fab222861c45b8a0dc51cb39945..99d13acc54fa528b4612ac540fd48cea649699ea 100644 (file)
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -150,7 +150,6 @@ output decoder {{
     {
         std::string mnem_str(mnemonic);
 
-#ifndef SS_COMPATIBLE_DISASSEMBLY
         std::string suffix("");
         suffix += ((_destRegIdx[0].isFloatReg())
                    ? fpTrappingModeSuffix[trappingMode]
@@ -160,7 +159,6 @@ output decoder {{
         if (suffix != "") {
             mnem_str = csprintf("%s/%s", mnemonic, suffix);
         }
-#endif
 
         std::stringstream ss;
         ccprintf(ss, "%-10s ", mnem_str.c_str());

diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 3f7e1a39a76f95ebcf67507a0e30c092fbc1a9ae..ab145ebf66969be716dd9886cf2e60b9fe5173d3 100644 (file)
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -47,7 +47,6 @@ output header {{
 
 #include "arch/alpha/faults.hh"
 #include "arch/alpha/types.hh"
-#include "config/ss_compatible_fp.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"  // some constructors use MemReq flags
@@ -64,7 +63,6 @@ output decoder {{
 #include "base/cprintf.hh"
 #include "base/fenv.hh"
 #include "base/loader/symtab.hh"
-#include "config/ss_compatible_fp.hh"
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
 #include "mem/packet.hh"
 #include "sim/full_system.hh"
@@ -83,7 +81,6 @@ output exec {{
 #include "arch/generic/memhelpers.hh"
 #include "base/cp_annotate.hh"
 #include "base/fenv.hh"
-#include "config/ss_compatible_fp.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "mem/packet.hh"
@@ -215,10 +212,6 @@ def operands {{
 //
 
 output header {{
-// uncomment the following to get SimpleScalar-compatible disassembly
-// (useful for diffing output traces).
-// #define SS_COMPATIBLE_DISASSEMBLY
-
     /**
      * Base class for all Alpha static instructions.
      */
@@ -409,11 +402,7 @@ output decoder {{
     std::string Nop::generateDisassembly(Addr pc,
                                          const SymbolTable *symtab) const
     {
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        return originalDisassembly;
-#else
         return csprintf("%-10s (%s)", "nop", originalDisassembly);
-#endif
     }
 }};
 

diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index 69b8a477b6245486539344882696ebe7196384da..f48cbfee932e9e40c6f760245fa12c18a79c92b5 100644 (file)
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -59,11 +59,7 @@ output decoder {{
     EmulatedCallPal::generateDisassembly(Addr pc,
                                          const SymbolTable *symtab) const
     {
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        return csprintf("%s %s", "call_pal", mnemonic);
-#else
         return csprintf("%-10s %s", "call_pal", mnemonic);
-#endif
     }
 }};
 
@@ -179,9 +175,6 @@ output decoder {{
     std::string
     HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     {
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
-#else
         // HW_LDST_LOCK and HW_LDST_COND are the same bit.
         const char *lock_str =
             (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
@@ -193,7 +186,6 @@ output decoder {{
                         HW_LDST_QUAD ? ",QUAD" : "",
                         HW_LDST_VPTE ? ",VPTE" : "",
                         lock_str);
-#endif
     }
 }};
 

diff --git a/src/arch/alpha/isa/unimp.isa b/src/arch/alpha/isa/unimp.isa
index e5a773d700f481d17e6863c2a3fa88e43b814255..011a90c3c656c2cd527688e228cb8a74bc395ba5 100644 (file)
--- a/src/arch/alpha/isa/unimp.isa
+++ b/src/arch/alpha/isa/unimp.isa
@@ -103,11 +103,7 @@ output decoder {{
     WarnUnimplemented::generateDisassembly(Addr pc,
                                            const SymbolTable *symtab) const
     {
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        return csprintf("%-10s", mnemonic);
-#else
         return csprintf("%-10s (unimplemented)", mnemonic);
-#endif
     }
 }};
 

diff --git a/src/arch/x86/isa/formats/unimp.isa b/src/arch/x86/isa/formats/unimp.isa
index 963e07c77352815e988c31d981357e47e09d3ded..807e40a6a0efd4718beacf48e5a57cdf2e559d7b 100644 (file)
--- a/src/arch/x86/isa/formats/unimp.isa
+++ b/src/arch/x86/isa/formats/unimp.isa
@@ -112,11 +112,7 @@ output decoder {{
     WarnUnimplemented::generateDisassembly(Addr pc,
                                            const SymbolTable *symtab) const
     {
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        return csprintf("%-10s", mnemonic);
-#else
         return csprintf("%-10s (unimplemented)", mnemonic);
-#endif
     }
 }};