radv: Emit VGT_GS_ONCHIP_CNTL for tess on GFX10.

Otherwise hangs are possible. This register was already set for
GS and NGG.

Fixes: 5eaed7ecfce "radv/gfx10: enable support for NAVI10, NAVI12 and NAVI14"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 64bd0d644019ddbc3fa761948d4243cb0d00b6b9..4e9e9e9c9cd1a5e18777ce5e1d4728957772e71b 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3812,6 +3812,14 @@ radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
        else
                radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
                                       tess->ls_hs_config);
+
+       if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
+           !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
+               radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
+                                      S_028A44_ES_VERTS_PER_SUBGRP(250) |
+                                      S_028A44_GS_PRIMS_PER_SUBGRP(126) |
+                                      S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
+       }
 }
 
 static void