log("\n");
log(" maccmap [-unmap] [selection]\n");
log("\n");
- log("This pass maps $macc cells to yosys gate primitives. When the -unmap option is\n");
- log("used then the $macc cell is mapped to $and, $sub, etc. cells instead.\n");
+ log("This pass maps $macc cells to yosys $fa and $alu cells. When the -unmap option\n");
+ log("is used then the $macc cell is mapped to $add, $sub, etc. cells instead.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)