Support more character literals
authorDan Gisselquist <zipcpu@gmail.com>
Thu, 3 May 2018 10:35:01 +0000 (12:35 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 3 May 2018 10:35:01 +0000 (12:35 +0200)
frontends/verilog/verilog_lexer.l

index 32d7738cf05105d97842c28d9b250805329da96d..d12c9ee4eac785abcce4c4d1fa9e6fdb45fa154d 100644 (file)
@@ -241,10 +241,18 @@ YOSYS_NAMESPACE_END
        while (yystr[i]) {
                if (yystr[i] == '\\' && yystr[i + 1]) {
                        i++;
-                       if (yystr[i] == 'n')
+                       if (yystr[i] == 'a')
+                               yystr[i] = '\a';
+                       else if (yystr[i] == 'f')
+                               yystr[i] = '\f';
+                       else if (yystr[i] == 'n')
                                yystr[i] = '\n';
+                       else if (yystr[i] == 'r')
+                               yystr[i] = '\r';
                        else if (yystr[i] == 't')
                                yystr[i] = '\t';
+                       else if (yystr[i] == 'v')
+                               yystr[i] = '\v';
                        else if ('0' <= yystr[i] && yystr[i] <= '7') {
                                yystr[i] = yystr[i] - '0';
                                if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {