Implement zany immediates

diff --git a/riscv/decode.h b/riscv/decode.h
index 2a53f3c76307a4c371b46c0650cb9a074b6f4742..e1a6b7401f8913f2126567429187874d3269c438 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -17,25 +17,8 @@ typedef int64_t sreg_t;
 typedef uint64_t reg_t;
 typedef uint64_t freg_t;
 
-const int OPCODE_BITS = 7;
-
-const int XPRID_BITS = 5;
-const int NXPR = 1 << XPRID_BITS;
-
-const int FPR_BITS = 64;
-const int FPRID_BITS = 5;
-const int NFPR = 1 << FPRID_BITS;
-
-const int IMM_BITS = 12;
-const int IMMLO_BITS = 7;
-const int TARGET_BITS = 25;
-const int FUNCT_BITS = 3;
-const int FUNCTR_BITS = 7;
-const int FFUNCT_BITS = 2;
-const int RM_BITS = 3;
-const int BIGIMM_BITS = 20;
-const int BRANCH_ALIGN_BITS = 1;
-const int JUMP_ALIGN_BITS = 1;
+const int NXPR = 32;
+const int NFPR = 32;
 
 #define FP_RD_NE  0
 #define FP_RD_0   1
@@ -62,62 +45,24 @@ const int JUMP_ALIGN_BITS = 1;
 
 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
 
-// note: bit fields are in little-endian order
-struct itype_t
+class insn_t
 {
-  unsigned opcode : OPCODE_BITS;
-  unsigned funct : FUNCT_BITS;
-  signed imm12 : IMM_BITS;
-  unsigned rs1 : XPRID_BITS;
-  unsigned rd : XPRID_BITS;
-};
-
-struct btype_t
-{
-  unsigned opcode : OPCODE_BITS;
-  unsigned funct : FUNCT_BITS;
-  unsigned immlo : IMMLO_BITS;
-  unsigned rs2 : XPRID_BITS;
-  unsigned rs1 : XPRID_BITS;
-  signed immhi : IMM_BITS-IMMLO_BITS;
-};
-
-struct rtype_t
-{
-  unsigned opcode : OPCODE_BITS;
-  unsigned funct : FUNCT_BITS;
-  unsigned functr : FUNCTR_BITS;
-  unsigned rs2 : XPRID_BITS;
-  unsigned rs1 : XPRID_BITS;
-  unsigned rd : XPRID_BITS;
-};
-
-struct ltype_t
-{
-  unsigned opcode : OPCODE_BITS;
-  signed bigimm : BIGIMM_BITS;
-  unsigned rd : XPRID_BITS;
-};
-
-struct ftype_t
-{
-  unsigned opcode : OPCODE_BITS;
-  unsigned ffunct : FFUNCT_BITS;
-  unsigned rm : RM_BITS;
-  unsigned rs3 : FPRID_BITS;
-  unsigned rs2 : FPRID_BITS;
-  unsigned rs1 : FPRID_BITS;
-  unsigned rd  : FPRID_BITS;
-};
-
-union insn_t
-{
-  itype_t itype;
-  rtype_t rtype;
-  btype_t btype;
-  ltype_t ltype;
-  ftype_t ftype;
-  uint_fast32_t bits;
+public:
+  uint32_t bits() { return b; }
+  reg_t i_imm() { return x(11, 11) | (imm_sign() << 11); }
+  reg_t s_imm() { return x(11, 6) | (x(27, 5) << 6) | (imm_sign() << 11); }
+  reg_t sb_imm() { return (x(12, 5) << 1) | (x(27, 5) << 6) | (x(11, 1) << 11) | (imm_sign() << 12); }
+  reg_t u_imm() { return (x(22, 5) << 12) | (x(7, 3) << 17) | (x(11, 11) << 20) | (imm_sign() << 31); }
+  reg_t uj_imm() { return (x(12, 10) << 1) | (x(11, 1) << 11) | (x(22, 5) << 12) | (x(7, 3) << 17) | (imm_sign() << 20); }
+  uint32_t rd() { return x(27, 5); }
+  uint32_t rs1() { return x(22, 5); }
+  uint32_t rs2() { return x(17, 5); }
+  uint32_t rs3() { return x(12, 5); }
+  uint32_t rm() { return x(9, 3); }
+private:
+  uint32_t b;
+  reg_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
+  reg_t imm_sign() { return -x(10, 1); }
 };
 
 template <class T>
@@ -162,23 +107,17 @@ private:
 
 // helpful macros, etc
 #define MMU (*p->get_mmu())
-#define RS1 p->get_state()->XPR[insn.rtype.rs1]
-#define RS2 p->get_state()->XPR[insn.rtype.rs2]
-#define RD p->get_state()->XPR.write_port(insn.rtype.rd)
-#define FRS1 p->get_state()->FPR[insn.ftype.rs1]
-#define FRS2 p->get_state()->FPR[insn.ftype.rs2]
-#define FRS3 p->get_state()->FPR[insn.ftype.rs3]
-#define FRD p->get_state()->FPR.write_port(insn.ftype.rd)
-#define BIGIMM insn.ltype.bigimm
-#define SIMM insn.itype.imm12
-#define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
-#define SHAMT (insn.itype.imm12 & 0x3F)
-#define SHAMTW (insn.itype.imm12 & 0x1F)
-#define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
-#define JUMP_TARGET (pc + (BIGIMM << JUMP_ALIGN_BITS))
-#define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
-#define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
-#define RM ({ int rm = insn.ftype.rm; \
+#define RS1 p->get_state()->XPR[insn.rs1()]
+#define RS2 p->get_state()->XPR[insn.rs2()]
+#define RD p->get_state()->XPR.write_port(insn.rd())
+#define FRS1 p->get_state()->FPR[insn.rs1()]
+#define FRS2 p->get_state()->FPR[insn.rs2()]
+#define FRS3 p->get_state()->FPR[insn.rs3()]
+#define FRD p->get_state()->FPR.write_port(insn.rd())
+#define SHAMT (insn.i_imm() & 0x3F)
+#define BRANCH_TARGET (pc + insn.sb_imm())
+#define JUMP_TARGET (pc + insn.uj_imm())
+#define RM ({ int rm = insn.rm(); \
               if(rm == 7) rm = (p->get_state()->fsr & FSR_RD) >> FSR_RD_SHIFT; \
               if(rm > 4) throw trap_illegal_instruction(); \
               rm; })

diff --git a/riscv/disasm.cc b/riscv/disasm.cc
index 703b5a69a45a2f1511e2955d1468f1d3d8a7f068..1271a181357dd52d130484fed735a3bedfbecae1 100644 (file)
--- a/riscv/disasm.cc
+++ b/riscv/disasm.cc
@@ -6,320 +6,189 @@
 #include <cstdarg>
 #include <sstream>
 #include <stdlib.h>
+using namespace std;
 
 class arg_t
 {
  public:
-  virtual std::string to_string(insn_t val) const = 0;
+  virtual string to_string(insn_t val) const = 0;
   virtual ~arg_t() {}
 };
 
-static const char* xpr_to_string[] = {
+static const char* xpr[] = {
   "zero", "ra", "s0", "s1",  "s2",  "s3",  "s4",  "s5",
   "s6",   "s7", "s8", "s9", "s10", "s11",  "sp",  "tp",
   "v0",   "v1", "a0", "a1",  "a2",  "a3",  "a4",  "a5",
-  "a6",   "a7", "a8", "a9", "a10", "a11", "a12", "a13"
+  "a6",   "a7", "t0", "t1",  "t2",  "t3",  "t4",  "gp"
 };
 
-static const char* fpr_to_string[] = {
+static const char* fpr[] = {
   "fs0", "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
   "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
   "fv0", "fv1", "fa0",   "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
-  "fa6", "fa7", "fa8",   "fa9", "fa10", "fa11", "fa12", "fa13"
+  "fa6", "fa7", "ft0",   "ft1",  "ft2",  "ft3",  "ft4",  "ft5"
 };
 
-static const char* vxpr_to_string[] = {
+static const char* vxpr[] = {
   "vx0",  "vx1",  "vx2",  "vx3",  "vx4",  "vx5",  "vx6",  "vx7",
   "vx8",  "vx9",  "vx10", "vx11", "vx12", "vx13", "vx14", "vx15",
   "vx16", "vx17", "vx18", "vx19", "vx20", "vx21", "vx22", "vx23",
   "vx24", "vx25", "vx26", "vx27", "vx28", "vx29", "vx30", "vx31"
 };
 
-static const char* vfpr_to_string[] = {
+static const char* vfpr[] = {
   "vf0",  "vf1",  "vf2",  "vf3",  "vf4",  "vf5",  "vf6",  "vf7",
   "vf8",  "vf9",  "vf10", "vf11", "vf12", "vf13", "vf14", "vf15",
   "vf16", "vf17", "vf18", "vf19", "vf20", "vf21", "vf22", "vf23",
   "vf24", "vf25", "vf26", "vf27", "vf28", "vf29", "vf30", "vf31"
 };
 
-class load_address_t : public arg_t
-{
- public:
-  load_address_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    std::stringstream s;
-    s << insn.itype.imm12 << '(' << xpr_to_string[insn.itype.rs1] << ')';
-    return s.str();
+struct : public arg_t {
+  string to_string(insn_t insn) const {
+    return ::to_string((int)insn.i_imm()) + '(' + xpr[insn.rs1()] + ')';
   }
-};
+} load_address;
 
-class store_address_t : public arg_t
-{
- public:
-  store_address_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    std::stringstream s;
-    int32_t imm = (int32_t)insn.btype.immlo;
-    imm |= insn.btype.immhi << IMMLO_BITS;
-    s << imm << '(' << xpr_to_string[insn.itype.rs1] << ')';
-    return s.str();
+struct : public arg_t {
+  string to_string(insn_t insn) const {
+    return ::to_string((int)insn.s_imm()) + '(' + xpr[insn.rs1()] + ')';
   }
-};
+} store_address;
 
-class amo_address_t : public arg_t
-{
- public:
-  amo_address_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    std::stringstream s;
-    s << "0(" << xpr_to_string[insn.itype.rs1] << ')';
-    return s.str();
+struct : public arg_t {
+  string to_string(insn_t insn) const {
+    return string("0(") + xpr[insn.rs1()] + ')';
   }
-};
+} amo_address;
 
-class xrd_reg_t : public arg_t
-{
- public:
-  xrd_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return xpr_to_string[insn.itype.rd];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return xpr[insn.rd()];
   }
-};
+} xrd;
 
-class xrs1_reg_t : public arg_t
-{
- public:
-  xrs1_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return xpr_to_string[insn.itype.rs1];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return xpr[insn.rs1()];
   }
-};
+} xrs1;
 
-class xrs2_reg_t : public arg_t
-{
- public:
-  xrs2_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return xpr_to_string[insn.rtype.rs2];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return xpr[insn.rs2()];
   }
-};
+} xrs2;
 
-class frd_reg_t : public arg_t
-{
- public:
-  frd_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return fpr_to_string[insn.ftype.rd];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return fpr[insn.rd()];
   }
-};
+} frd;
 
-class frs1_reg_t : public arg_t
-{
- public:
-  frs1_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return fpr_to_string[insn.ftype.rs1];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return fpr[insn.rs1()];
   }
-};
+} frs1;
 
-class frs2_reg_t : public arg_t
-{
- public:
-  frs2_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return fpr_to_string[insn.ftype.rs2];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return fpr[insn.rs2()];
   }
-};
+} frs2;
 
-class frs3_reg_t : public arg_t
-{
- public:
-  frs3_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return fpr_to_string[insn.ftype.rs3];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return fpr[insn.rs3()];
   }
-};
+} frs3;
 
-class vxrd_reg_t : public arg_t
-{
- public:
-  vxrd_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return vxpr_to_string[insn.itype.rd];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return vxpr[insn.rd()];
   }
-};
+} vxrd;
 
-class vxrs1_reg_t : public arg_t
-{
- public:
-  vxrs1_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return vxpr_to_string[insn.itype.rs1];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return vxpr[insn.rs1()];
   }
-};
+} vxrs1;
 
-class vfrd_reg_t : public arg_t
-{
- public:
-  vfrd_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return vfpr_to_string[insn.itype.rd];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return vfpr[insn.rd()];
   }
-};
+} vfrd;
 
-class vfrs1_reg_t : public arg_t
-{
- public:
-  vfrs1_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    return vfpr_to_string[insn.itype.rs1];
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return vfpr[insn.rs1()];
   }
-};
+} vfrs1;
 
-class nxregs_reg_t : public arg_t
-{
- public:
-  nxregs_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    std::stringstream s;
-    s << (insn.itype.imm12 & 0x3f);
-    return s.str();
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return ::to_string(insn.i_imm() & 0x3f);
   }
-};
+} nxregs;
 
-class nfregs_reg_t : public arg_t
-{
- public:
-  nfregs_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    std::stringstream s;
-    s << ((insn.itype.imm12 >> 6) & 0x3f);
-    return s.str();
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return ::to_string((insn.i_imm() >> 6) & 0x3f);
   }
-};
+} nfregs;
 
-class pcr_reg_t : public arg_t
-{
- public:
-  pcr_reg_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    std::stringstream s;
-    s << "pcr" << insn.rtype.rs1;
-    return s.str();
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return string("pcr") + xpr[insn.rs1()];
   }
-};
+} pcr;
 
-class imm_t : public arg_t
-{
- public:
-  imm_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
-    std::stringstream s;
-    s << insn.itype.imm12;
-    return s.str();
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return ::to_string((int)insn.i_imm());
   }
-};
+} imm;
 
-class bigimm_t : public arg_t
-{
- public:
-  bigimm_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
     std::stringstream s;
-    s << std::hex << "0x" << insn.ltype.bigimm;
+    s << std::hex << "0x" << ((uint32_t)insn.u_imm() >> 12);
     return s.str();
   }
-};
+} bigimm;
 
-class branch_target_t : public arg_t
-{
- public:
-  branch_target_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
     std::stringstream s;
-    int32_t target = (int32_t)insn.btype.immlo;
-    target |= insn.btype.immhi << IMMLO_BITS;
-    target <<= BRANCH_ALIGN_BITS;
+    int32_t target = insn.sb_imm();
     char sign = target >= 0 ? '+' : '-';
-    s << "pc " << sign << std::hex << " 0x" << abs(target);
+    s << "pc " << sign << ' ' << abs(target);
     return s.str();
   }
-};
+} branch_target;
 
-class jump_target_t : public arg_t
-{
- public:
-  jump_target_t() {}
-  virtual std::string to_string(insn_t insn) const
-  {
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
     std::stringstream s;
-    int32_t target = (int32_t)insn.ltype.bigimm;
-    target <<= JUMP_ALIGN_BITS;
+    int32_t target = insn.sb_imm();
     char sign = target >= 0 ? '+' : '-';
     s << "pc " << sign << std::hex << " 0x" << abs(target);
     return s.str();
   }
-};
+} jump_target;
 
-// workaround for lack of initializer_list in gcc-4.1
 class disasm_insn_t
 {
  public:
-  disasm_insn_t(const char* name, uint32_t match, uint32_t mask)
-  {
-    init(name, match, mask, 0);
-  }
-  disasm_insn_t(const char* name, uint32_t match, uint32_t mask,
-                const arg_t* a0)
-  {
-    init(name, match, mask, 1, a0);
-  }
   disasm_insn_t(const char* name, uint32_t match, uint32_t mask,
-                const arg_t* a0, const arg_t* a1)
-  {
-    init(name, match, mask, 2, a0, a1);
-  }
-  disasm_insn_t(const char* name, uint32_t match, uint32_t mask,
-                const arg_t* a0, const arg_t* a1, const arg_t* a2)
-  {
-    init(name, match, mask, 3, a0, a1, a2);
-  }
-  disasm_insn_t(const char* name, uint32_t match, uint32_t mask,
-                const arg_t* a0, const arg_t* a1, const arg_t* a2,
-                const arg_t* a3)
-  {
-    init(name, match, mask, 4, a0, a1, a2, a3);
-  }
-  disasm_insn_t(const char* name, uint32_t match, uint32_t mask,
-                const arg_t* a0, const arg_t* a1, const arg_t* a2,
-                const arg_t* a3, const arg_t* a4)
-  {
-    init(name, match, mask, 5, a0, a1, a2, a3, a4);
-  }
+                const std::vector<const arg_t*>& args)
+    : match(match), mask(mask), args(args), name(name) {}
 
   bool operator == (insn_t insn) const
   {
-    return (insn.bits & mask) == match;
+    return (insn.bits() & mask) == match;
   }
 
   std::string to_string(insn_t insn) const
@@ -347,18 +216,6 @@ class disasm_insn_t
   uint32_t mask;
   std::vector<const arg_t*> args;
   const char* name;
-
-  void init(const char* name, uint32_t match, uint32_t mask, int n, ...)
-  {
-    va_list vl;
-    va_start(vl, n);
-    for (int i = 0; i < n; i++)
-      args.push_back(va_arg(vl, const arg_t*));
-    va_end(vl);
-    this->match = match;
-    this->mask = mask;
-    this->name = name;
-  }
 };
 
 std::string disassembler::disassemble(insn_t insn)
@@ -369,41 +226,12 @@ std::string disassembler::disassemble(insn_t insn)
 
 disassembler::disassembler()
 {
-  static const xrd_reg_t _xrd_reg, *xrd_reg = &_xrd_reg;
-  static const xrs1_reg_t _xrs1_reg, *xrs1_reg = &_xrs1_reg;
-  static const load_address_t _load_address, *load_address = &_load_address;
-  static const store_address_t _store_address, *store_address = &_store_address;
-  static const amo_address_t _amo_address, *amo_address = &_amo_address;
-  static const xrs2_reg_t _xrs2_reg, *xrs2_reg = &_xrs2_reg;
-  static const frd_reg_t _frd_reg, *frd_reg = &_frd_reg;
-  static const frs1_reg_t _frs1_reg, *frs1_reg = &_frs1_reg;
-  static const frs2_reg_t _frs2_reg, *frs2_reg = &_frs2_reg;
-  static const frs3_reg_t _frs3_reg, *frs3_reg = &_frs3_reg;
-  static const pcr_reg_t _pcr_reg, *pcr_reg = &_pcr_reg;
-  static const imm_t _imm, *imm = &_imm;
-  static const bigimm_t _bigimm, *bigimm = &_bigimm;
-  static const branch_target_t _branch_target, *branch_target = &_branch_target;
-  static const jump_target_t _jump_target, *jump_target = &_jump_target;
-  static const vxrd_reg_t _vxrd_reg, *vxrd_reg = &_vxrd_reg;
-  static const vxrs1_reg_t _vxrs1_reg, *vxrs1_reg = &_vxrs1_reg;
-  static const vfrd_reg_t _vfrd_reg, *vfrd_reg = &_vfrd_reg;
-  static const vfrs1_reg_t _vfrs1_reg, *vfrs1_reg = &_vfrs1_reg;
-  static const nxregs_reg_t _nxregs_reg, *nxregs_reg = &_nxregs_reg;
-  static const nfregs_reg_t _nfregs_reg, *nfregs_reg = &_nfregs_reg;
-
-  insn_t dummy;
-  dummy.bits = -1, dummy.rtype.rs1 = 0;
-  uint32_t mask_rs1 = ~dummy.bits;
-  dummy.bits = -1, dummy.rtype.rs2 = 0;
-  uint32_t mask_rs2 = ~dummy.bits;
-  dummy.bits = -1, dummy.rtype.rd = 0;
-  uint32_t mask_rd = ~dummy.bits;
-  dummy.bits = -1, dummy.itype.imm12 = 0;
-  uint32_t mask_imm = ~dummy.bits;
-  dummy.bits = 0, dummy.itype.rd = 1;
-  uint32_t match_rd_ra = dummy.bits;
-  dummy.bits = 0, dummy.itype.rs1 = 1;
-  uint32_t match_rs1_ra = dummy.bits;
+  const uint32_t mask_rd = 0x1fUL << 27;
+  const uint32_t match_rd_ra = 1UL << 27;
+  const uint32_t mask_rs1 = 0x1fUL << 22;
+  const uint32_t match_rs1_ra = 1UL << 22;
+  const uint32_t mask_rs2 = 0x1fUL << 17;
+  const uint32_t mask_imm = 0xfffUL << 10;
 
   #define DECLARE_INSN(code, match, mask) \
    const uint32_t match_##code = match; \
@@ -415,28 +243,27 @@ disassembler::disassembler()
   #define DISASM_INSN(name, code, extra, ...) \
     add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
   #define DEFINE_NOARG(code) \
-    add_insn(new disasm_insn_t(#code, match_##code, mask_##code));
-  #define DEFINE_DTYPE(code) DISASM_INSN(#code, code, 0, xrd_reg)
-  #define DEFINE_RTYPE(code) DISASM_INSN(#code, code, 0, xrd_reg, xrs1_reg, xrs2_reg)
-  #define DEFINE_ITYPE(code) DISASM_INSN(#code, code, 0, xrd_reg, xrs1_reg, imm)
-  #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, xrd_reg, imm)
-  #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, xrd_reg, xrs1_reg)
-  #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, xrs1_reg)
-  #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, xrd_reg, bigimm)
-  #define DEFINE_BTYPE(code) DISASM_INSN(#code, code, 0, xrs1_reg, xrs2_reg, branch_target)
-  #define DEFINE_B0TYPE(name, code) DISASM_INSN(name, code, mask_rs1 | mask_rs2, branch_target)
-  #define DEFINE_B1TYPE(name, code) DISASM_INSN(name, code, mask_rs2, xrs1_reg, branch_target)
-  #define DEFINE_JTYPE(code) DISASM_INSN(#code, code, 0, xrd_reg, jump_target)
-  #define DEFINE_XLOAD(code) DISASM_INSN(#code, code, 0, xrd_reg, load_address)
-  #define DEFINE_XSTORE(code) DISASM_INSN(#code, code, 0, xrs2_reg, store_address)
-  #define DEFINE_XAMO(code) DISASM_INSN(#code, code, 0, xrd_reg, xrs2_reg, amo_address)
-  #define DEFINE_FLOAD(code) DISASM_INSN(#code, code, 0, frd_reg, load_address)
-  #define DEFINE_FSTORE(code) DISASM_INSN(#code, code, 0, frs2_reg, store_address)
-  #define DEFINE_FRTYPE(code) DISASM_INSN(#code, code, 0, frd_reg, frs1_reg, frs2_reg)
-  #define DEFINE_FR1TYPE(code) DISASM_INSN(#code, code, 0, frd_reg, frs1_reg)
-  #define DEFINE_FR3TYPE(code) DISASM_INSN(#code, code, 0, frd_reg, frs1_reg, frs2_reg, frs3_reg)
-  #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, xrd_reg, frs1_reg)
-  #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, frd_reg, xrs1_reg)
+    add_insn(new disasm_insn_t(#code, match_##code, mask_##code, {}));
+  #define DEFINE_DTYPE(code) DISASM_INSN(#code, code, 0, {&xrd})
+  #define DEFINE_RTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &xrs2})
+  #define DEFINE_ITYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &imm})
+  #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm})
+  #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1})
+  #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1})
+  #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm})
+  #define DEFINE_BTYPE(code) DISASM_INSN(#code, code, 0, {&xrs1, &xrs2, &branch_target})
+  #define DEFINE_B0TYPE(name, code) DISASM_INSN(name, code, mask_rs1 | mask_rs2, {&branch_target})
+  #define DEFINE_B1TYPE(name, code) DISASM_INSN(name, code, mask_rs2, {&xrs1, &branch_target})
+  #define DEFINE_XLOAD(code) DISASM_INSN(#code, code, 0, {&xrd, &load_address})
+  #define DEFINE_XSTORE(code) DISASM_INSN(#code, code, 0, {&xrs2, &store_address})
+  #define DEFINE_XAMO(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs2, &amo_address})
+  #define DEFINE_FLOAD(code) DISASM_INSN(#code, code, 0, {&frd, &load_address})
+  #define DEFINE_FSTORE(code) DISASM_INSN(#code, code, 0, {&frs2, &store_address})
+  #define DEFINE_FRTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2})
+  #define DEFINE_FR1TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1})
+  #define DEFINE_FR3TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2, &frs3})
+  #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &frs1})
+  #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &xrs1})
 
   DEFINE_XLOAD(lb)
   DEFINE_XLOAD(lbu)
@@ -479,7 +306,9 @@ disassembler::disassembler()
   DEFINE_FSTORE(fsw)
   DEFINE_FSTORE(fsd)
 
-  DEFINE_JTYPE(jal);
+  add_insn(new disasm_insn_t("j", match_jal, mask_jal | mask_rd, {&jump_target}));
+  add_insn(new disasm_insn_t("jal", match_jal | match_rd_ra, mask_jal | mask_rd, {&jump_target}));
+  add_insn(new disasm_insn_t("jal", match_jal, mask_jal, {&xrd, &jump_target}));
 
   DEFINE_B0TYPE("b",    beq);
   DEFINE_B1TYPE("beqz", beq);
@@ -497,11 +326,11 @@ disassembler::disassembler()
   DEFINE_LTYPE(auipc);
 
   DEFINE_I2TYPE("jr", jalr);
-  add_insn(new disasm_insn_t("jalr", match_jalr | match_rd_ra, mask_jalr | mask_rd | mask_imm, xrs1_reg));
-  add_insn(new disasm_insn_t("ret", match_jalr | match_rs1_ra, mask_jalr | mask_rd | mask_rs1 | mask_imm));
+  add_insn(new disasm_insn_t("jalr", match_jalr | match_rd_ra, mask_jalr | mask_rd | mask_imm, {&xrs1}));
+  add_insn(new disasm_insn_t("ret", match_jalr | match_rs1_ra, mask_jalr | mask_rd | mask_rs1 | mask_imm, {}));
   DEFINE_ITYPE(jalr);
 
-  add_insn(new disasm_insn_t("nop", match_addi, mask_addi | mask_rd | mask_rs1 | mask_imm));
+  add_insn(new disasm_insn_t("nop", match_addi, mask_addi | mask_rd | mask_rs1 | mask_imm, {}));
   DEFINE_I0TYPE("li", addi);
   DEFINE_I1TYPE("move", addi);
   DEFINE_ITYPE(addi);
@@ -556,11 +385,11 @@ disassembler::disassembler()
   DEFINE_DTYPE(rdtime);
   DEFINE_DTYPE(rdinstret);
 
-  add_insn(new disasm_insn_t("mtpcr", match_mtpcr, mask_mtpcr | mask_rd, xrs2_reg, pcr_reg));
-  add_insn(new disasm_insn_t("mtpcr", match_mtpcr, mask_mtpcr, xrd_reg, xrs2_reg, pcr_reg));
-  add_insn(new disasm_insn_t("mfpcr", match_mfpcr, mask_mfpcr, xrd_reg, pcr_reg));
-  add_insn(new disasm_insn_t("setpcr", match_setpcr, mask_setpcr, xrd_reg, pcr_reg, imm));
-  add_insn(new disasm_insn_t("clearpcr", match_clearpcr, mask_clearpcr, xrd_reg, pcr_reg, imm));
+  add_insn(new disasm_insn_t("mtpcr", match_mtpcr, mask_mtpcr | mask_rd, {&xrs2, &pcr}));
+  add_insn(new disasm_insn_t("mtpcr", match_mtpcr, mask_mtpcr, {&xrd, &xrs2, &pcr}));
+  add_insn(new disasm_insn_t("mfpcr", match_mfpcr, mask_mfpcr, {&xrd, &pcr}));
+  add_insn(new disasm_insn_t("setpcr", match_setpcr, mask_setpcr, {&xrd, &pcr, &imm}));
+  add_insn(new disasm_insn_t("clearpcr", match_clearpcr, mask_clearpcr, {&xrd, &pcr, &imm}));
   DEFINE_NOARG(eret)
 
   DEFINE_FRTYPE(fadd_s);
@@ -623,20 +452,20 @@ disassembler::disassembler()
   DEFINE_FXTYPE(flt_d);
   DEFINE_FXTYPE(fle_d);
 
-  add_insn(new disasm_insn_t("fssr", match_fssr, mask_fssr | mask_rd, xrs1_reg));
-  add_insn(new disasm_insn_t("fssr", match_fssr, mask_fssr, xrd_reg, xrs1_reg));
+  add_insn(new disasm_insn_t("fssr", match_fssr, mask_fssr | mask_rd, {&xrs1}));
+  add_insn(new disasm_insn_t("fssr", match_fssr, mask_fssr, {&xrd, &xrs1}));
   DEFINE_DTYPE(frsr);
 
   // provide a default disassembly for all instructions as a fallback
   #define DECLARE_INSN(code, match, mask) \
-   add_insn(new disasm_insn_t(#code " (args unknown)", match, mask));
+   add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {}));
   #include "opcodes.h"
   #undef DECLARE_INSN
 }
 
 const disasm_insn_t* disassembler::lookup(insn_t insn)
 {
-  size_t idx = insn.bits % HASH_SIZE;
+  size_t idx = insn.bits() % HASH_SIZE;
   for (size_t j = 0; j < chain[idx].size(); j++)
     if(*chain[idx][j] == insn)
       return chain[idx][j];

diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index 88881e5aec6561853fed1c45fec349deae6a6e57..d6994bac679ad82c6af6fc0d375f4c0ba33907f5 100644 (file)
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 + SIMM);
+RD = sext_xprlen(RS1 + insn.i_imm());

diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index 23ae2788407d8721196b69b284e845a62f04ef0d..a0608ed989946e3e48fd60954c4e9355e01b84fa 100644 (file)
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(SIMM + RS1);
+RD = sext32(insn.i_imm() + RS1);

diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 5caea164fbf0175f2d40f351157c1fb74f215109..713692ea925f77f389c7a1e1b397174cc40becb1 100644 (file)
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RD = SIMM & RS1;
+RD = insn.i_imm() & RS1;

diff --git a/riscv/insns/auipc.h b/riscv/insns/auipc.h
index 48480cdc185fdf0b7736e7898b5b06a901394e1c..1c75a406cfd4755ce7bfda202f81601761e15c57 100644 (file)
--- a/riscv/insns/auipc.h
+++ b/riscv/insns/auipc.h
@@ -1 +1 @@
-RD = sext_xprlen(sext32(BIGIMM << IMM_BITS) + pc);
+RD = sext_xprlen(insn.u_imm() + pc);

diff --git a/riscv/insns/clearpcr.h b/riscv/insns/clearpcr.h
index 56c3584dd54ee32b9e325baa83c9ee3e985412cc..33e0c318ee23beee7525d8049c1a946036e2294b 100644 (file)
--- a/riscv/insns/clearpcr.h
+++ b/riscv/insns/clearpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rtype.rs1, p->get_pcr(insn.rtype.rs1) & ~SIMM);
+RD = p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) & ~insn.i_imm());

diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index 2704a4d25ad7ebee82b29aaf4f5f49f160732e06..54d4a779e9eefe9840ae27eb8126b9baf2647610 100644 (file)
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = MMU.load_int64(ITYPE_EADDR);
+FRD = MMU.load_int64(RS1 + insn.i_imm());

diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index afab6364a1ea0fb51bf47f571e2e18160842f22c..1559ecc51237f96b31bbcb1b9e9aba145ff179ae 100644 (file)
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = MMU.load_int32(ITYPE_EADDR);
+FRD = MMU.load_int32(RS1 + insn.i_imm());

diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 0e1c38ade5932115affba44b52ae2282db22c76a..fe90a6b6320f46707108e80b2c05ca626e6eb235 100644 (file)
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,2 +1,2 @@
 require_fp;
-MMU.store_uint64(BTYPE_EADDR, FRS2);
+MMU.store_uint64(RS1 + insn.s_imm(), FRS2);

diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index c921123f6c9a5d8c67df3299c39e2253c9f31e68..85c8091ab16af0a2c8d15f86310dc2b5ee27fb98 100644 (file)
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,2 +1,2 @@
 require_fp;
-MMU.store_uint32(BTYPE_EADDR, FRS2);
+MMU.store_uint32(RS1 + insn.s_imm(), FRS2);

diff --git a/riscv/insns/jalr.h b/riscv/insns/jalr.h
index 6f17ab16209d5c62555b03185328f2765789a611..fa6d7f1fdb04b4e70307c309f4ab7a46022c9853 100644 (file)
--- a/riscv/insns/jalr.h
+++ b/riscv/insns/jalr.h
@@ -1,3 +1,3 @@
 reg_t temp = RS1;
 RD = npc;
-set_pc((temp + SIMM) & ~1);
+set_pc((temp + insn.i_imm()) & ~1);

diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index 56a5f32ea6ce37ed1d8af315132872f2d1e4f48c..36acd7bd719063ccf3012ea48ed5efe02e5205fa 100644 (file)
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RD = MMU.load_int8(ITYPE_EADDR);
+RD = MMU.load_int8(RS1 + insn.i_imm());

diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index 66621c0653bf0198687eb1112dd95e0bb8a25467..f1e94723fa76dc2d2609e188efca51dff0febe65 100644 (file)
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RD = MMU.load_uint8(ITYPE_EADDR);
+RD = MMU.load_uint8(RS1 + insn.i_imm());

diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index f2142946ab52eab5d71f13a4fdaf7aa721d0bcfa..e57daac9b483430fd06b0de5f35b7f255321be9e 100644 (file)
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = MMU.load_int64(ITYPE_EADDR);
+RD = MMU.load_int64(RS1 + insn.i_imm());

diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index fea2a8e17d94ea77bb56674ca30a313fd09536a4..b158ada1b499cec3ed10268cd1d24bc71c915bef 100644 (file)
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-RD = MMU.load_int16(ITYPE_EADDR);
+RD = MMU.load_int16(RS1 + insn.i_imm());

diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 71c21be48967bddd95b3adcf283f00acdae8891e..842a7527f65e2ae5dcf898cf234ed834298716e7 100644 (file)
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RD = MMU.load_uint16(ITYPE_EADDR);
+RD = MMU.load_uint16(RS1 + insn.i_imm());

diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h
index 6af2a2a32c97df03c0c7e6323a7488d85d900fe5..8dce543216513ed543c57cd3661046d8973bf83d 100644 (file)
--- a/riscv/insns/lui.h
+++ b/riscv/insns/lui.h
@@ -1 +1 @@
-RD = sext32(BIGIMM << IMM_BITS);
+RD = insn.u_imm();

diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 77f735e688bc1eb7e5a742f8d624f4fdcdcf8fa7..1b4ea3519d9daac9665899cdbf21cd04a073acfc 100644 (file)
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RD = MMU.load_int32(ITYPE_EADDR);
+RD = MMU.load_int32(RS1 + insn.i_imm());

diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index e731178eee98db120a3a3f503bd45e786e11abde..6c4ad769da911f5f2117708a965a89ae62b5e0fa 100644 (file)
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = MMU.load_uint32(ITYPE_EADDR);
+RD = MMU.load_uint32(RS1 + insn.i_imm());

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 0f23426e508c3c8680ba93a33b925aa4270ffdd0..f711931d466794056c1657652053e3fe1a18a8c3 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->get_pcr(insn.rtype.rs1);
+RD = p->get_pcr(insn.rs1());

diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index 770dfd5aab015da90f9c1abf8cd25eefdc03bb22..2d4121f5da1f10e2d2db17d5c9248480b76461a0 100644 (file)
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rtype.rs1, RS2);
+RD = p->set_pcr(insn.rs1(), RS2);

diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index 9561b971f4b92ffe63249b21a8e510314ca58a63..695a56ba0ecec63e8c7528c1708b038c4c113394 100644 (file)
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RD = SIMM | RS1;
+RD = insn.i_imm() | RS1;

diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index db4d523aeb7d85b236c21a2c318c5d3ffe14e766..8729c2d47f46f5884e4d88ea4cb95e2e0a49c54f 100644 (file)
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-MMU.store_uint8(BTYPE_EADDR, RS2);
+MMU.store_uint8(RS1 + insn.s_imm(), RS2);

diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 24c0de9a06423498d4c8c9b45e79de6ba6987e92..9364d875bded2d0e951f029efb8cf2cb3cb9d52a 100644 (file)
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
 require_xpr64;
-MMU.store_uint64(BTYPE_EADDR, RS2);
+MMU.store_uint64(RS1 + insn.s_imm(), RS2);

diff --git a/riscv/insns/setpcr.h b/riscv/insns/setpcr.h
index 4a25d80bef86ef68835d2356e448a7c34043f4fc..287667073ded742027a13f31f5bd21b7a2680f08 100644 (file)
--- a/riscv/insns/setpcr.h
+++ b/riscv/insns/setpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rtype.rs1, p->get_pcr(insn.rtype.rs1) | SIMM);
+RD = p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) | insn.i_imm());

diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
index 69234dce212e8c7a70f0aabde1ecab14804e2a11..22aa3a889e58db8294691bfb97b116fd567daba1 100644 (file)
--- a/riscv/insns/sh.h
+++ b/riscv/insns/sh.h
@@ -1 +1 @@
-MMU.store_uint16(BTYPE_EADDR, RS2);
+MMU.store_uint16(RS1 + insn.s_imm(), RS2);

diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index 1f6e50dfb52195764c2d1aa21b504874f4073279..8ef4ae782fb2b2f67df810ad64437fbbd5af8a1a 100644 (file)
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 << SHAMTW);
+RD = sext32(RS1 << SHAMT);

diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 1dcd8927fac7dbc8fdbd87391fef1d816c44cd80..51873f3b7c0a62d45fd6c483812b5abc8768c501 100644 (file)
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(SIMM));
+RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(insn.i_imm()));

diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index 45e579b518d151d221769949df6510787c100eac..924fc929d32ae7c8ffa0d1f9ab5c7bfea6b0e873 100644 (file)
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-RD = cmp_trunc(RS1) < cmp_trunc(SIMM);
+RD = cmp_trunc(RS1) < cmp_trunc(insn.i_imm());

diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index 4c5673007d1dcd9e4d169136c7df2ed8a5041908..f43b3fb46fa3e5b62ec0fa738f14f770517450de 100644 (file)
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(int32_t(RS1) >> SHAMTW);
+RD = sext32(int32_t(RS1) >> SHAMT);

diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index c400507570fd3adc08fbd69191b5101b7a43f2b4..2ee1be0b57e521cb50c3e53c7e01c2acec73055d 100644 (file)
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32((uint32_t)RS1 >> SHAMTW);
+RD = sext32((uint32_t)RS1 >> SHAMT);

diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
index 81ca71dd40ed6602463a2177785a89b6cb3fc9f0..aa5ead372e57b31785dc1a2a1ebc681197660869 100644 (file)
--- a/riscv/insns/sw.h
+++ b/riscv/insns/sw.h
@@ -1 +1 @@
-MMU.store_uint32(BTYPE_EADDR, RS2);
+MMU.store_uint32(RS1 + insn.s_imm(), RS2);

diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index 5852aaca4b8fb2d5505822e6b1dda2f5ddf4ade9..4eba2334b4f4633b0a9649444aebdbde08a80d7a 100644 (file)
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RD = SIMM ^ RS1;
+RD = insn.i_imm() ^ RS1;

diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index 33efcfbc0e47559c117c70448133ca7b965765f7..a1b7dd05cfc341dc054142c20913bc06056de4c5 100644 (file)
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -258,12 +258,16 @@ void sim_t::interactive_until(const std::string& cmd, const std::vector<std::str
 
   while (1)
   {
-    reg_t current = (this->*func)(args2);
+    try
+    {
+      reg_t current = (this->*func)(args2);
 
-    if (cmd_until == (current == val))
-      break;
-    if (ctrlc_pressed)
-      break;
+      if (cmd_until == (current == val))
+        break;
+      if (ctrlc_pressed)
+        break;
+    }
+    catch (trap_t t) {}
 
     step(1, false);
   }

diff --git a/riscv/mmu.h b/riscv/mmu.h
index b69de9c9020670f29e63e0bc78c5e82d8f7163b4..227d5c700ecd6edc6c2d54ac81a382b0e51cad00 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -68,28 +68,31 @@ public:
   struct insn_fetch_t
   {
     insn_func_t func;
-    insn_t insn;
+    union {
+      insn_t insn;
+      uint_fast32_t pad;
+    } insn;
   };
 
   // load instruction from memory at aligned address.
   inline insn_fetch_t load_insn(reg_t addr)
   {
-    reg_t idx = (addr/sizeof(insn_t::itype)) % ICACHE_ENTRIES;
+    reg_t idx = (addr/sizeof(insn_t)) % ICACHE_ENTRIES;
     if (unlikely(icache_tag[idx] != addr))
     {
-      reg_t paddr = translate(addr, sizeof(insn_t::itype), false, true);
+      reg_t paddr = translate(addr, sizeof(insn_t), false, true);
       insn_fetch_t fetch;
-      fetch.insn.itype = *(decltype(insn_t::itype)*)(mem + paddr);
-      fetch.func = proc->decode_insn(fetch.insn);
+      fetch.insn.insn = *(insn_t*)(mem + paddr);
+      fetch.func = proc->decode_insn(fetch.insn.insn);
 
-      reg_t idx = (paddr/sizeof(insn_t::itype)) % ICACHE_ENTRIES;
+      reg_t idx = (paddr/sizeof(insn_t)) % ICACHE_ENTRIES;
       icache_tag[idx] = addr;
       icache_data[idx] = fetch;
 
-      if (tracer.interested_in_range(paddr, paddr + sizeof(insn_t::itype), false, true))
+      if (tracer.interested_in_range(paddr, paddr + sizeof(insn_t), false, true))
       {
         icache_tag[idx] = -1;
-        tracer.trace(paddr, sizeof(insn_t::itype), false, true);
+        tracer.trace(paddr, sizeof(insn_t), false, true);
       }
     }
     return icache_data[idx];

diff --git a/riscv/opcodes.h b/riscv/opcodes.h
index 8b0c5e320aeecc8bef0ad1079779cc6676e070f7..b18efbbea28d9a0db89c9fe9dbcba6111a347e86 100644 (file)
--- a/riscv/opcodes.h
+++ b/riscv/opcodes.h
@@ -4,7 +4,7 @@ DECLARE_INSN(fmin_d, 0x180d3, 0x1ffff)
 DECLARE_INSN(lr_w, 0x412b, 0x3e7fff)
 DECLARE_INSN(bltu, 0x363, 0x3ff)
 DECLARE_INSN(fmin_s, 0x18053, 0x1ffff)
-DECLARE_INSN(slliw, 0x9b, 0x3f83ff)
+DECLARE_INSN(slliw, 0x9b, 0x3f07ff)
 DECLARE_INSN(lb, 0x3, 0x3ff)
 DECLARE_INSN(fcvt_s_wu, 0xf053, 0x3ff1ff)
 DECLARE_INSN(fcvt_d_l, 0xc0d3, 0x3ff1ff)
@@ -27,7 +27,7 @@ DECLARE_INSN(break, 0xf7, 0xffffffff)
 DECLARE_INSN(fcvt_s_w, 0xe053, 0x3ff1ff)
 DECLARE_INSN(mul, 0x433, 0x1ffff)
 DECLARE_INSN(amominu_d, 0x19ab, 0x7fff)
-DECLARE_INSN(srli, 0x293, 0x3f03ff)
+DECLARE_INSN(srli, 0x293, 0x3e07ff)
 DECLARE_INSN(amominu_w, 0x192b, 0x7fff)
 DECLARE_INSN(divuw, 0x6bb, 0x1ffff)
 DECLARE_INSN(mulw, 0x43b, 0x1ffff)
@@ -51,13 +51,13 @@ DECLARE_INSN(eret, 0x273, 0xffffffff)
 DECLARE_INSN(blt, 0x263, 0x3ff)
 DECLARE_INSN(sc_w, 0x452b, 0x7fff)
 DECLARE_INSN(rem, 0x733, 0x1ffff)
-DECLARE_INSN(srliw, 0x29b, 0x3f83ff)
+DECLARE_INSN(srliw, 0x29b, 0x3f07ff)
 DECLARE_INSN(lui, 0x37, 0x7f)
 DECLARE_INSN(fcvt_s_lu, 0xd053, 0x3ff1ff)
 DECLARE_INSN(addi, 0x13, 0x3ff)
 DECLARE_INSN(mulh, 0x4b3, 0x1ffff)
 DECLARE_INSN(fmul_s, 0x2053, 0x1f1ff)
-DECLARE_INSN(srai, 0x10293, 0x3f03ff)
+DECLARE_INSN(srai, 0x693, 0x3e07ff)
 DECLARE_INSN(amoand_d, 0x9ab, 0x7fff)
 DECLARE_INSN(flt_d, 0x160d3, 0x1ffff)
 DECLARE_INSN(sraw, 0x102bb, 0x1ffff)
@@ -71,7 +71,7 @@ DECLARE_INSN(feq_s, 0x15053, 0x1ffff)
 DECLARE_INSN(fsgnjx_d, 0x70d3, 0x1ffff)
 DECLARE_INSN(sra, 0x102b3, 0x1ffff)
 DECLARE_INSN(bge, 0x2e3, 0x3ff)
-DECLARE_INSN(sraiw, 0x1029b, 0x3f83ff)
+DECLARE_INSN(sraiw, 0x69b, 0x3f07ff)
 DECLARE_INSN(srl, 0x2b3, 0x1ffff)
 DECLARE_INSN(fsub_d, 0x10d3, 0x1f1ff)
 DECLARE_INSN(fsgnjx_s, 0x7053, 0x1ffff)
@@ -113,7 +113,7 @@ DECLARE_INSN(remu, 0x7b3, 0x1ffff)
 DECLARE_INSN(flw, 0x107, 0x3ff)
 DECLARE_INSN(remw, 0x73b, 0x1ffff)
 DECLARE_INSN(sltu, 0x1b3, 0x1ffff)
-DECLARE_INSN(slli, 0x93, 0x3f03ff)
+DECLARE_INSN(slli, 0x93, 0x3e07ff)
 DECLARE_INSN(amoor_w, 0xd2b, 0x7fff)
 DECLARE_INSN(beq, 0x63, 0x3ff)
 DECLARE_INSN(fld, 0x187, 0x3ff)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 266bda6db77bfa93be51be38d9bc0ed0d63b9798..2bd215566cebfd5bd5da31a872b860ed59415842 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -102,8 +102,8 @@ void processor_t::step(size_t n, bool noisy)
     #define execute_insn(noisy) \
       do { \
         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
-        if(noisy) disasm(fetch.insn, npc); \
-        npc = fetch.func(this, fetch.insn, npc); \
+        if(noisy) disasm(fetch.insn.insn, npc); \
+        npc = fetch.func(this, fetch.insn.insn, npc); \
       } while(0)
 
     if(noisy) for( ; i < n; i++) // print out instructions as we go
@@ -167,8 +167,8 @@ void processor_t::disasm(insn_t insn, reg_t pc)
 {
   // the disassembler is stateless, so we share it
   static disassembler disasm;
-  fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIxFAST32 ") %s\n",
-          id, state.pc, insn.bits, disasm.disassemble(insn).c_str());
+  fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
+          id, state.pc, insn.bits(), disasm.disassemble(insn).c_str());
 }
 
 reg_t processor_t::set_pcr(int which, reg_t val)
@@ -291,9 +291,9 @@ insn_func_t processor_t::decode_insn(insn_t insn)
 {
   bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 
-  auto key = insn.bits & ((1L << opcode_bits)-1);
+  auto key = insn.bits() & ((1L << opcode_bits)-1);
   for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
-    if ((insn.bits & it->second.mask) == it->second.match)
+    if ((insn.bits() & it->second.mask) == it->second.match)
       return rv64 ? it->second.rv64 : it->second.rv32;
 
   return &illegal_instruction;

diff --git a/riscv/sim.cc b/riscv/sim.cc
index f01e931ea6eb24f153feabdb1f84e5283dfe5d97..864ec09c4694fb2e51c1d4960f647ccd8c3e2b30 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -76,6 +76,7 @@ void sim_t::run()
 {
   while (!htif->done())
   {
+    htif->tick();
     if (debug || ctrlc_pressed)
       interactive();
     else
@@ -99,8 +100,6 @@ void sim_t::step(size_t n, bool noisy)
         current_proc = 0;
 
       htif->tick();
-      if (!running())
-        break;
     }
   }
 }