ac/surface/gfx6: explicitly support S8 surfaces

This is needed by radv for dEQP-VK.renderpass.simple.stencil

Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index d77b490c0195e6060be5087e6bb6771936081f10..51e15d07d3cd4019ae764be6898ea1723cbbb1e5 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -386,6 +386,31 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
        return index;
 }
 
+/**
+ * Copy surface-global settings like pipe/bank config from level 0 surface
+ * computation.
+ */
+static void gfx6_surface_settings(const struct radeon_info* info,
+                                 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
+                                 struct radeon_surf *surf)
+{
+       surf->surf_alignment = csio->baseAlign;
+       surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
+       gfx6_set_micro_tile_mode(surf, info);
+
+       /* For 2D modes only. */
+       if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
+               surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
+               surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
+               surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
+               surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
+               surf->u.legacy.num_banks = csio->pTileInfo->banks;
+               surf->u.legacy.macro_tile_index = csio->macroModeIndex;
+       } else {
+               surf->u.legacy.macro_tile_index = 0;
+       }
+}
+
 /**
  * Fill in the tiling information in \p surf based on the given surface config.
  *
@@ -584,30 +609,22 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
        surf->htile_slice_size = 0;
        surf->htile_alignment = 1;
 
+       const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
+                                 !(surf->flags & RADEON_SURF_ZBUFFER);
+
        /* Calculate texture layout information. */
-       for (level = 0; level < config->info.levels; level++) {
-               r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
-                                      &AddrSurfInfoIn, &AddrSurfInfoOut,
-                                      &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
-               if (r)
-                       return r;
+       if (!only_stencil) {
+               for (level = 0; level < config->info.levels; level++) {
+                       r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
+                                              &AddrSurfInfoIn, &AddrSurfInfoOut,
+                                              &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
+                       if (r)
+                               return r;
 
-               if (level == 0) {
-                       surf->surf_alignment = AddrSurfInfoOut.baseAlign;
-                       surf->u.legacy.pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
-                       gfx6_set_micro_tile_mode(surf, info);
-
-                       /* For 2D modes only. */
-                       if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
-                               surf->u.legacy.bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
-                               surf->u.legacy.bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
-                               surf->u.legacy.mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
-                               surf->u.legacy.tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
-                               surf->u.legacy.num_banks = AddrSurfInfoOut.pTileInfo->banks;
-                               surf->u.legacy.macro_tile_index = AddrSurfInfoOut.macroModeIndex;
-                       } else {
-                               surf->u.legacy.macro_tile_index = 0;
-                       }
+                       if (level > 0)
+                               continue;
+
+                       gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
                }
        }
 
@@ -629,11 +646,19 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
                                return r;
 
                        /* DB uses the depth pitch for both stencil and depth. */
-                       if (surf->u.legacy.stencil_level[level].nblk_x !=
-                           surf->u.legacy.level[level].nblk_x)
-                               surf->u.legacy.stencil_adjusted = true;
+                       if (!only_stencil) {
+                               if (surf->u.legacy.stencil_level[level].nblk_x !=
+                                   surf->u.legacy.level[level].nblk_x)
+                                       surf->u.legacy.stencil_adjusted = true;
+                       } else {
+                               surf->u.legacy.level[level].nblk_x =
+                                       surf->u.legacy.stencil_level[level].nblk_x;
+                       }
 
                        if (level == 0) {
+                               if (only_stencil)
+                                       gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
+
                                /* For 2D modes only. */
                                if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
                                        surf->u.legacy.stencil_tile_split =