sim: make sure replaced memory signals are always in VCD signal set

diff --git a/migen/sim/core.py b/migen/sim/core.py
index d531ee90cca89ef51ba53926d9fe1c8e6d254776..3329e8e39b890c1ce483820eed5883cfaa9141dc 100644 (file)
--- a/migen/sim/core.py
+++ b/migen/sim/core.py
@@ -237,6 +237,8 @@ class Simulator:
                 signals.add(cd.clk)
                 if cd.rst is not None:
                     signals.add(cd.rst)
+            for memory_array in mta.replacements.values():
+                signals |= set(memory_array)
             signals = sorted(signals, key=lambda x: x.duid)
             self.vcd = VCDWriter(vcd_name, signals)