allow 4 CSR entries to be set at a time, on RV64

diff --git a/riscv/processor.cc b/riscv/processor.cc
index b95c03083e6eb54c158dd9b30cc14eec509e77f6..d87da2521c3ccbf4fbda771c736375d7e097bafd 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -374,10 +374,16 @@ void processor_t::set_csr(int which, reg_t val)
       fprintf(stderr, "set REGCFG %d %lx\n", tbidx, val);
       // lower 16 bits go into even, upper into odd...
       state.sv_csrs[tbidx].u = get_field(val, 0xffff);
-      state.sv_csrs[tbidx+1].u = get_field(val, 0xffff0000);
+      state.sv_csrs[tbidx+1].u = get_field(val, 0xffff<<16);
+      int clroffset = 0;
+      if (xlen == 64)
+      {
+          state.sv_csrs[tbidx+2].u = get_field(val, 0xffff<<32);
+          state.sv_csrs[tbidx+3].u = get_field(val, 0xffff<<48);
+      }
       // clear out all CSRs above the one(s) being set: this ensures that
       // when it comes to context-switching, it's clear what needs to be saved
-      for (int i = tbidx+2; i < 16; i++)
+      for (int i = tbidx+clroffset; i < 16; i++)
       {
           fprintf(stderr, "clr REGCFG %d\n", i);
           state.sv_csrs[i].u = 0;
@@ -429,7 +435,13 @@ void processor_t::set_csr(int which, reg_t val)
       int tbidx = (which - CSR_SVPREDCFG0) * 2;
       state.sv_pred_csrs[tbidx].u = get_field(val, 0xffff);
       state.sv_pred_csrs[tbidx+1].u = get_field(val, 0xffff0000);
-      for (int i = tbidx+2; i < 16; i++)
+      int clroffset = 0;
+      if (xlen == 64)
+      {
+          state.sv_pred_csrs[tbidx+2].u = get_field(val, 0xffff<<32);
+          state.sv_pred_csrs[tbidx+3].u = get_field(val, 0xffff<<48);
+      }
+      for (int i = tbidx+clroffset; i < 16; i++)
       {
           state.sv_pred_csrs[i].u = 0;
       }