If init is 1'bx, do not add to dict as per @cliffordwolf

diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 48390488eff98faddc995c4b4f7a43e143bfef41..0ad33dc0eda6c057649d17d7dc3fb24fc9255f24 100644 (file)
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -102,7 +102,8 @@ struct DffinitPass : public Pass {
                                if (wire->attributes.count("\\init")) {
                                        Const value = wire->attributes.at("\\init");
                                        for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
-                                               init_bits[sigmap(SigBit(wire, i))] = value[i];
+                                               if (value[i] != State::Sx)
+                                                       init_bits[sigmap(SigBit(wire, i))] = value[i];
                                }
                                if (wire->port_output)
                                        for (auto bit : sigmap(wire))