#ifndef R600_ASM_H
#define R600_ASM_H
-#include "radeon.h"
#include "util/u_double_list.h"
#define NUM_OF_CYCLES 3
unsigned inst;
unsigned last;
unsigned is_op3;
- unsigned predicate;
+ unsigned predicate;
unsigned nliteral;
unsigned literal_added;
- unsigned bank_swizzle;
- unsigned bank_swizzle_force;
+ unsigned bank_swizzle;
+ unsigned bank_swizzle_force;
u32 value[4];
int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
};
unsigned addr;
unsigned ndw;
unsigned id;
- unsigned cond;
- unsigned pop_count;
- unsigned cf_addr; /* control flow addr */
- unsigned kcache0_mode;
+ unsigned cond;
+ unsigned pop_count;
+ unsigned cf_addr; /* control flow addr */
+ unsigned kcache0_mode;
struct list_head alu;
struct list_head tex;
struct list_head vtx;
struct r600_bc_output output;
- struct r600_bc_alu *curr_bs_head;
+ struct r600_bc_alu *curr_bs_head;
};
#define FC_NONE 0
#define FC_PUSH_WQM 5
struct r600_cf_stack_entry {
- int type;
- struct r600_bc_cf *start;
- struct r600_bc_cf **mid; /* used to store the else point */
- int num_mid;
+ int type;
+ struct r600_bc_cf *start;
+ struct r600_bc_cf **mid; /* used to store the else point */
+ int num_mid;
};
#define SQ_MAX_CALL_DEPTH 0x00000020
struct r600_cf_callstack {
- unsigned fc_sp_before_entry;
- int sub_desc_index;
- int current;
- int max;
+ unsigned fc_sp_before_entry;
+ int sub_desc_index;
+ int current;
+ int max;
};
struct r600_bc {
enum radeon_family family;
- int chiprev; /* 0 - r600, 1 - r700, 2 - evergreen */
- unsigned use_mem_constant;
+ int chiprev; /* 0 - r600, 1 - r700, 2 - evergreen */
+ unsigned use_mem_constant;
struct list_head cf;
struct r600_bc_cf *cf_last;
unsigned ndw;
unsigned ncf;
unsigned ngpr;
- unsigned nstack;
+ unsigned nstack;
unsigned nresource;
unsigned force_add_cf;
u32 *bytecode;
-
- u32 fc_sp;
- struct r600_cf_stack_entry fc_stack[32];
-
- unsigned call_sp;
- struct r600_cf_callstack callstack[SQ_MAX_CALL_DEPTH];
+ u32 fc_sp;
+ struct r600_cf_stack_entry fc_stack[32];
+ unsigned call_sp;
+ struct r600_cf_callstack callstack[SQ_MAX_CALL_DEPTH];
};
int r600_bc_init(struct r600_bc *bc, enum radeon_family family);
int r600_bc_build(struct r600_bc *bc);
int r600_bc_add_cfinst(struct r600_bc *bc, int inst);
int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type);
+
#endif
}
}
-static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_resource_texture *rtex)
+static void r600_setup_miptree(struct r600_resource_texture *rtex)
{
struct pipe_resource *ptex = &rtex->resource.base.b;
unsigned long w, h, pitch, size, layer_size, i, offset;
{
struct r600_resource_texture *rtex;
struct r600_resource *resource;
- struct r600_screen *rscreen = r600_screen(screen);
+ struct radeon *radeon = (struct radeon *)screen->winsys;
rtex = CALLOC_STRUCT(r600_resource_texture);
if (!rtex) {
resource->base.vtbl = &r600_texture_vtbl;
pipe_reference_init(&resource->base.b.reference, 1);
resource->base.b.screen = screen;
- r600_setup_miptree(rscreen, rtex);
+ r600_setup_miptree(rtex);
/* FIXME alignment 4096 enought ? too much ? */
resource->domain = r600_domain_from_usage(resource->base.b.bind);
- resource->bo = radeon_bo(rscreen->rw, 0, rtex->size, 4096, NULL);
+ resource->bo = radeon_bo(radeon, 0, rtex->size, 4096, NULL);
if (resource->bo == NULL) {
FREE(rtex);
return NULL;
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
struct r600_resource *resource = &rtex->resource;
- struct r600_screen *rscreen = r600_screen(screen);
+ struct radeon *radeon = (struct radeon *)screen->winsys;
if (resource->bo) {
- radeon_bo_decref(rscreen->rw, resource->bo);
+ radeon_bo_decref(radeon, resource->bo);
}
if (rtex->uncompressed) {
- radeon_bo_decref(rscreen->rw, rtex->uncompressed);
+ radeon_bo_decref(radeon, rtex->uncompressed);
}
r600_texture_destroy_state(ptex);
FREE(rtex);
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
struct radeon_bo *bo;
enum pipe_format format = transfer->resource->format;
- struct r600_screen *rscreen = r600_screen(ctx->screen);
+ struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
struct r600_resource_texture *rtex;
unsigned long offset = 0;
char *map;
transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
}
- if (radeon_bo_map(rscreen->rw, bo)) {
+ if (radeon_bo_map(radeon, bo)) {
return NULL;
}
- radeon_bo_wait(rscreen->rw, bo);
+ radeon_bo_wait(radeon, bo);
map = bo->data;
return map + offset;
struct pipe_transfer* transfer)
{
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct r600_screen *rscreen = r600_screen(ctx->screen);
+ struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
struct r600_resource_texture *rtex;
struct radeon_bo *bo;
bo = ((struct r600_resource *)transfer->resource)->bo;
}
}
- radeon_bo_unmap(rscreen->rw, bo);
+ radeon_bo_unmap(radeon, bo);
}
struct u_resource_vtbl r600_texture_vtbl =
default:
break;
}
-
+
/* S3TC formats. TODO */
if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
goto out_unknown;