/* Nonzero if tuning for XScale */
int arm_tune_xscale = 0;
-/* Nonzero if we want to tune for stores that access the write-buffer.
+/* Nonzero if we want to tune for stores that access the write-buffer.
This typically means an ARM6 or ARM7 with MMU or MPU. */
int arm_tune_wbuf = 0;
options. */
if (i == ARM_OPT_SET_ARCH)
target_arch_cpu = sel->core;
-
+
if (i != ARM_OPT_SET_TUNE)
{
/* If we have been given an architecture and a processor
const_ok_for_arm (HOST_WIDE_INT i)
{
int lowbit;
-
+
/* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
be all zero, or all one. */
if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
return FALSE;
i &= (unsigned HOST_WIDE_INT) 0xffffffff;
-
+
/* Fast return for 0 and small values. We must do this for zero, since
the code below can't handle that one case. */
if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
gen_rtx_SET (VOIDmode, target, source));
return 1;
}
-
+
/* We don't know how to handle other cases yet. */
gcc_assert (remainder == 0xffffffff);
-
+
if (generate)
emit_constant_insn (cond,
gen_rtx_SET (VOIDmode, target,
temp1 = 0x80000000 >> (topshift - 1);
temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
-
+
if (const_ok_for_arm (temp2))
{
if (generate)
mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
}
}
-
+
return LIBCALL_VALUE(mode);
}
-/* Determine the amount of memory needed to store the possible return
+/* Determine the amount of memory needed to store the possible return
registers of an untyped call. */
int
arm_apply_result_size (void)
attribute. */
static tree
-arm_handle_notshared_attribute (tree *node,
- tree name ATTRIBUTE_UNUSED,
- tree args ATTRIBUTE_UNUSED,
- int flags ATTRIBUTE_UNUSED,
+arm_handle_notshared_attribute (tree *node,
+ tree name ATTRIBUTE_UNUSED,
+ tree args ATTRIBUTE_UNUSED,
+ int flags ATTRIBUTE_UNUSED,
bool *no_add_attrs)
{
tree decl = TYPE_NAME (*node);
}
gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
-
+
base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
base == reg ? 0 : reg);
&& current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
&& cfun->args_info.nregs < 4)
return LAST_ARG_REGNUM;
-
+
/* Otherwise look for a call-saved register that is going to be pushed. */
for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
if (pushed_regs_mask & (1 << reg))
}
rtx
-thumb_legitimize_reload_address(rtx *x_p,
- enum machine_mode mode,
- int opnum, int type,
- int ind_levels ATTRIBUTE_UNUSED)
+thumb_legitimize_reload_address (rtx *x_p,
+ enum machine_mode mode,
+ int opnum, int type,
+ int ind_levels ATTRIBUTE_UNUSED)
{
rtx x = *x_p;
-
+
if (GET_CODE (x) == PLUS
&& GET_MODE_SIZE (mode) < 4
&& REG_P (XEXP (x, 0))
return NULL;
}
-
\f
-
#define REG_OR_SUBREG_REG(X) \
(GET_CODE (X) == REG \
|| (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
return 1;
}
-/* Generate a memory reference for a half word, such that it will be loaded
- into the top 16 bits of the word. We can assume that the address is
- known to be alignable and of the form reg, or plus (reg, const). */
-
/* Select a dominance comparison mode if possible for a test of the general
form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
COND_OR == DOM_CC_X_AND_Y => (X && Y)
case LT:
if (cond_or == DOM_CC_X_AND_Y)
return CC_DLTmode;
-
+
switch (cond2)
{
case LT:
case GTU:
if (cond_or == DOM_CC_X_AND_Y)
return CC_DGTUmode;
-
+
switch (cond2)
{
case GTU:
return !BYTES_BIG_ENDIAN;
}
-
\f
/* Print a symbolic form of X to the debug file, F. */
static void
{
rtx lowpart, highpart;
enum machine_mode mode;
-
+
mode = GET_MODE (val);
if (mode == VOIDmode)
mode = DImode;
gcc_assert (GET_MODE_SIZE (mode) == 8);
-
+
lowpart = gen_lowpart (SImode, val);
highpart = gen_highpart_mode (SImode, mode, val);
-
+
gcc_assert (GET_CODE (lowpart) == CONST_INT);
gcc_assert (GET_CODE (highpart) == CONST_INT);
if (mode == VOIDmode)
mode = DImode;
-
+
part = gen_highpart_mode (SImode, mode, val);
-
+
gcc_assert (GET_CODE (part) == CONST_INT);
-
+
if (const_ok_for_arm (INTVAL (part))
|| const_ok_for_arm (~INTVAL (part)))
return true;
-
+
part = gen_lowpart (SImode, val);
-
+
gcc_assert (GET_CODE (part) == CONST_INT);
-
+
if (const_ok_for_arm (INTVAL (part))
|| const_ok_for_arm (~INTVAL (part)))
return true;
-
+
return false;
}
case REG:
output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
break;
-
+
case PRE_INC:
gcc_assert (TARGET_LDRD);
output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
break;
-
+
case PRE_DEC:
output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
break;
-
+
case POST_INC:
output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
break;
-
+
case POST_DEC:
gcc_assert (TARGET_LDRD);
output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
break;
-
+
case PRE_MODIFY:
case POST_MODIFY:
otherops[0] = operands[0];
otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
-
+
if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
{
if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
}
break;
-
+
case LABEL_REF:
case CONST:
output_asm_insn ("adr%?\t%0, %1", operands);
output_asm_insn ("ldm%?ia\t%0, %M0", operands);
break;
-
+
default:
if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
otherops[0] = operands[0];
otherops[1] = XEXP (XEXP (operands[1], 0), 0);
otherops[2] = XEXP (XEXP (operands[1], 0), 1);
-
+
if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
{
if (GET_CODE (otherops[2]) == CONST_INT)
avoid a conflict. */
otherops[1] = XEXP (XEXP (operands[1], 0), 1);
otherops[2] = XEXP (XEXP (operands[1], 0), 0);
-
}
/* If both registers conflict, it will usually
have been fixed by a splitter. */
output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops);
return "";
}
-
+
if (GET_CODE (otherops[2]) == CONST_INT)
{
if (!(const_ok_for_arm (INTVAL (otherops[2]))))
/* If we aren't loading the PIC register,
don't stack it even though it may be live. */
if (flag_pic
- && !TARGET_SINGLE_PIC_BASE
+ && !TARGET_SINGLE_PIC_BASE
&& (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
|| current_function_uses_pic_offset_table))
save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
else
{
gcc_assert (seeking_return || arm_ccfsm_state == 2);
-
+
while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
{
this_insn = next_nonnote_insn (this_insn);
if (frame_pointer_needed)
{
amount = offsets->outgoing_args - offsets->locals_base;
-
+
if (amount < 1024)
insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
stack_pointer_rtx, GEN_INT (amount)));
emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
amount = offsets->locals_base - offsets->saved_regs;
}
-
+
if (amount)
{
if (amount < 512)
{
case REG:
operands[2] = adjust_address (operands[1], SImode, 4);
-
+
if (REGNO (operands[0]) == REGNO (addr))
{
output_asm_insn ("ldr\t%H0, %2", operands);
case CONST:
/* Compute <address> + 4 for the high order load. */
operands[2] = adjust_address (operands[1], SImode, 4);
-
+
output_asm_insn ("ldr\t%0, %1", operands);
output_asm_insn ("ldr\t%H0, %2", operands);
break;
{
/* Compute <address> + 4 for the high order load. */
operands[2] = adjust_address (operands[1], SImode, 4);
-
/* If the computed address is held in the low order register
then load the high order register first, otherwise always
DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
DECL_VISIBILITY_SPECIFIED (decl) = 1;
}
-
+
static bool
arm_cxx_class_data_always_comdat (void)
{
|| GET_CODE (XEXP (e, 0)) != MEM
|| GET_CODE (XEXP (e, 1)) != REG)
abort ();
-
+
reg = REGNO (XEXP (e, 1));
if (reg < lastreg)
abort ();
-
+
if (i != 1)
fprintf (asm_out_file, ", ");
/* We can't use %r for vfp because we need to use the
{
HOST_WIDE_INT offset;
unsigned reg;
-
+
if (GET_CODE (e1) == PLUS)
{
if (GET_CODE (XEXP (e1, 0)) != REG
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