Fixed a bug in AST frontend for cases with non-blocking assigned variables as case...

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 36074be34830a334b1f451956a7e129c2175ec4a..cb57bbab794399a712bf0d84a53049cad5160545 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -337,9 +337,9 @@ struct AST_INTERNAL::ProcessGenerator
                        reg.sort_and_unify();
        }
 
-       // remove all assignments to the given signal pattern in a case and all its children
-       // when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
-       // function is acalled to clean up the first two assignments as they are overwritten by
+       // remove all assignments to the given signal pattern in a case and all its children.
+       // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
+       // function is called to clean up the first two assignments as they are overwritten by
        // the third assignment.
        void removeSignalFromCaseTree(RTLIL::SigSpec pattern, RTLIL::CaseRule *cs)
        {
@@ -461,7 +461,7 @@ struct AST_INTERNAL::ProcessGenerator
                                                } else if (node->type == AST_BLOCK) {
                                                        processAst(node);
                                                } else if (!generated_default_case)
-                                                       current_case->compare.push_back(node->genWidthRTLIL(sw->signal.width));
+                                                       current_case->compare.push_back(node->genWidthRTLIL(sw->signal.width, &subst_rvalue_from, &subst_rvalue_to));
                                        }
                                        sw->cases.push_back(current_case);
                                        current_case = backup_case;

diff --git a/tests/simple/process.v b/tests/simple/process.v
index 532586649d7e8faede5e0425ccc2b0d0baac78ac..8cb4c870e4f355d12b712ebef4439e62bfff6808 100644 (file)
--- a/tests/simple/process.v
+++ b/tests/simple/process.v
@@ -1,4 +1,23 @@
 
+module blocking_cond (in, out);
+
+input in;
+output reg out;
+reg tmp;
+
+always @* begin
+       tmp = 1;
+       out = 1'b0;
+       case (1'b1)
+               tmp: out = in;
+       endcase
+       tmp = 0;
+end
+
+endmodule
+
+// -------------------------------------------------------------
+
 module uut(clk, arst, a, b, c, d, e, f,  out1);
 
 input clk, arst, a, b, c, d, e, f;